JP2003519835A - ウェイ予測がミスした時にサーチを方向付けるための、予測されないウェイからの部分的なタグを提供するキャッシュ - Google Patents

ウェイ予測がミスした時にサーチを方向付けるための、予測されないウェイからの部分的なタグを提供するキャッシュ

Info

Publication number
JP2003519835A
JP2003519835A JP2001550564A JP2001550564A JP2003519835A JP 2003519835 A JP2003519835 A JP 2003519835A JP 2001550564 A JP2001550564 A JP 2001550564A JP 2001550564 A JP2001550564 A JP 2001550564A JP 2003519835 A JP2003519835 A JP 2003519835A
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JP
Japan
Prior art keywords
way
cache
address
tag
partial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001550564A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003519835A5 (enExample
Inventor
ケラー，ジェイムズ・ビィ
シャケル，キース・アール
シャーマ，プニート
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2003519835A publication Critical patent/JP2003519835A/ja
Publication of JP2003519835A5 publication Critical patent/JP2003519835A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/608—Details relating to cache mapping
    • G06F2212/6082—Way prediction in set-associative cache
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2001550564A 2000-01-03 2000-08-08 ウェイ予測がミスした時にサーチを方向付けるための、予測されないウェイからの部分的なタグを提供するキャッシュ Pending JP2003519835A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/476,577 US6687789B1 (en) 2000-01-03 2000-01-03 Cache which provides partial tags from non-predicted ways to direct search if way prediction misses
US09/476,577 2000-01-03
PCT/US2000/021756 WO2001050272A1 (en) 2000-01-03 2000-08-08 Cache which provides partial tags from non-predicted ways to direct search if way prediction misses

Publications (2)

Publication Number Publication Date
JP2003519835A true JP2003519835A (ja) 2003-06-24
JP2003519835A5 JP2003519835A5 (enExample) 2007-09-20

Family

ID=23892412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001550564A Pending JP2003519835A (ja) 2000-01-03 2000-08-08 ウェイ予測がミスした時にサーチを方向付けるための、予測されないウェイからの部分的なタグを提供するキャッシュ

Country Status (7)

Country Link
US (1) US6687789B1 (enExample)
EP (1) EP1244970B1 (enExample)
JP (1) JP2003519835A (enExample)
KR (1) KR100747127B1 (enExample)
CN (1) CN1208726C (enExample)
DE (1) DE60003235T2 (enExample)
WO (1) WO2001050272A1 (enExample)

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WO2011049051A1 (ja) * 2009-10-20 2011-04-28 国立大学法人電気通信大学 キャッシュメモリおよびその制御方法
US7945766B2 (en) 2008-03-21 2011-05-17 Fujitsu Limited Conditional execution of floating point store instruction by simultaneously reading condition code and store data from multi-port register file

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US6944713B2 (en) * 2002-06-18 2005-09-13 Intel Corporation Low power set associative cache
US20040054867A1 (en) * 2002-09-13 2004-03-18 Paulus Stravers Translation lookaside buffer
US6973557B2 (en) * 2003-02-04 2005-12-06 Sun Microsystems, Inc. Apparatus and method for dual access to a banked and pipelined data cache memory unit
US20040181626A1 (en) * 2003-03-13 2004-09-16 Pickett James K. Partial linearly tagged cache memory system
TWI246658B (en) * 2003-04-25 2006-01-01 Ip First Llc Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status
US20040243767A1 (en) * 2003-06-02 2004-12-02 Cierniak Michal J. Method and apparatus for prefetching based upon type identifier tags
US7117290B2 (en) * 2003-09-03 2006-10-03 Advanced Micro Devices, Inc. MicroTLB and micro tag for reducing power in a processor
US20050050278A1 (en) * 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. Low power way-predicted cache
US7085894B2 (en) * 2003-09-11 2006-08-01 International Business Machines Corporation Selectively accepting cache content
US6961276B2 (en) * 2003-09-17 2005-11-01 International Business Machines Corporation Random access memory having an adaptable latency
US7669009B2 (en) * 2004-09-23 2010-02-23 Intel Corporation Method and apparatus for run-ahead victim selection to reduce undesirable replacement behavior in inclusive caches
KR100688503B1 (ko) * 2004-11-02 2007-03-02 삼성전자주식회사 브랜치 목적 어드레스를 이용하여 캐쉬 웨이를 예측하는프로세서 및 그 방법
US7707387B2 (en) 2005-06-01 2010-04-27 Microsoft Corporation Conditional execution via content addressable memory and parallel computing execution model
US7793040B2 (en) * 2005-06-01 2010-09-07 Microsoft Corporation Content addressable memory architecture
US20060277352A1 (en) * 2005-06-07 2006-12-07 Fong Pong Method and system for supporting large caches with split and canonicalization tags
US20060274787A1 (en) * 2005-06-07 2006-12-07 Fong Pong Adaptive cache design for MPT/MTT tables and TCP context
US9946547B2 (en) 2006-09-29 2018-04-17 Arm Finance Overseas Limited Load/store unit for a processor, and applications thereof
US7594079B2 (en) * 2006-09-29 2009-09-22 Mips Technologies, Inc. Data cache virtual hint way prediction, and applications thereof
US20100332762A1 (en) * 2009-06-30 2010-12-30 Moga Adrian C Directory cache allocation based on snoop response information
US8392665B2 (en) 2010-09-25 2013-03-05 Intel Corporation Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines
CN102193875B (zh) * 2011-04-26 2013-08-14 北京工业大学 多核下基于Cache划分的自适应路预测算法
US20120297256A1 (en) * 2011-05-20 2012-11-22 Qualcomm Incorporated Large Ram Cache
US8458447B2 (en) * 2011-06-17 2013-06-04 Freescale Semiconductor, Inc. Branch target buffer addressing in a data processor
US9460016B2 (en) 2014-06-16 2016-10-04 Analog Devices Global Hamilton Cache way prediction
KR102354990B1 (ko) * 2014-09-17 2022-01-24 삼성전자주식회사 캐시 메모리 시스템 및 그 동작방법
US9846648B2 (en) 2015-05-11 2017-12-19 Intel Corporation Create page locality in cache controller cache allocation
GB2553102B (en) * 2016-08-19 2020-05-20 Advanced Risc Mach Ltd A memory unit and method of operation of a memory unit to handle operation requests
US10324850B2 (en) 2016-11-11 2019-06-18 Microsoft Technology Licensing, Llc Serial lookup of tag ways
GB2560336B (en) * 2017-03-07 2020-05-06 Imagination Tech Ltd Address generators for verifying integrated circuit hardware designs for cache memory
US10565122B2 (en) 2017-05-30 2020-02-18 Microsoft Technology Licensing, Llc Serial tag lookup with way-prediction
US10545875B2 (en) 2017-12-27 2020-01-28 Advanced Micro Devices, Inc. Tag accelerator for low latency DRAM cache
US11507174B2 (en) 2020-02-25 2022-11-22 Qualcomm Incorporated System physical address size aware cache memory
CN111988444B (zh) * 2020-08-19 2022-10-18 成都安可信电子股份有限公司 一种同步总线快速搜索终端地址搜索方法
US11928472B2 (en) 2020-09-26 2024-03-12 Intel Corporation Branch prefetch mechanisms for mitigating frontend branch resteers
CN114691542A (zh) * 2020-12-25 2022-07-01 瑞昱半导体股份有限公司 数据处理装置与其数据存取电路
US12182317B2 (en) 2021-02-13 2024-12-31 Intel Corporation Region-based deterministic memory safety
US11593001B1 (en) * 2021-08-02 2023-02-28 Nvidia Corporation Using per memory bank load caches for reducing power use in a system on a chip
US12235791B2 (en) 2021-08-23 2025-02-25 Intel Corporation Loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing

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JPS63163939A (ja) * 1986-12-26 1988-07-07 Nippon Telegr & Teleph Corp <Ntt> キヤツシユメモリの制御方法
JPH02156352A (ja) * 1988-12-09 1990-06-15 Hitachi Ltd キャッシュメモリ
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JPS62293596A (ja) * 1986-06-12 1987-12-21 Matsushita Electric Ind Co Ltd 連想記憶装置
JPS63163939A (ja) * 1986-12-26 1988-07-07 Nippon Telegr & Teleph Corp <Ntt> キヤツシユメモリの制御方法
JPH02156352A (ja) * 1988-12-09 1990-06-15 Hitachi Ltd キャッシュメモリ
JPH05120135A (ja) * 1991-10-25 1993-05-18 Oki Electric Ind Co Ltd キヤツシユ制御方式
JPH0721785A (ja) * 1993-06-29 1995-01-24 Kawasaki Steel Corp 半導体メモリ
JPH07334423A (ja) * 1994-06-07 1995-12-22 Hitachi Ltd セットアソシアティブ方式のメモリ装置
JPH08263370A (ja) * 1995-03-27 1996-10-11 Toshiba Microelectron Corp キャッシュメモリシステム
JPH1139216A (ja) * 1997-07-24 1999-02-12 Hitachi Ltd 半導体記憶装置及びキャッシュメモリシステム

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7945766B2 (en) 2008-03-21 2011-05-17 Fujitsu Limited Conditional execution of floating point store instruction by simultaneously reading condition code and store data from multi-port register file
WO2011049051A1 (ja) * 2009-10-20 2011-04-28 国立大学法人電気通信大学 キャッシュメモリおよびその制御方法
JP5622155B2 (ja) * 2009-10-20 2014-11-12 国立大学法人電気通信大学 キャッシュメモリおよびその制御方法
US8904111B2 (en) 2009-10-20 2014-12-02 The University Of Electro-Communications Cache memory with CAM and SRAM sub-tags and generation control

Also Published As

Publication number Publication date
KR100747127B1 (ko) 2007-08-09
EP1244970B1 (en) 2003-06-04
CN1415092A (zh) 2003-04-30
EP1244970A1 (en) 2002-10-02
US6687789B1 (en) 2004-02-03
DE60003235T2 (de) 2004-04-08
WO2001050272A1 (en) 2001-07-12
DE60003235D1 (de) 2003-07-10
CN1208726C (zh) 2005-06-29
KR20020067596A (ko) 2002-08-22

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