KR100706837B1 - Flip-flop circuit - Google Patents

Abstract

The flip-flop circuit of the present invention includes a pulse generator for generating a pulse signal in response to a clock and a pre-generated output signal, and a controller for controlling the potential level of the precharge terminal in response to the input of the pulse signal and the clock and the input signal. And a latch unit for latching the potential of the precharge terminal and a signal output unit for controlling and outputting a logic value of the output signal according to a potential level of the output signal of the precharge terminal and the latch unit.

Flip-Flop, Pulse Signal, Precharge Terminals

Description

Flip-Flop Circuit

1 is a schematic configuration diagram of a flip-flop circuit according to the prior art,

2 is a detailed configuration diagram of the flip-flop circuit shown in FIG.

3 is a block diagram showing the configuration of a flip-flop circuit according to the present invention;

4 is a detailed configuration diagram of the flip-flop circuit shown in FIG.

5A and 5B are timing diagrams for describing an operation of a flip-flop circuit according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: signal input unit 20/60: signal output unit

30: pulse generator 40: controller

50: latch portion

The present invention relates to a flip-flop circuit, and more particularly, to a flip-flop circuit for reducing power consumption.

In general, a flip-flop circuit is a circuit that maintains a state when two stable states are applied to one stable state input until a stable input of the other is applied thereafter. Such a flip-flop circuit is mainly used in a semiconductor integrated circuit. In a semiconductor integrated circuit to which a clock is input, a synchronous flip-flop circuit that performs input / output operations of a signal in synchronization with a clock is used.

Hereinafter, a flip-flop circuit according to the related art will be described with reference to FIGS. 1 and 2.

1 is a schematic configuration diagram of a flip-flop circuit according to the related art, which shows a synchronous S-R flip-flop circuit, commonly referred to as a sense amplifier type. Hereinafter, the Set terminal and the Reset terminal, which are precharge terminals, will be referred to as the S terminal and the R terminal, respectively. The terminal having the opposite phase of the S terminal will be referred to as the / S terminal, Terminals having the opposite phase will be expressed as / R terminals.

As shown, the flip-flop circuit includes a signal input unit 10 and an S terminal for controlling potential levels of the S terminal and the R terminal in response to the input of the clock clk and the input signal pairs A and / A. And a signal output section 20 for controlling and outputting the potential levels of the output signal pairs Q and / Q corresponding to the potential levels of the R terminal.

In the flip-flop circuit configured as described above, if the potential of the clock clk is at a low level, the signal input unit 10 may be connected to the S terminal regardless of a logic value of the input signal pairs A and / A. And the potential of the R terminal is controlled to a low level. The signal output unit 20 then maintains the logic values of the output signal pairs Q and / Q previously.

However, when the potential of the clock clk rises to a high level, the potential levels of the S terminal and the R terminal are determined by logic values of the input signal pairs A and / A. That is, when the logic value of the input signal pairs A and / A is (1, 0), the potential of the S terminal is at a high level, and the potential of the R terminal is at a low level. Accordingly, the logic value of the output signal pair Q, / Q becomes (1, 0), which is maintained until the next rising edge time of the clock clk. Similarly, when the logic value of the input signal pairs A and / A is (0, 1), the potential of the S terminal is at a low level, and the potential of the R terminal is at a high level. Accordingly, the logic value of the output signal pair Q, / Q becomes (0, 1), which is maintained until the next rising edge time of the clock clk.

A more detailed description of the flip-flop circuit will be made with reference to the accompanying drawings.

FIG. 2 is a detailed block diagram of the flip-flop circuit shown in FIG. 1.

As shown in the drawing, the signal input unit 10 includes a first transistor TR1 having a clock input to a gate terminal, a driving voltage Vdrv applied to a source terminal, and a drain terminal connected to the / S terminal; The second transistor TR2 receives the clock clk at the gate terminal, the driving voltage Vdrv is applied at the source terminal, and the drain terminal is connected to the / R terminal, and the clock clk is input at the gate terminal. A third transistor TR3 having a drain terminal connected to the first node N1, a source terminal connected to the ground terminal, a gate terminal connected to the / R terminal, and a driving voltage Vdrv applied to the source terminal; A fourth transistor TR4 connected to the / S terminal, a fifth transistor having a gate terminal connected to the / S terminal, the driving voltage Vdrv applied to a source terminal, and a drain terminal connected to the / R terminal; TR5), the gate terminal is connected to the / R terminal and A sixth transistor TR6 having a lane end connected to the / S terminal, a source end connected to a second node N2, a gate end connected to the / S terminal, and a drain end connected to the / R terminal, A seventh transistor TR7 having a terminal connected to a third node N3, an input signal A is input to a gate terminal, a drain terminal connected to the second node N2, and a source terminal connected to the first node N1. An ninth transistor TR8 connected to the gate terminal, an input signal / A is input to a gate terminal, a drain terminal thereof is connected to the third node N3, and a source terminal thereof is connected to the first node N1 ( TR9), the driving voltage Vdrv is input to a gate terminal, and a drain terminal and a source terminal are respectively connected to the second node N2 and the third node N3, and the / S terminal. The first inverter IV1 and the / R which inverts the signal transmitted from the second terminal to the S terminal By inverting the signal transmitted from the party it is composed of the second inverter (IV2) for transmitting to the R terminal.

The signal output unit 20 includes an eleventh transistor TR11 having a gate terminal connected to the R terminal, a drain terminal connected to an output terminal Q, and a source terminal grounded, a gate terminal connected to the S terminal, and a drain terminal connected to the R terminal. A twelfth transistor TR12 connected to the output terminal / Q and having a source terminal grounded, a gate terminal connected to the / S terminal, the driving voltage Vdrv applied to a source terminal, and a drain terminal connected to the Q terminal; The thirteenth transistor TR13 is connected to the / Q terminal, and the fourteenth transistor TR14 to which the driving voltage Vdrv is applied to the source terminal, the gate terminal is connected to the R terminal, and the source terminal is A sixteenth transistor connected to the drain terminal of the fourteenth transistor TR14, a source terminal connected to the Q terminal, a gate terminal connected to the / S terminal, and a drain terminal connected to the Q terminal; G (Tr16), the gate terminal is connected to the / Q terminal, the drain terminal is connected to the source terminal of the sixteenth transistor TR16, the source terminal is connected to the seventeenth transistor TR17, the gate terminal is connected to the / R terminal An eighteenth transistor TR18 connected to the source terminal, a drain terminal connected to the / Q terminal, a gate terminal connected to the Q terminal, and a driving voltage Vdrv connected to the source terminal. A nineteenth transistor TR19 to be applied, a twentieth transistor TR20 having a gate terminal connected to the S terminal, a source terminal connected to a drain terminal of the nineteenth transistor TR19, and a drain terminal connected to the / Q terminal; A twenty-first transistor TR21 having a gate terminal connected to the / R terminal, a drain terminal connected to the / Q terminal, a gate terminal connected to the Q terminal, and a drain terminal connected to a source terminal of the twenty-first transistor TR21 Be It consists of 22 transistors (TR22) that is the source end grounded.

In this case, the driving voltage Vdrv is a power supply voltage of the flip-flop circuit, and may be preferably implemented as an external supply power supply VDD used in a semiconductor integrated circuit, but is not limited thereto.

When the potential of the clock clk input to the flip-flop circuit configured as described above is at a low level, the first transistor TR1 and the second transistor TR2 of the signal input unit 10 are turned on. On, the third transistor TR3 is turned off. Therefore, the potential level of the / S terminal and the / R terminal is a high level, thereby the potential of the S terminal and the R terminal is a low level. Since the potentials of the S and R terminals are at a low level and the potentials of the / S and / R terminals are at a high level, the 15th, 16th, 20th, and 21st transistors TR15, TR16, TR20 and TR21 are turned on, and the eleventh, twelfth, thirteenth and eighteenth transistors TR11, TR12, TR13, and TR18 are turned off.

At this time, if the logic value previously held by the output signal pairs Q and / Q was (0, 1), the seventeenth and nineteenth transistors TR17 and TR19 are turned on and the fourteenth and twenty-second transistors are turned on. (TR14, TR22) are turned off. Therefore, in this case, the logic value of the output signal pairs Q and / Q is (0, 1), and the logic value of the output signal pairs Q and / Q at this time is not changed. .

If the logic value of the output signal pairs Q and / Q was (1, 0), the fourteenth and twenty-second transistors TR14 and TR22 are turned on and the seventeenth and nineteenth transistors TR17 and TR19 are turned on. Is turned off. Therefore, the logic value of the output signal pairs Q and / Q at this time becomes (1, 0), and the logic value of the output signal pairs Q and / Q at this time does not change. have.

However, when the potential of the clock clk becomes a high level, the potential levels of the S, R, / S, and / R terminals are affected by the input signal pairs A and / A. First, the first and second transistors TR1 and TR2 of the signal input unit 10 are turned off and the third transistor TR3 is turned on so that the potential of the first node N1 has a low level. do. At this time, if the logic value of the input signal pairs A and / A is (0, 1), the eighth transistor TR8 is turned off and the ninth transistor TR9 is turned on. When the potential of the clock clk is at the low level, the potentials of the / S terminal and the / R terminal are at the high level, so the sixth and seventh transistors TR6 and TR7 are already turned on. Thus, the potential of the / R terminal transitions to a low level and the potential of the / S terminal does not change. Thereafter, the fourth transistor TR4 is turned on and the sixth transistor TR6 is turned off to maintain the high level of the / S terminal and the low level of the / R terminal. Accordingly, the state where the S terminal is at a low level and the R terminal is at a high level is established.

The 11th, 16th, 18th, and 20th transistors TR11 and TR16 of the signal output unit 20 are formed when the S and / R terminals are at a low level and the R and / S terminals are at a high level. , TR18, TR20 are turned on, and the twelfth, thirteenth, fifteenth, and twenty-first transistors TR12, TR13, TR15, and TR21 are turned off. Accordingly, the potential of the / Q terminal is at a high level, after which the seventeenth transistor TR17 is turned on, so that the potential of the Q terminal is at a low level. That is, the logic value of the output signal pair Q, / Q becomes (0, 1), which is maintained until the next rising edge time of the clock clk.

When the logic value of the input signal pairs A, / A is (1, 0), a state is created in which the potentials of the S and / R terminals are at a high level, and the R and / S terminals are at a low level. Accordingly, the logic value of the output signal pair Q, / Q becomes (1, 0), which is likewise maintained until the next rising edge time of the clock clk.

Herein, the tenth transistor TR10 of the signal input unit 10 is provided to prevent the floating state when the level transition of the / S terminal or the / R terminal occurs. The driving voltage Vdrv is used as the gate voltage of the tenth transistor TR10, but the tenth transistor TR10 is implemented in a size having a larger resistance value than other transistors. The malfunction due to the conduction current of TR10) does not occur.

In the flip-flop circuit configured as described above, when the clock clk has a high level potential, the potential levels of the / S terminal and the / R terminal are controlled according to the logic values of the input signal pairs A and / A. do. That is, when the logic value of the input signal pairs A and / A is (0, 1), the potential of the / S terminal is at a high level, and the potential of the / R terminal is at a low level. At this time, since the / R terminal had a high level potential when the potential of the clock clk was at a low level, a level transition phenomenon to a low level occurs at the / R terminal. At this time, a current path is generated through the seventh transistor TR7, the ninth transistor TR9, and the third transistor TR3 at the / R terminal, and the current flows through the / R terminal. Similarly, when the logic value of the input signal pairs A and / A is (1, 0), the sixth transistor TR6, the eighth transistor TR8 and the third transistor TR3 are connected to the / S terminal. There is a current path through it, and current flows through it.

However, such a current flow occurs every rising edge time of the clock clk. Therefore, this becomes a power consumption factor that cannot be ignored in a device in which such a flip-flop circuit is implemented. This power consumption becomes larger as the frequency of the clock clk increases, and as the current trend of semiconductor integrated circuits increasingly using high frequency clocks causes this to reduce the efficiency of flip-flop circuit use. . In addition, in the semiconductor integrated circuit for a mobile communication terminal seeking to minimize the power consumption, when a plurality of flip-flop circuits having such a configuration is provided, the overall efficiency of the semiconductor integrated circuit may be reduced. However, in the related art, such a flip-flop circuit is used while taking a predetermined power consumption, and the power consumption generated as a result is a technical limitation in implementing a semiconductor integrated circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and is a flip that generates a pulse signal using transistors of a relatively small size compared to other components and thus reduces power consumption by controlling the level shift of the precharge terminal. There is a technical problem in providing a flop circuit.

The flip-flop circuit of the present invention for achieving the above technical problem, the pulse generator for generating a pulse signal corresponding to the clock and the pre-generated output signal; A control unit controlling a potential level of a precharge terminal in response to the input of the pulse signal and the clock and input signals; A latch unit for latching a potential of the precharge terminal; And a signal output unit configured to control and output a logic value of the output signal according to a potential level of the output signal of the precharge terminal and the latch unit.

In addition, the flip-flop circuit of the present invention includes a pulse generator for selectively generating a first pulse signal or a second pulse signal corresponding to a pre-generated output signal pair when the potential of the clock is a high level; A control unit controlling potential levels of the first and second precharge terminals in response to whether the first pulse signal or the second pulse signal is generated, a potential of the clock, and an input signal pair; A latch unit configured to control potential levels of third and fourth precharge terminals by latching potentials of the first and second precharge terminals; And a signal output unit configured to control and output a logic value of the pair of output signals according to the potential levels of the first, second, third, and fourth precharge terminals.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a block diagram showing the configuration of a flip-flop circuit according to the present invention. Hereinafter, the set terminal and the reset terminal, which are precharge terminals, will be referred to as the S terminal and the R terminal, respectively.The terminal having the opposite phase of the S terminal is referred to as the / S terminal, and the terminal having the opposite phase of the R terminal is referred to as the / R terminal. It is expressed as.

As shown, the flip-flop circuit of the present invention corresponds to the first pulse signal pls1 or the second pulse signal pls2 in response to the logic value of the input of the clock clk and the prestored output signal pairs Q and / Q. ) Generates a pulse generator 30 selectively, whether the first pulse signal (pls1) or the second pulse signal (pls2) is generated, the potential of the clock (clk) and the input signal pair (A, / A A control unit 40 for controlling the potential levels of the / S terminal and the / R terminal in response to the input of the control panel, and controlling the potential levels of the / S terminal and the / R terminal by latching the potential levels of the / S terminal and the / R terminal. To an output signal generator 60 for controlling and outputting a logic value of the output signal pairs Q and / Q according to the potential level of the latch unit 50 and the S, R, / S and / R terminals. It is composed.

In the flip-flop circuit configured as described above, when the potential of the clock clk is at a low level, the pulse generator 30 does not generate the first and second pulse signals pls1 and pls2. The input signal pairs A and / A do not affect the potential levels of the / S terminal and the / R terminal, so that the / S terminal and the / R terminal are precharged to a high level. Thereafter, the potential levels of the S terminal and the R terminal are precharged to a low level by the latch operation of the latch unit 50. By the potential of the high level / S and / R terminals and the potential of the low level S and R terminals, the signal output unit 60 stores a logic value of the pre-stored output signal pairs Q and / Q. Does not change.

However, when the potential of the clock clk is at a high level, the pulse generator 30 may generate the first pulse signal pls1 or the second pulse signal according to a logic value of the output signal pairs Q and / Q. pls2) is optionally generated. Thereafter, the controller 40 selects an input signal A or / A to selectively enable the / R terminal or the / S in response to the first pulse signal pls1 or the second pulse signal pls2 being selectively enabled. Is delivered to the terminal. The latch section 50 controls the potential levels of the R and S terminals from the potential levels of the / R and / S terminals. Thereafter, the signal output unit 60 controls and outputs a logic value of the output signal pairs Q and / Q according to potential levels of the S, R, / S, and / R terminals.

In the flip-flop circuit, when the potential of the clock clk is at a high level, if the logic value of the input signal pairs A and / A is (1, 0), the logic value of the output signal pairs Q and / Q. Becomes (1, 0) which is maintained until the next rising edge time of the clock clk. Similarly, if the logic value of the input signal pair (A, / A) is (0, 1), the logic value of the output signal pair (Q, / Q) is (0, 1), which is next to the clock (clk). Maintained until rising edge time. This operation is not different from the flip-flop circuit according to the prior art.

A more detailed description of the flip-flop circuit will be made with reference to the accompanying drawings.

4 is a detailed block diagram of the flip-flop circuit shown in FIG.

As illustrated, the pulse generator 30 has both gate terminals connected to the input terminal of the clock clk and the fourth node N4, respectively, and a driving voltage Vdrv is applied to the common source terminal. The first pass gate PG1 and both gate terminals connected to the fifth node N5 are connected to the input terminal of the clock clk and the fourth node N4, respectively, and the driving voltage Vdrv is connected to the common source terminal. The third pass gate PG2 having the common drain terminal connected to the sixth node N6 and the third inverter which inverts the signal applied to the fifth node N5 and transmits the inverted signal to the seventh node N7. (IV3), the fourth inverter IV4 for inverting the signal applied to the sixth node N6 and transferring it to the eighth node N8, the output signal / Q is input to the gate terminal, and the drain terminal is the fourth inverter IV4. A twenty-third transistor TR23 connected to a fifth node N5 and a source terminal connected to a ninth node N9, and an output signal Q is input to a gate terminal. A high drain terminal is connected to the sixth node N6, a source terminal is connected to the ninth node N9, a twenty-fourth transistor TR24, a clock terminal is input to a gate terminal, and a drain terminal is connected to the sixth node N6. A twenty-fifth transistor TR25 connected to a ninth node N9, the clock clk is input to a gate terminal, the driving voltage Vdrv is applied to a source terminal, and a drain terminal is connected to the fourth node N4. The twenty-sixth transistor TR26, the gate terminal thereof is connected to the fourth node N4, the drain terminal thereof is connected to the source terminal of the twenty-fifth transistor TR25, and the source terminal is grounded. The twenty-eighth transistor TR28 and the gate terminal connected to the seventh node N7, the drain terminal connected to the fourth node N4, and the source terminal grounded, are connected to the eighth node N8, and the drain terminal is connected to the eighth node N8. A 29th end connected to the fourth node N4 and a source end thereof grounded It consists of transistor TR29.

At this time, the pulse signal formed at the seventh node N7 is the first pulse signal pls1, and the pulse signal formed at the eighth node N8 is the second pulse signal pls2. The driving voltage Vdrv is a power supply voltage of the flip-flop circuit, and may be implemented as an external supply power supply VDD used in a semiconductor integrated circuit, but is not limited thereto. The first and second pass gates PG1 and PG2 are formed of a combination of transistors.

On the other hand, the controller 40 has a thirtieth transistor TR30 and a gate in which the clock clk is input to a gate terminal, the driving voltage Vdrv is applied to a source terminal, and a drain terminal is connected to the / S terminal. A thirty-first transistor TR31 having a clock terminal clk applied thereto, a driving voltage Vdrv applied to a source terminal, a drain terminal connected to the / R terminal, and a gate terminal of the pulse generator 30 A thirty-second transistor TR32 and a gate terminal connected to a seventh node N7, a drain terminal connected to the / S terminal, and the input signal / A is applied to a source terminal are the eighth of the pulse generator 30. The thirty-third transistor TR33 is connected to a node N8, a drain terminal is connected to the / R terminal, and the input signal A is applied to a source terminal.

In addition, the latch unit 50 inverts the signal applied to the / S terminal and transfers the fifth inverter IV5 to the S terminal and the fifth inverter IV5 to form a latch structure with the fifth inverter IV5. ), And a seventh inverter IV7 which inverts the signal applied to the / R terminal and transmits it to the R terminal, and an eighth inverter IV8 which forms a latch structure with the seventh inverter IV7.

Finally, the signal output unit 60 includes a thirty-fourth transistor TR34 having a gate terminal connected to the / S terminal, a driving voltage Vdrv applied to a source terminal, and a drain terminal connected to a Q terminal. A thirty-fifth transistor TR35 connected to the / R terminal; the driving voltage Vdrv applied to a source terminal; and a drain terminal connected to the / Q terminal; a gate terminal connected to the R terminal; and a drain terminal connected to the Q terminal. A thirty-sixth transistor TR36 connected to the source terminal and grounded; a gate terminal connected to the S terminal; a drain terminal connected to the / Q terminal; and a thirty-seventh transistor TR37 connected to the source terminal; A 38th transistor TR38 connected to a Q terminal, a source terminal connected to the / S terminal, and a drain terminal connected to the / Q terminal, a gate terminal connected to the / Q terminal, and a source terminal connected to the / R terminal Connected to the drain A 39 th transistor TR39 having a terminal connected to the Q terminal, a 40 th transistor TR40 having a gate terminal connected to the Q terminal, a drain terminal connected to the R terminal, and a source terminal connected to the / Q terminal; The gate terminal is connected to the / Q terminal, the drain terminal is connected to the S terminal, and the source terminal is composed of the forty-first transistor TR41.

Looking at the operation of the flip-flop circuit configured as described above are as follows.

When the potential of the clock clk is at a low level, the first and second passgates PG1 and PG2 of the pulse generator 30 are partially turned on to form the fifth and sixth nodes N5 and N6. To deliver a high level potential. Thereafter, the high level potentials applied to the fifth and sixth nodes N5 and N6 are inverted by the third and fourth inverters IV3 and IV4 and thus the seventh and eighth nodes N7 and N8. ) Is at the low level. Since the pulse signals formed at the seventh and eighth nodes N7 and N8, respectively, are the first and second pulse signals pls1 and pls2, when the potential of the clock clk is at a low level, the first signal may be used. And it is understood that the second pulse signals pls1 and pls2 are not generated. Since the low level potentials are formed in the seventh and eighth nodes N7 and N8, the 28th and 29th transistors TR28 and TR29 are turned off. At this time, since the 26th transistor TR26 is turned on, the potential of the fourth node N4 becomes high level, and the 27th transistor TR27 is turned on.

Since the first and second pulse signals pls1 and pls2 are not generated, the 32nd and 33rd transistors TR32 and TR33 of the controller 40 are turned off. Accordingly, the input signal pairs A and / A are not transmitted to the / S terminal and the / R terminal. At this time, since the thirtieth and thirty-first transistors TR30 and TR31 are turned on, both the / S terminal and the / R terminal are precharged to a high level.

Thereafter, the S terminal and the R terminal have a low level potential by the fifth and sixth inverters IV5 and IV6 of the latch unit 50. The latch structure by the fifth to eighth inverters IV5 to IV8 maintains the potential levels of the S, R, / S, and / R terminals.

Since the potentials of the S terminal and the R terminal are at a low level, and the potentials of the / S terminal and the / R terminal are at a high level, all of the thirty-fifth to thirty-eighth transistors TR35 to TR38 of the signal output unit 60 are all. Is turned off. At this time, if the logic value of the output signal pairs Q and / Q is (1, 0), the 39 th and 40 th transistors TR39 and TR40 are turned on and the 37 th and 38 th transistors TR37, TR38) is turned off. Since the potential level of the R terminal is a low level and the potential level of the / R terminal is a high level, the potential level previously formed in the Q terminal and the / Q terminal does not change.

However, when the potential of the clock clk rises to a high level, current paths of the first and second passgates PG1 and PG2 that are partially turned on by the pulse generator 30 are blocked. The twenty-fifth transistor TR25 is turned on and the twenty-sixth transistor TR26 is turned off. If the logical value of the previously generated output signal pairs Q and / Q is (0, 1), the twenty-third transistor TR23 is turned on and the twenty-fourth transistor TR24 is turned off. . Since the twenty-seventh transistor TR27 is turned on, the potential of the fifth node N5 is at a low level. Accordingly, the potential of the seventh node N7 becomes high level. At this time, the potential of the eighth node N8 is maintained at a low level. The twenty-eighth transistor TR28 is turned on by the high level potential of the seventh node N7, the potential level of the fourth node N4 is turned low, and the twenty-seventh transistor TR27 is turned off. . Thereafter, as the potential of the fourth node N4 becomes low, the first passgate PG1 is partially turned on, and the potential of the driving voltage Vdrv is transferred to the fifth node N5. At this time, since the twenty-seventh transistor TR27 is turned off, the fifth node N5 again has a high level potential. Therefore, the potential of the seventh node N7 becomes low again. That is, when the potential of the output signal pairs Q and / Q previously generated when the potential of the clock clk is at the high level is (0, 1), the seventh node N7 may have the clock clk. A pulse signal with an enable period shorter than half period is generated. The pulse signal thus generated is the first pulse signal pls1.

Referring to the operation of the pulse generator 30 described above, the twenty-third transistor TR23, the twenty-fifth transistor TR25, and the fifth node N5 from the fifth node N5 according to the logic values of the output signals Q and / Q. The current path through the twenty-seventh transistor TR27 or the current path from the sixth node N6 through the twenty-fourth transistor TR24, the twenty-fifth transistor TR25, and the twenty-seventh transistor TR27 is It is created. In addition, a flow of a current passing through the twenty-eighth transistor TR28 or the twenty-ninth transistor TR29 from the fourth node N4 is generated. In order to reduce the current flow, the width of the transistors provided in the pulse generator 30 is adjusted to reduce the width. As a result, the response speed of each transistor becomes slow. The pulse generator 30 generates an pulse signal having an enable period shorter than a half period of the clock clk while the potential of the clock clk is at a high level without performing an input / output operation of the input signal. Since the transistors of the pulse generator 30 do not need to have a fast response speed. By such a configuration, the amount of current flowing in the current path formed in the pulse generator 30 can be reduced as compared to the flip-flop circuit of the prior art.

Meanwhile, when the first pulse signal pls1 is enabled, the thirty-second transistor TR32 of the controller 40 is turned on. At this time, the thirty-third transistor TR33 is turned off. In this case, the logical value of the previously generated output signal pairs Q and / Q is (0, 1). Therefore, the potential of the S terminal is at a low level, and the potential of the / S terminal is at a high level. At this time, if the input signal pairs A and / A having the same logic value as the output signal pairs Q and / Q are input, the potential of the input signal / A and the potential of the / S terminal are at the same level so that the operation is different. Only the operation of maintaining the output signal pairs Q and / Q of the pre-generated logic value without change is performed.

However, if the input signal pair (A, / A) of the logic value different from the output signal pair (Q, / Q) is input, the logical value of the input signal pair (A, / A) is (1, 0) The potential at the / S terminal transitions to a low level. This in turn causes the level transition of the S terminal of the latch unit 50 to form the potential of the S terminal to a high level.

In this case, the potentials of the S and / R terminals are at a high level and the potentials of the / S and R terminals are at a low level. Therefore, the 34 th and 37 th transistors TR34 and TR37 of the signal output unit 60 are turned on, and the 35 th and 36 th transistors TR35 and TR36 are turned off. At this time, the 38th and 41st transistors TR38 and TR41 are turned on and the 39th and 40th transistors TR39 and TR40 are turned off by the potential of the output signal pairs Q and / Q. It is in a state. Therefore, the high level potential of the S terminal is transferred to the Q terminal, and the low level potential of the / S terminal is transferred to the / Q terminal, so that the logic value of the output signal pairs Q and / Q is (1, 0). ).

In contrast, when the potential of the clock clk is at a high level, the second pulse signal pls2 is generated when the logic value of the previously generated output signal pairs Q and / Q is (1, 0). Similarly, if the logic value of the input signal pair (A, / A) input at this time is (1, 0), the level transition of the S, R, / S and / R terminals, which are precharge terminals, does not occur. Is not generated, but if the logic value of the input signal pairs (A, / A) is (0, 1), the level of the R terminal and the / R terminal is shifted, so that the output signal pair in the signal output unit 60 The logical value of (Q, / Q) changes.

That is, the flip-flop circuit of the present invention generates a pulse signal to reduce the number of level transitions of the precharge terminal and to reduce the power consumption that has occurred in the level transition of the precharge terminal. In this case, power consumption may be reduced by adjusting the sizes of transistors provided to generate the pulse signal.

5A and 5B are timing diagrams for explaining an operation of a flip-flop circuit according to the present invention. When the logic value of the output signal pairs Q and / Q is (0, 1), the input signal pairs A and / The operation of the flip-flop in the case where the logic value of A) is (1, 0) and (0, 1) is explained respectively.

5A, it can be seen that the first pulse signal pls1 is generated in a section where the potential of the clock clk is at a high level. At this time, the second pulse signal pls2 is not generated. When the potential of the / S terminal transitions to a low level by the low level potential of the input signal / A as the first pulse signal pls1 occurs, and when the potential of the clock clk transitions to a low level This level is maintained until. According to the potential level of the / S terminal, the potential of the / Q terminal transitions to a low level, and the potential of the Q terminal transitions to a high level. The potential level of the output signal pairs Q, / Q is maintained until the next rising edge time of the clock clk by a latch operation.

Similarly in FIG. 5B, it is confirmed that only the first pulse signal pls1 is generated in a section in which the potential of the clock clk is at a high level. Although the first pulse signal pls1 is generated, the level shift of the / S terminal does not occur due to the high level potential of the input signal / A. According to the potential level of the / S terminal, the potential of the / Q terminal maintains a high level, and the potential of the Q terminal maintains a low level. The potential of the output signal pairs Q and / Q having such a level is maintained until the next rising edge time of the clock clk by a latch operation.

As described above, the flip-flop circuit of the present invention generates a pulse signal according to the potential of the clock and the logic value of the pre-stored output signal pair, and the precharge terminal according to whether the generated pulse signal is enabled and the input signal pair. Control the level of the output signal to perform the operation. At this time, since the circuit unit for generating the pulse signal only needs to generate the pulse signal within a half period of the clock, it is not sensitive to the response speed. Therefore, the amount of current lost can be reduced by relatively reducing the size of the transistors provided in the circuit unit for generating the pulse signal. In the precharge terminal, the level shift occurs only when the potentials of the input signal and the output signal are different, thereby reducing the current loss. As described above, the flip-flop circuit that performs the function as the flip-flop circuit and reduces the power consumption can be realized. Therefore, when the flip-flop circuit is provided in the semiconductor integrated circuit, power consumption is not large even when the high frequency clock is used, and the technical efficiency is improved in the utilization of the semiconductor integrated circuit.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The flip-flop circuit of the present invention described above has the effect of reducing power consumption by generating a pulse signal using transistors of a relatively smaller size than other components and controlling the level shift of the precharge terminal accordingly.

In addition, since the level shift of the precharge terminal occurs only when the potential of the input signal and the output signal is different, there is an effect of reducing the power consumption of the precharge terminal.

Claims (22)

A pulse generator for generating a pulse signal in response to a clock and a pre-generated output signal; A control unit controlling a potential level of a precharge terminal in response to the input of the pulse signal and the clock and input signals; A latch unit for latching a potential of the precharge terminal; And A signal output unit controlling and outputting a logic value of the output signal according to a potential level of the precharge terminal and the output signal of the latch unit; Flip-flop circuit comprising a. The method of claim 1, The transistors provided in the pulse generator are implemented in a smaller size than the control unit, the latch unit and the output unit. The method of claim 2, The pulse generator does not generate the pulse signal when the potential of the clock is at a low level, and generates a first pulse signal or a second pulse signal according to the potential of the pre-generated output signal when the potential of the clock is at a high level. Flip-flop circuitry for selectively generating; The method of claim 3, wherein The pulse generator, A first pass gate having both gate terminals connected to an input terminal and a first node of the clock, a driving voltage applied to a common source terminal, and a common drain terminal connected to a second node, respectively; A second pass gate having both gate terminals connected to an input terminal of the clock and the first node, the driving voltage applied to a common source terminal, and a common drain terminal connected to a third node; A first inverter for inverting and applying a signal applied to the second node to a fourth node; A second inverter inverting the signal applied to the third node and transferring the inverted signal to a fifth node; A first transistor having an output signal / Q input to a gate terminal, a drain terminal connected to the second node, and a source terminal connected to a sixth node; A second transistor having an output signal Q input to a gate end thereof, a drain end thereof connected to the third node, and a source end thereof connected to the sixth node; A third transistor having the clock input to a gate end thereof and a drain end thereof connected to the sixth node; A fourth transistor in which the clock is input to a gate terminal, the driving voltage is applied to a source terminal, and a drain terminal is connected to the first node; A fifth transistor having a gate terminal connected to the first node, a drain terminal connected to a source terminal of the third transistor, and a source terminal grounded; A sixth transistor having a gate terminal connected to the fourth node, a drain terminal connected to the first node, and a source terminal grounded; And A seventh transistor having a gate terminal connected to the fifth node, a drain terminal connected to the first node, and a source terminal grounded; And forming the first pulse signal at the fourth node and forming the second pulse signal at the fifth node. The method of claim 4, wherein And said first and second passgates comprise a combination of transistors. The method of claim 1, The control unit controls the potential of the precharge terminal to a high level when the potential of the clock is at a low level, and transmits the input signal to the precharge terminal according to whether the pulse signal is enabled when the potential of the clock is at a high level. Flip-flop circuit characterized in that for transmitting. The method of claim 6, And the precharge terminal generates a level transition only when a logic value of the input signal and the output signal is different when the pulse signal is generated. The method of claim 6, The control unit, A first transistor having a clock input to a gate terminal, a driving voltage applied to a source terminal, and a drain terminal connected to a / S precharge terminal; A second transistor having the clock input to a gate terminal, the driving voltage applied to a source terminal, and a drain terminal connected to a / R precharge terminal; A third transistor having a gate terminal connected to a first pulse signal input terminal, a drain terminal connected to the / S precharge terminal, and an input signal / A applied to a source terminal; And A fourth transistor having a gate terminal connected to a second pulse signal input terminal, a drain terminal connected to the / R precharge terminal, and an input signal A applied to a source terminal; Flip-flop circuit comprising a. The method of claim 1, The latch unit, A first inverter inverting the signal applied to the / S precharge terminal and transferring the inverted signal to the S precharge terminal; A second inverter forming a latch structure with the first inverter; A third inverter that inverts the signal applied to the / R precharge terminal and transmits the inverted signal to the R precharge terminal; And A fourth inverter forming a latch structure with the third inverter; Flip-flop circuit comprising a. The method of claim 1, The signal output unit, A first transistor having a gate end connected to the / S precharge terminal, a driving voltage applied to the source end, and a drain end connected to the Q output terminal; A second transistor having a gate terminal connected to a / R precharge terminal, a driving voltage applied to a source terminal, and a drain terminal connected to a / Q output terminal; A third transistor having a gate terminal connected to an R precharge terminal, a drain terminal connected to the Q output terminal, and a source terminal grounded; A fourth transistor having a gate terminal connected to an S precharge terminal, a drain terminal connected to the / Q output terminal, and a source terminal grounded; A fifth transistor having a gate terminal connected to the Q output terminal, a source terminal connected to the / S precharge terminal, and a drain terminal connected to the / Q output terminal; A sixth transistor having a gate terminal connected to the / Q output terminal, a source terminal connected to the / R precharge terminal, and a drain terminal connected to the Q output terminal; A seventh transistor having a gate terminal connected to the Q output terminal, a drain terminal connected to the R precharge terminal, and a source terminal connected to the / Q output terminal; And An eighth transistor having a gate terminal connected to the / Q output terminal, a drain terminal connected to the S precharge terminal, and a source terminal connected to the Q output terminal; Flip-flop circuit comprising a. The method according to any one of claims 4, 8 and 10, And the driving voltage is an external supply power supply (VDD) of a semiconductor integrated circuit. A pulse generator for selectively generating a first pulse signal or a second pulse signal in response to a pre-generated output signal pair when the potential of the clock is at a high level; A control unit controlling potential levels of the first and second precharge terminals in response to whether the first pulse signal or the second pulse signal is generated, a potential of the clock, and an input signal pair; A latch unit configured to control potential levels of third and fourth precharge terminals by latching potentials of the first and second precharge terminals; And A signal output unit configured to control and output a logic value of the pair of output signals according to potential levels of the first, second, third and fourth precharge terminals; Flip-flop circuit comprising a. The method of claim 12, The transistors provided in the pulse generator are implemented in a smaller size than the control unit, the latch unit and the output unit. The method of claim 13, And the pulse generator does not generate the first and second pulse signals when the potential of the clock is at a low level. The method of claim 14, The pulse generator, A first pass gate having both gate terminals connected to an input terminal and a first node of the clock, a driving voltage applied to a common source terminal, and a common drain terminal connected to a second node, respectively; A second pass gate having both gate terminals connected to an input terminal of the clock and the first node, the driving voltage applied to a common source terminal, and a common drain terminal connected to a third node; A first inverter for inverting and applying a signal applied to the second node to a fourth node; A second inverter inverting the signal applied to the third node and transferring the inverted signal to a fifth node; A first transistor having an output signal / Q input to a gate terminal, a drain terminal connected to the second node, and a source terminal connected to a sixth node; A second transistor having an output signal Q input to a gate end thereof, a drain end thereof connected to the third node, and a source end thereof connected to the sixth node; A third transistor having the clock input to a gate end thereof and a drain end thereof connected to the sixth node; A fourth transistor in which the clock is input to a gate terminal, the driving voltage is applied to a source terminal, and a drain terminal is connected to the first node; A fifth transistor having a gate terminal connected to the first node, a drain terminal connected to a source terminal of the third transistor, and a source terminal grounded; A sixth transistor having a gate terminal connected to the fourth node, a drain terminal connected to the first node, and a source terminal grounded; And A seventh transistor having a gate terminal connected to the fifth node, a drain terminal connected to the first node, and a source terminal grounded; And forming the first pulse signal at the fourth node and forming the second pulse signal at the fifth node. The method of claim 15, And said first and second passgates comprise a combination of transistors. The method of claim 12, The control unit controls the potential of the precharge terminal to a high level when the potential of the clock is at a low level. The controller controls whether the first pulse signal or the second pulse signal is enabled when the potential of the clock is at a high level. And a first input signal or a second input signal to the first precharge terminal or the second precharge terminal, respectively. The method of claim 17, The first precharge terminal or the second precharge terminal flips a level transition only when a logic value of the input signal pair and the output signal pair is different when the first pulse signal or the second pulse signal is generated. Flop circuit. The method of claim 17, The control unit, A first transistor having the clock input to a gate terminal, a driving voltage applied to a source terminal, and a drain terminal connected to the first precharge terminal; A second transistor having the clock input to a gate terminal, the driving voltage applied to a source terminal, and a drain terminal connected to the second precharge terminal; A third transistor having a gate terminal connected to a first pulse signal input terminal, a drain terminal connected to the first precharge terminal, and a first input signal applied to a source terminal; And A fourth transistor having a gate terminal connected to a second pulse signal input terminal, a drain terminal connected to the second precharge terminal, and a second input signal applied to a source terminal; Flip-flop circuit comprising a. The method of claim 12, The latch unit, A first inverter inverting the signal applied to the first precharge terminal and transferring the inverted signal to the third precharge terminal; A second inverter forming a latch structure with the first inverter; A third inverter inverting the signal applied to the second precharge terminal and transferring the inverted signal to the fourth precharge terminal; And A fourth inverter forming a latch structure with the third inverter; Flip-flop circuit comprising a. The method of claim 12, The signal output unit, A first transistor having a gate terminal connected to the first precharge terminal, a driving voltage applied to a source terminal, and a drain terminal connected to a first output terminal; A second transistor having a gate terminal connected to the second precharge terminal, a driving voltage applied to a source terminal, and a drain terminal connected to a second output terminal; A third transistor having a gate terminal connected to a third precharge terminal, a drain terminal connected to the first output terminal, and a source terminal grounded; A fourth transistor having a gate terminal connected to a fourth precharge terminal, a drain terminal connected to the second output terminal, and a source terminal grounded; A fifth transistor having a gate terminal connected to the first output terminal, a source terminal connected to the first precharge terminal, and a drain terminal connected to the second output terminal; A sixth transistor having a gate terminal connected to the second output terminal, a source terminal connected to the second precharge terminal, and a drain terminal connected to the first output terminal; A seventh transistor having a gate terminal connected to the first output terminal, a drain terminal connected to the third precharge terminal, and a source terminal connected to the second output terminal; And An eighth transistor having a gate terminal connected to the second output terminal, a drain terminal connected to the fourth precharge terminal, and a source terminal connected to the first output terminal; Flip-flop circuit comprising a. The method according to any one of claims 15, 19 and 21, And the driving voltage is an external supply power supply (VDD) of a semiconductor integrated circuit.

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