JPH10320996A - Redundancy judgement circuit and semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a redundancy judgement circuit and a semiconductor memory device which enable the suppression of an unnecessary current flowing through a fuse circuit regardless of the necessity of the relief of the redundancy. SOLUTION: As a node n1 is precharged to be on a high level and, after a P-type MOS transistor P1 is turned off and its current route is cut off, one of respective transistors N1-N4 is turned on in accordance with addresses A1 and A2, a current flowing from the node n1 to a ground side can be suppressed to be sufficiently small. Further, as the P-type MOS transistor P2 of a latching circuit 103 has a lower driving capability than the respective transistors N1-N4, the level of the node n1 can be switched to a low level quickly and the P-type MOS transistor P2 is turned off and the current route is cut off. Therefore, a current from the latching circuit 103 can be also suppressed to be sufficiently small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a redundancy judgment circuit,
And a semiconductor memory device to which the redundancy judgment circuit is applied.

[0002]

2. Description of the Related Art As this kind of conventional redundancy judgment circuit,
There is one as shown in FIG. In FIG. 1, a fuse circuit 101 includes fuses f1 to f4 and a transistor N1.
To N4 in series.
These series circuits are inserted between the node n1 and the ground potential. Each address decode signal A1, A2, / A1, A2,
A1 / A2, / A1 / A2 are 2-bit addresses A
1, A2 are decoded, and these address decode signals A1, A2, / A1, A2, A1, / A2, / A1,.
/ A2 is applied to each of the transistors N1 to N4, and any one of these transistors N1 to N4 is selectively turned on.

Here, for simplicity, 2-bit addresses A1 and A2 are illustrated, but in general, in the case of an n-bit address, there are 2 ⁿ types of decoded signals. Provide ²ⁿ sets of fuses and transistors.

A P-channel MOS transistor P1 has
A signal / P is applied to the gate, and when the signal / P is at a low level, the P-channel MOS transistor P1 is turned on. As a result, the power supply potential Vcc is applied to the node n1 via the P-channel MOS transistor P1, and this node n1 becomes high level (power supply potential Vcc).
Is charged.

At this time, if the addresses A1 and A2 are redundantly replaced addresses, any one of the transistors N1 to N4 corresponding to the address is turned on, so that the fuse paired with the on transistor is cut in advance. If so, the high level of this node n1 is held, inverted by the latch circuit 103, and
4 is output as a high-level redundancy activation signal SP. This redundant activation signal SP
It is used to select a memory cell for redundancy.

For example, when the fuse f1 is cut in advance and the address decode signals A1 and A2 go high, the transistor N
When only 1 is turned on, the operation as shown in the timing chart of FIG. 10 is performed.

First, when the address decode signals A1 and A2 go to a high level, only the transistor N1 turns on.
The channel type MOS transistor P1 is turned on, and the node n1 is charged to a high level.

Even when the transistor N1 is turned on, the fuse f1 is cut in advance and the other transistors N1 to N4 are turned off, so that the node N1 is not connected to the ground potential and maintains a high level. I do.

[0009] Even after the P-channel MOS transistor P1 is turned off, the high level of the node N1 is kept held by the latch circuit 103. Latch circuit 1
03 outputs the inverted level of the node N1, and the output is inverted again by the inverter 104 to output a high-level redundancy activation signal SP, and this redundancy activation signal SP becomes active.

If the addresses A1 and A2 are not addresses that are redundantly replaced, the other signals /A1.A2, A1.
One of / A2, / A1,... / A2 goes high, turning on one of the other transistors N2 to N4. At this time, since the other fuses f2 to f4 are not blown, the node N1 is connected to the other transistors N2 to N4.
4, the node N1 goes low, the redundancy activation signal SP goes low, and becomes inactive.

However, even if the node N1 is grounded via any of the other transistors N2 to N4, the signal / P becomes low level and the P-channel type
Since the S transistor P1 is turned on and the node n1 is about to be charged to a high level, the P-channel MOS
Unnecessary current flows from the transistor P1 to the ground via one of the other transistors N2 to N4.

If it is not necessary to repair the redundancy,
Since neither fuse is blown, each transistor N
Regardless of which of 1 to N4 is turned on, when the signal / P is at a low level, the P-channel MOS transistor P1 is turned on, and an unnecessary current flows from the P-channel MOS transistor P1 to the ground side.

Next, in order to suppress such unnecessary current, Japanese Unexamined Patent Publication No. 4-216398 discloses a configuration shown in FIG.
Has been proposed. In this redundancy judgment circuit, unnecessary current is suppressed when there is no need to repair the redundancy, that is, when none of the fuses is cut.

In this redundancy judgment circuit, a redundancy operation switching circuit 111, an OR circuit 112, and an N-channel MOS transistor N5 are added to the circuit of FIG.

If there is no need to repair the redundancy, the fuse f5 of the redundancy operation switching circuit 111 is not cut. At this time, since a high-level signal is always applied from the redundant operation switching circuit 111 to the OR circuit 112, the signal / P
High level signal is applied from the OR circuit 112 to the P-channel MOS transistor P1, regardless of the level of the P-channel MOS transistor P1, and the P-channel MOS transistor P1 is always turned off. As a result, unnecessary current does not flow to the ground side.

If redundancy needs to be relieved,
The fuse f5 of the redundant operation switching circuit 111 is cut. At this time, the redundant operation switching circuit 111 switches the OR circuit 11
2, the level of the signal / P is transmitted to the P-channel MOS transistor P1 via the OR circuit 112, and the P-channel MOS transistor P1 is turned on in accordance with the level of the signal / P. Turn on and off.

Further, each fuse f of the fuse circuit 101
Any one of 1 to f4 is cut in advance. For example, when the fuse f1 is cut in advance and only the transistor N1 paired with the fuse f1 is turned on, the operation as shown in the timing chart of FIG. 12 is performed.

First, when the address decode signals A1 and A2 go high, only the transistor N1 turns on. Subsequently, at time t0, when each signal / P, / EN goes low, the P-channel MOS transistor P
1 turns on, and the N-channel MOS transistor N5
Is turned off, and the node n1 is charged to a high level.

At time tE, even after the signal / P goes high and the P-channel MOS transistor P1 is turned off, the high level of the node n1 remains at the latch circuit 103.
, And is inverted twice by the latch circuit 103 and the inverter 104 to output a high-level redundancy activation signal SP.
P becomes active.

However, also in this circuit, if the addresses A1 and A2 are not redundantly replaced addresses,
When the signal / P goes low when the node N1 is grounded via any of the other transistors N2 to N4, the P-channel MOS transistor P1 turns on, and the node n1 goes high. Unnecessary current flows from the P-channel type MOS transistor P1 to the ground side via any one of the other transistors N2 to N4 because it is about to be charged.

Next, Japanese Patent Laying-Open No. 5-258590 proposes a redundancy judgment circuit as shown in FIG. In this redundancy determination circuit, unnecessary current is suppressed when redundancy needs to be relieved, that is, when one of the fuses is cut.

In this redundancy judgment circuit, each transistor t1, t2, t3 and each fuse f1, f2, f3 are connected in series by one pair,
1 ', t2', t3 'and each fuse f1', f2 ', f3'
Each series circuit connected in series with each pair, each input terminal m1, m2, m3 for inputting each address input signal A1, A2, A3,
A fuse circuit is formed from the inverters INV1, INV2, and INV3. Further, transfer gates c1, c2, and c3 are inserted between the transistors t1, t2, and t3 and the input terminals m1, m2, and m3. Each transistor t1 ', t2', t3 'and each inverter INV1, INV2, INV3
Transfer gates c1 ', c2', c
3 ', and each transistor t1, t2, t3, t1',
In order to set the gate sides of t2 'and t3' to low level, each of the N-channel MOS transistors d1, d2, d3, d
1 ', d2' and d3 'are provided. The precharge signal P is input to the gates of the transfer gates c1, c2, c3, c1 ', c2', c3 ', and the N-channel MOS transistors d1, d2, d3, d1', d2 ',
To the gate of d3 ', an inverted signal of the precharge signal P inverted by the inverter INV is input. As a result, when the precharge signal P goes low to precharge the node n1, each of the N-channel MOS transistors d1, d2, d
3, d1 ', d2', d3 'are turned off.

The operation of the redundancy judgment circuit having such a configuration is shown in FIG.
4 will be described according to the timing chart.

First, when the precharge signal P goes low, the P-channel MOS transistor tp turns on. During the low level period of the precharge signal P,
Node n1 is precharged to a high level. At this time, regardless of the level of each address input signal A1, A2, A3, each transfer gate c1, c2, c3, c
1 ', c2', c3 'are all turned off, and the respective N-channel MOS transistors d1, d2, d3, d1', d2 ',
All of d3 'are on. Therefore, the gates of the transistors t1, t2, t3, t1 ', t2', t3 'are all at a low level, and all of the transistors t1, t2, t3, t1', t2 ', t3' Turns off.

On the other hand, when the precharge signal P goes high, each of the N-channel MOS transistors d1, d2,
All of d3, d1 ', d2', d3 'are turned off, and each transfer gate c1, c2, c3, c1', c2 ',
All of c3 'are turned on.

Here, for example, each address input signal A1,
When A2 and A3 are at high level, low level and low level (address "100"), each transistor t1,.
t2 'and t3' are turned on. These transistors t
Each fuse f1, f2 ', f paired with 1, t2', t3 '
Since 3 'is disconnected, the high level of the node n1 is held, and the high level redundancy activation signal SP is output.

Further, for example, each address input signal A1, A
2, A3 are at low level, high level and low level (address "010"), and when the precharge signal P is at low level, each transfer gate c1, c2, c
3, c1 ', c2', c3 'are all turned off, and the N-channel MOS transistors d1, d2, d3, d1', d2 ',
Since all of d3 'are turned on, the transistors t1, t
2, t3, t1 ', t2', and t3 'are all turned off.

When the precharge signal P goes high, each of the N-channel MOS transistors d1, d
2, d3, d1 ', d2', d3 'are all turned off, and each transfer gate c1, c2, c3, c1', c2 ',
All of the transistors c1 'and t3' are turned on.
2, t3 'is turned on. These transistors t1 ',
Since f1 'and f2 of the fuses paired with t2 and t3' are not cut, the potential of the node n1 passes to the ground via the fuses f1 'and f2 and the transistors t1' and t2. Node n1 goes low.

As described above, while the precharge signal P is at the low level and the node n1 is being precharged, all of the transistors t1, t2, t3, t1 ', t2', t3 'are turned off. Unnecessary current does not flow from the node n1 to the ground potential.

[0030]

As described above, in the conventional redundancy judging circuit shown in FIG. 9, when it is necessary to repair the redundancy, if the addresses A1 and A2 are not addresses that replace the redundancy, the node n1 is connected to each transistor. In the state where the node n1 is grounded via any one of the above, the node n1 tends to be charged to a high level, so that an unnecessary current flows from the P-channel MOS transistor P1 to the ground via any one of the transistors.

Alternatively, when it is not necessary to relieve the redundancy, none of the fuses is blown. Therefore, even if any of the transistors N1 to N4 is turned on, when the signal / P is at a low level, the P-channel MOS Transistor P
1 is turned on, and the P-channel MOS transistor P1
Unnecessary current flows from the ground to the ground.

The other conventional redundancy judgment circuit shown in FIG. 11 can suppress unnecessary current when there is no need to relieve the redundancy. If A1 and A2 are not redundantly replaced addresses, the node n1 will be charged to a high level while the node N1 is grounded via one of the transistors. Unnecessary current flows to the ground side.

Further, in another conventional redundancy judgment circuit shown in FIG. 13, although unnecessary current when redundancy needs to be relieved can be suppressed, each element in a range surrounded by a broken line in FIG. Each N-channel MOS transistor d
1, d2, d3, d1 ', d2', d3 ', and transfer gates c1, c2, c3, c1', c2 ', c3', etc., must be provided and compared with the redundancy judgment circuits of FIGS. 9 and 11. do it,
There is a disadvantage that the circuit configuration becomes complicated and the circuit scale becomes large.

Accordingly, the present invention is to solve such a conventional problem, and can suppress unnecessary current flowing through the fuse circuit regardless of the necessity of relieving redundancy. It is an object of the present invention to provide a redundancy judgment circuit and a semiconductor memory device that do not require a relatively large circuit scale.

[0035]

According to a first aspect of the present invention, a plurality of series circuits each having a switching element and a fuse connected in series are inserted between a node and a reference potential. Selectively disconnect any one of the fuses, selectively turn on each switching element according to the address, and respond to the potential of the node when the switching element paired with the blown fuse is turned on. A redundancy determination circuit that outputs a redundant activation signal
With each switching element turned off, a precharge means for precharging the potential of the node, a latch means for latching the potential of the node, and an output of the latch means are activated to activate a redundant active circuit corresponding to the output. Activating means for outputting an activation signal, wherein the potential of the node is precharged by the precharge means, and thereafter, each switching element is selectively turned on in accordance with the address, and then the potential of the node is latched by the latch means. Then, the output of the latch means is activated by the activation means.

According to such a configuration, first, when redundancy needs to be remedied, if the address is an address that replaces the redundancy, one of the transistors corresponding to this address is turned on. If the fuse paired with the node is cut in advance, the high level of the node is held, the high level of this node is latched by the latching means, and the output of this latching means is activated by the activating means to be at the high level. A corresponding redundancy activation signal is output from the activation means.

If the address is not an address which is redundantly replaced, although a current flows from the node through one of the switching elements, the potential of the node is precharged by the precharge means, and thereafter, each switching element is changed in accordance with the address. Based on the procedure of selectively turning on the node, when the current flows from the node, the pre-jersey of the potential of the node is terminated, and unnecessary current can be sufficiently reduced.

Further, when there is no need to repair redundancy,
Do not blow any of the fuses. In this state, when the node is precharged and then each switching element is selectively turned on, current flows from the node through one of the switching elements, but at this time, the pre-jersey of the potential of the node is terminated. Therefore, unnecessary current can be sufficiently reduced.

If the address is not an address that replaces the redundancy or if it is not necessary to relieve the redundancy, the potential of the node becomes the reference potential, and this reference potential is latched by the latch means. The output of the latch means is activated by the activation means. Activated, a redundant activation signal corresponding to the reference potential is output from the activating means.

As described in claim 2, each series circuit is inserted between the node and the ground potential, and the precharge means is a P-channel MOS transistor inserted between the power supply and the node. When a low-level precharge signal is input to the gate of the type MOS transistor, the node may be precharged to the power supply potential via the P-channel type MOS transistor.

Further, as described in claim 3, each series circuit is inserted between a node and a ground potential, and the precharge means comprises:
An N-channel MOS transistor inserted between a power supply and a node. When a high-level precharge signal is input to the gate of the N-channel MOS transistor, the node is connected via the N-channel MOS transistor. It may be precharged to the power supply potential.

Alternatively, as described in claim 4, each series circuit is inserted between the node and the potential of the power supply, and the precharge means is an N-channel type M inserted between the node and the ground potential.
When a high-level precharge signal is input to the gate of the N-channel MOS transistor, the node may be precharged to the ground potential via the N-channel MOS transistor.

Further, as described in claim 5, each series circuit is inserted between a node and a ground potential, the latch means inverts and outputs the potential of the node, and the activating means outputs the output of the latch means. Alternatively, the NOR logic of the signal obtained by inverting the chip internal activation signal may be obtained, and the result may be output as a redundant activation signal.

Alternatively, as described in claim 6, each series circuit is inserted between a node and a potential of a power supply, and the latch means comprises:
The activation means may invert and output the potential of the node, obtain the AND logic of the output of the latch means and the chip internal activation signal, and output the result as a redundant activation signal.

Next, the invention according to claim 7 is directed to claim 1
7. In the semiconductor memory device provided with the redundancy judgment circuit according to any one of the above items, the precharge signal applied to the precharge means is activated in response to the input of the external control signal and the external address, and the precharge means is activated. And an address decode delay means for decoding an external address into an address, delaying the address, and applying the delayed address to a switching element of each serial circuit, so that the precharge signal once activated becomes inactive. After that, the address is given to the switching element of each series circuit.

That is, in this semiconductor memory device, in response to the input of the external control signal and the external address, the timing for activating the precharge means is determined, the external address is decoded into an address, and the serial address is delayed by delaying this address. By providing the switching elements of the circuit, the node is precharged, and thereafter, the procedure of selectively turning on each switching element is realized.

[0047]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a first embodiment of the redundancy judgment circuit of the present invention. In the redundancy judgment circuit of the first embodiment, the inverter 10 of the circuit of FIG.
4, a NOR circuit 11 and an inverter 12 are provided. The P-channel type MOS of the latch circuit 103
As the transistor P2, a transistor having a lower driving ability than each of the transistors N1 to N4 of the fuse circuit 101 is applied. Further, each address decode signal A1, A2, / A
The timings of 1.A2, A1./A2, /A1./A2 and the precharge signal / P are different, and the chip 12 activation signal ACT is applied to the inverter 12.

The operation of such a redundancy judgment circuit will be described with reference to the timing chart shown in FIG. Here, the fuse f1 is cut in advance, and when the address decode signals A1 and A2 become high level, only the transistor N1 paired with the fuse f1 is turned on.

First, in the period up to the time point t1, the precharge signal / P is at the high level and the P-channel type MO
The S transistor P1 is turned off, and each address decode signal A1
All of A2, / A1, A2, A1, / A2, / A1, / A2 are at low level, and all of the transistors N1 to N4 are off.

In the period from time t1 to time t2, the precharge signal / P is at the low level and the P-channel MOS transistor P1 is turned on, whereas the address decode signals A1, A2, / A1, A2, A
1 / A2, /A1./A2 are all kept at the low level, all the transistors N1 to N4 are kept off, and the node n is independent of the state of each fuse f1 to f4.
1 is precharged to high level.

At time t2, the precharge signal / P goes high, the P-channel MOS transistor P1 turns off, and the precharging of the node n1 ends.

At this time, if the addresses A1 and A2 are not addresses that are redundantly replaced, at the subsequent time t3, each of the other address decode signals / A1, A2, A1, / A2, /, excluding the address decode signals A1, A2. One of A1 / A2 becomes high level, and one of the transistors N2 to N4 paired with the uncut fuses f2 to f4 is turned on, and a current flows from the node n1 to the ground side. Node n1 goes low.

However, since the precharge period from time t1 to time t2 has ended and the P-channel MOS transistor P1 has been turned off, the current path is cut off and the current flowing from the node n1 to the ground side. Can be kept sufficiently small.

When the node n1 switches from the high level to the low level, the latch circuit 10
3, the P-channel MOS transistor P2 is turned on, but the P-channel MOS transistor P2
2 has a lower driving capability than the transistors N1 to N4 of the fuse circuit 101, the latch circuit 103 cannot hold the potential of the node n1 and the node n1 is quickly switched to a low level. Accordingly, the latch circuit 1
The output of the inverter INV 03 goes high, the P-channel MOS transistor P2 is turned off, and the current path from the latch circuit 103 to the fuse circuit 101 is cut off. Therefore, the current from the latch circuit 103 can be sufficiently reduced.

Alternatively, if the addresses A1 and A2 are redundantly replaced addresses, at time t3, only the address decode signals A1 and A2 go high, and the transistors N1 paired with the blown fuse f1 turn on. However, no current flows from the node n1 to the ground side, and the high level of the node n1 is maintained.

The high level of the node n1 continues to be held by the latch circuit 103.
Output of the inverter INV becomes low level.

Although the node n1 is set to either the high level or the low level from the time point t1 to the time point t4, the chip internal activation signal ACT is kept at the low level until the time point t4. , Inverter 12
Is at a high level, and the output of the NOR circuit 11, that is, the redundancy activation signal SP is maintained at a low level.

At time t4, the chip internal activation signal ACT is switched to high level, one input of the NOR circuit 11 becomes low level, and one of the high level and low level of the node n1 becomes NOR circuit. The signal is output as a redundancy activation signal SP via the line 11. Table 1 below shows the level of the redundant activation signal SP with respect to the level of the node n1 and the level of the chip internal activation signal ACT.

[0059]

[Table 1]

At time t5, the chip internal activation signal ACT
Is switched to low level, one input of the NOR circuit 11 becomes high level, and the redundancy activation signal SP returns to low level.

As described above, in the redundancy judgment circuit of the first embodiment, during the period from time t1 to time t2, the node n1 is precharged to the high level, the current path is cut off, and at time t3, the address Since any one of the transistors N1 to N4 is turned on in accordance with A1 and A2, the node n
Unnecessary current flowing from 1 to the ground side can be suppressed. Further, the P-channel type M of the latch circuit 103
Since the OS transistor P2 has a lower driving capability than each of the transistors N1 to N4, the node n1 is quickly switched to the low level, and the P-channel MOS transistor P2
Is turned off, and the current path is cut off, so that the current from the latch circuit 103 can be sufficiently suppressed.

Further, even when there is no need to relieve the redundancy, the node n1 is not connected during the period from time t1 to time t2.
Is precharged to a high level, and at time t3, one of the transistors N1 to N4 is turned on.
Unnecessary current flowing from 1 to the ground side can be sufficiently suppressed.

The P-channel MOS transistor P
Instead of 1, an N-channel MOS transistor can be applied. In this case, the precharge signal / P
May be used.

FIG. 3 shows a second embodiment of the redundancy judgment circuit of the present invention. In the redundancy judgment circuit of the second embodiment, instead of the N-channel MOS transistors N1 to N4 in the fuse circuit 101 of FIG.
Using each of the P-channel MOS transistors P1 to P4, the node n1 is moved to the ground side,
It is connected to the ground via a channel type MOS transistor N1. The node n1 is connected to an AND circuit 22 via a latch circuit 21. The latch circuit 21 has substantially the same configuration as the latch circuit 103 of FIG. 1, but uses an N-channel MOS transistor N2 instead of the P-channel MOS transistor P2. Further, the precharge signal P applied to the N-channel MOS transistor N1 and the address decode signals A1, A2, / A1, A2, A1, / A2, / A1,. We use things that are related.

The operation of such a redundancy judgment circuit will be described with reference to the timing chart shown in FIG. Here, the fuse f1 is cut in advance, and when the address decode signals A1 and A2 become high level, only the transistor N1 paired with the fuse f1 is turned on.

First, in the period up to the time point t1, the precharge signal P is at the low level and the N-channel MOS
The transistor N1 is turned off, and each address decode signal A1.
All of A2, / A1, A2, A1, / A2, / A1, / A2 are at the high level, and all of the transistors P1 to P4 are off.

During the period from time t1 to time t2, the precharge signal P is at the high level, and the N-channel type M
While the OS transistor N1 switches on,
Each address decode signal A1, A2, / A1, A2, A1,
/ A2, /A1./A2 remain at the high level, and all of the transistors P1 to P4 are kept off;
The node n1 is precharged to a low level regardless of the state of each of the fuses f1 to f4.

At time t2, the precharge signal P goes low, the N-channel MOS transistor N1 turns off, and the precharging of the node n1 ends.

At this time, if the addresses A1 and A2 are not redundantly replaced addresses, at the subsequent time t3, each of the other address decode signals /A1.A2, A1./A2, //, excluding the address decode signals A1 and A2. A1 / A2 goes low, and any of the transistors P2 to P4 that are paired with the uncut fuses f2 to f4 are turned on, and a current flows from the power supply potential Vcc to the node n1, This node n1 goes high.

However, the precharge period from time t1 to time t2 ends, the N-channel MOS transistor N1 is turned off, and the current path is cut off, so that the power supply potential Vcc changes to the node n1. The flowing current can be kept sufficiently small.

When the node n1 switches from low level to high level, the latch circuit 10
3, the N-channel MOS transistor N2 is turned on, but the N-channel MOS transistor N2 is turned on.
2 has a lower driving capability than the transistors P1 to P4 of the fuse circuit 101, the latch circuit 103 cannot hold the potential of the node n1 and the node n1 is quickly switched to a high level. Accordingly, the latch circuit 1
The output of the inverter INV 03 goes low, the N-channel MOS transistor N2 is turned off, and the current path from the latch circuit 103 to the fuse circuit 101 is cut off. Therefore, the current from the latch circuit 103 can be sufficiently reduced.

Alternatively, if the addresses A1 and A2 are redundantly replaced addresses, only the address decode signals A1 and A2 go low at time t3, and the transistors P1 paired with the blown fuse f1 are turned on. However, no current flows from the power supply potential Vcc to the node n1, and the low level of the node n1 is maintained.

The low level of the node n1 is kept held by the latch circuit 103.
Output of the inverter INV becomes high level.

Although the node n1 is set to either the high level or the low level between the time points t1 and t4, the chip internal activation signal ACT is maintained at the low level until the time point t4. , AND circuit 22
, That is, the redundancy activation signal SP maintains a low level.

At time t4, the chip internal activation signal ACT is switched to the high level, one input of the AND circuit 22 becomes the high level, and either the high level or the low level of the node n1 becomes the AND circuit. The signal is output as a redundancy activation signal SP via the line 22.

At time t5, chip internal activation signal ACT
Is switched to low level, one input of the AND circuit 22 becomes high level, and the redundancy activation signal SP returns to low level.

As described above, also in the redundancy judgment circuit of the second embodiment, the node n1 is precharged to the low level during the period from the time t1 to the time t2, the current path is cut off, and at the time t3, the address A1 , A2, one of the transistors P1 to P4 is turned on, so that the current flowing from the power supply potential Vcc to the node n1 can be sufficiently suppressed. Also, since the N-channel MOS transistor N2 of the latch circuit 103 has a lower driving capability than each of the transistors P1 to P4, the node n1 is quickly switched to a high level, and the N-channel MOS transistor N2 is turned off. Since the current path is cut off, the current flowing from the power supply potential Vcc to the node n1 can be sufficiently suppressed.

Further, even when there is no need to relieve the redundancy, the node n1 is not connected during the period from time t1 to time t2.
Is precharged to a low level, and at time t3, one of the transistors P1 to P4 is turned on.
Unnecessary current flowing from 1 to the ground side can be sufficiently suppressed.

The N-channel MOS transistor N
Instead of 1, a P-channel MOS transistor can be used. In this case, a signal / P obtained by inverting the precharge signal P may be used.

Next, one embodiment of the semiconductor memory device of the present invention will be described.

When the redundancy judgment circuit of each of the embodiments shown in FIGS. 1 and 3 is applied to a semiconductor memory device, it is necessary to generate a precharge signal and an address decode signal in the semiconductor memory device. An embodiment as shown in FIG. 5 may be adopted.

In FIG. 5, a precharge signal generation circuit 31 receives an external control signal and an external address signal,
A precharge signal is output in response to these signals.
The address decode circuit 32 receives the external address signal delayed by the delay circuit 33, decodes the external address signal, and outputs an address decode signal.

In a dynamic random access type semiconductor memory device, in the case of redundancy determination of a row address, a precharge signal generation circuit 31 outputs a row address strobe signal / signal as shown in the timing chart of FIG. RAS and external address signal A
d, the precharge signal / P is activated at the fall of the row address strobe signal / RAS to charge the node n1 of FIG. 1 or FIG.
After the charging of the node n1 is completed, the address decode circuit 32 outputs the address decode signals A1 and A2.

As is apparent from the timing chart of FIG. 6, external address signal Ad is input before row address strobe signal / RAS, but is delayed by delay circuit 33 before address decode circuit 32.
, The address decode signals A1 and A2 are active after the precharge signal / P becomes inactive. As a result, as described above, the current path is cut off, and the current flowing through the node n1 can be sufficiently reduced.

In the case of the redundancy judgment of the column address, FIG.
As shown in the timing chart of FIG. 7, the address transition detection signal ATD is generated before the column address strobe signal / CAS in accordance with the change of the external address signal Ad, so that the precharge signal generation circuit 31
An address transition detection signal ATD is inputted, and an external address signal Ad is inputted.
At the rise of TD, the precharge signal / P is activated to charge the node n1 in FIG. 1 or FIG. After the charging of the node n1 is completed and the current path is cut off, the address decode circuit 32 outputs the address decode signals A1 and A2.

Further, in the case of a static random access type semiconductor memory device, as shown in the timing chart of FIG. 8, before the chip select signal / CS, an address transition detection signal ATD is generated according to a change in the external address signal Ad.
Is generated, the precharge signal generation circuit 31 inputs the address transition detection signal ATD as an external control signal and the external address signal Ad, and at the rising edge of the address transition detection signal ATD, the precharge signal generation circuit 31 The signal / P is activated to charge the node n1 in FIG. 1 or FIG. After the charging of the node n1 is completed and the current path is cut off, the address decode circuit 32 outputs the address decode signals A1 and A2.

[0087]

As described above, according to the redundancy judgment circuit of the first aspect, when it is necessary to relieve the redundancy, if the address replaces the redundancy, each transistor corresponding to this address is used. Is turned on, if the fuse paired with this transistor is cut in advance, the high level of the node is held, the high level of this node is latched by the latch means, and the output of this latch means is The activation unit activates the redundancy activation signal corresponding to the high level and outputs the redundancy activation signal.

If the address is not an address that can be replaced redundantly, although a current flows from the node through one of the switching elements, the potential of the node is precharged by the precharge means, and thereafter, each switching element is set in accordance with the address. Based on the procedure of selectively turning on the node, when the current flows from the node, the pre-jersey of the potential of the node is terminated, and unnecessary current can be sufficiently reduced.

Further, when there is no need to repair redundancy,
Do not blow any of the fuses. In this state, when the node is precharged and then each switching element is selectively turned on, current flows from the node through one of the switching elements, but at this time, the pre-jersey of the potential of the node is terminated. Therefore, unnecessary current can be sufficiently reduced.

If the address is not the address that replaces the redundancy or if it is not necessary to relieve the redundancy, the potential of the node becomes the reference potential, and this reference potential is latched by the latch means. The output of the latch means is activated by the activation means. Activated, a redundant activation signal corresponding to the reference potential is output from the activating means.

As described in claim 2, each series circuit is inserted between the node and the ground potential, and the precharge means is a P-channel MOS transistor inserted between the power supply and the node. When a low-level precharge signal is input to the gate of the type MOS transistor, the node may be precharged to the power supply potential via the P-channel type MOS transistor.

Further, as described in claim 3, each series circuit is inserted between a node and a ground potential, and the precharge means comprises:
An N-channel MOS transistor inserted between a power supply and a node. When a high-level precharge signal is input to the gate of the N-channel MOS transistor, the node is connected via the N-channel MOS transistor. It may be precharged to the power supply potential.

Alternatively, as described in claim 4, each series circuit is inserted between a node and a potential of a power supply, and the precharge means includes an N-channel type M inserted between the node and a ground potential.
When a high-level precharge signal is input to the gate of the N-channel MOS transistor, the node may be precharged to the ground potential via the N-channel MOS transistor.

Further, each series circuit is inserted between the node and the ground potential, the latch means inverts and outputs the potential of the node, and the activating means outputs the output of the latch means. Alternatively, the NOR logic of the signal obtained by inverting the chip internal activation signal may be obtained, and the result may be output as a redundant activation signal.

Alternatively, each series circuit is inserted between the node and the potential of the power supply, and the latch means comprises:
The activation means may invert and output the potential of the node, obtain the AND logic of the output of the latch means and the chip internal activation signal, and output the result as a redundant activation signal.

Next, according to the semiconductor memory device of the present invention, in response to the input of the external control signal and the external address, the timing for activating the precharge means is determined, and the external address is decoded into an address. By delaying this address and applying it to the switching elements of each series circuit, a procedure of precharging the node and then selectively turning on each switching element is realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a redundancy judgment circuit according to the present invention;

FIG. 2 is a timing chart showing signals in the redundancy judgment circuit of FIG. 1;

FIG. 3 is a block diagram showing a second embodiment of the redundancy judgment circuit of the present invention;

FIG. 4 is a timing chart showing the timing of each signal in the redundancy judgment circuit of FIG. 3;

FIG. 5 is a block diagram showing one embodiment of a semiconductor memory device of the present invention;

6 is a timing chart showing the timing of each signal in the semiconductor memory device of FIG.

FIG. 7 is a timing chart showing another timing of each signal in the semiconductor memory device of FIG. 5;

FIG. 8 is a timing chart showing another timing of each signal in the semiconductor memory device of FIG. 5;

FIG. 9 is a block diagram showing a conventional redundancy judgment circuit.

10 is a timing chart showing the timing of each signal in the redundancy judgment circuit of FIG.

FIG. 11 is a block diagram showing another conventional redundancy judgment circuit.

FIG. 12 is a timing chart showing the timing of each signal in the redundancy judgment circuit of FIG. 11;

FIG. 13 is a block diagram showing another conventional redundancy judgment circuit.

14 is a timing chart showing the timing of each signal in the redundancy judgment circuit of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 NOR circuit 12 Inverter 21 Latch circuit 22 AND circuit 31 Precharge signal generation circuit 32 Address decode circuit 33 Delay circuit 101 Fuse circuit 103 Latch circuit 104 Inverter A1, A2 Address A1, A2, / A1, A2, A1, / A2, / A1, / A2 Address decode signal ACT Chip internal activation signal Ad External address signal ATD Address transition detection signal / CAS Column address strobe signal / CS Chip select signal f1 to f4 Fuse INV Inverter N1 to N4 N-channel MOS transistor n1 node P1 to P4 P-channel type MOS transistor P, / P Precharge signal SP Redundancy activation signal / RAS Row address strobe signal

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[Procedure amendment]

[Submission date] June 17, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

Patent application title: Redundancy determination circuit and semiconductor memory device

[Claims]

8. The redundancy according to claim 1, wherein :
Equipped with a judgment circuit and is a dynamic random access type.
In a semiconductor memory device, a precharge operation is performed in response to a row address strobe signal.
Activate the precharge signal applied to the stage and
Generating means for starting the precharging means
And decode the external address into an address
Delay to the switching element of each series circuit.
And a dress decode delay means , so that the precharge signal once activated becomes inactive.
Address, switching the address of each series circuit
A semiconductor memory device to be given to an element.

9. The redundancy of any one of claims 1 to 6
Equipped with a judgment circuit and is a dynamic random access type.
In a semiconductor memory device, a precharge means responds to a change in an external address signal.
Activates the precharge signal applied to
Precharge generating means for activating the precharge means;
Decode the external address into an address,
The address given to the switching element of each series circuit with a delay
And a decode delay means , so that the precharge signal once activated becomes inactive.
Address, switching the address of each series circuit
A semiconductor memory device to be given to an element.

10. The redundancy according to claim 1, wherein
Equipped with length judgment circuit, static random access type
In a semiconductor memory device, a precharge unit responds to a change in an external address signal.
Activates the precharge signal applied to
Precharge generating means for activating the precharge means;
Decode the external address into an address,
The address given to the switching element of each series circuit with a delay
And a decode delay means , so that the precharge signal once activated becomes inactive.
Address, switching the address of each series circuit
A semiconductor memory device to be given to an element.

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a redundancy judgment circuit,
And a semiconductor memory device to which the redundancy judgment circuit is applied.

[0002]

2. Description of the Related Art As this kind of conventional redundancy judgment circuit,
There is one as shown in FIG. In FIG. 1, a fuse circuit 101 includes fuses f1 to f4 and a transistor N1.
To N4 in series.
These series circuits are inserted between the node n1 and the ground potential. Each address decode signal A1, A2, / A1, A2,
A1 / A2, / A1 / A2 are 2-bit addresses A
1, A2 are decoded, and these address decode signals A1, A2, / A1, A2, A1, / A2, / A1,.
/ A2 is applied to each of the transistors N1 to N4, and any one of these transistors N1 to N4 is selectively turned on.

Here, for simplicity, 2-bit addresses A1 and A2 are illustrated, but in general, in the case of an n-bit address, there are 2 ⁿ types of decoded signals. Provide ²ⁿ sets of fuses and transistors.

A P-channel MOS transistor P1 has
A signal / P is applied to the gate, and when the signal / P is at a low level, the P-channel MOS transistor P1 is turned on. As a result, the power supply potential Vcc is applied to the node n1 via the P-channel MOS transistor P1, and this node n1 becomes high level (power supply potential Vcc).
Is charged.

At this time, if the addresses A1 and A2 are redundantly replaced addresses, any one of the transistors N1 to N4 corresponding to the address is turned on, so that the fuse paired with the on transistor is cut in advance. If so, the high level of this node n1 is held, inverted by the latch circuit 103, and
4 is output as a high-level redundancy activation signal SP. This redundant activation signal SP
It is used to select a memory cell for redundancy.

For example, when the fuse f1 is cut in advance and the address decode signals A1 and A2 go high, the transistor N
When only 1 is turned on, the operation as shown in the timing chart of FIG. 10 is performed.

First, when the address decode signals A1 and A2 go to a high level, only the transistor N1 turns on.
The channel type MOS transistor P1 is turned on, and the node n1 is charged to a high level.

Even when the transistor N1 is turned on, the fuse f1 is cut in advance and the other transistors N1 to N4 are turned off, so that the node N1 is not connected to the ground potential and maintains a high level. I do.

[0009] Even after the P-channel MOS transistor P1 is turned off, the high level of the node N1 is kept held by the latch circuit 103. Latch circuit 1
03 outputs the inverted level of the node N1, and the output is inverted again by the inverter 104 to output a high-level redundancy activation signal SP, and this redundancy activation signal SP becomes active.

If the addresses A1 and A2 are not addresses that are redundantly replaced, the other signals /A1.A2, A1.
One of / A2, / A1,... / A2 goes high, turning on one of the other transistors N2 to N4. At this time, since the other fuses f2 to f4 are not blown, the node N1 is connected to the other transistors N2 to N4.
4, the node N1 goes low, the redundancy activation signal SP goes low, and becomes inactive.

However, even if the node N1 is grounded via any of the other transistors N2 to N4, the signal / P becomes low level and the P-channel type
Since the S transistor P1 is turned on and the node n1 is about to be charged to a high level, the P-channel MOS
Unnecessary current flows from the transistor P1 to the ground via one of the other transistors N2 to N4.

If it is not necessary to repair the redundancy,
Since neither fuse is blown, each transistor N
Regardless of which of 1 to N4 is turned on, when the signal / P is at a low level, the P-channel MOS transistor P1 is turned on, and an unnecessary current flows from the P-channel MOS transistor P1 to the ground side.

Next, in order to suppress such unnecessary current, Japanese Unexamined Patent Publication No. 4-216398 discloses a configuration shown in FIG.
Has been proposed. In this redundancy judgment circuit, unnecessary current is suppressed when there is no need to repair the redundancy, that is, when none of the fuses is cut.

In this redundancy judgment circuit, a redundancy operation switching circuit 111, an OR circuit 112, and an N-channel MOS transistor N5 are added to the circuit of FIG.

If there is no need to repair the redundancy, the fuse f5 of the redundancy operation switching circuit 111 is not cut. At this time, since a high-level signal is always applied from the redundant operation switching circuit 111 to the OR circuit 112, the signal / P
High level signal is applied from the OR circuit 112 to the P-channel MOS transistor P1, regardless of the level of the P-channel MOS transistor P1, and the P-channel MOS transistor P1 is always turned off. As a result, unnecessary current does not flow to the ground side.

If redundancy needs to be relieved,
The fuse f5 of the redundant operation switching circuit 111 is cut. At this time, the redundant operation switching circuit 111 switches the OR circuit 11
2, the level of the signal / P is transmitted to the P-channel MOS transistor P1 via the OR circuit 112, and the P-channel MOS transistor P1 is turned on in accordance with the level of the signal / P. Turn on and off.

Further, each fuse f of the fuse circuit 101
Any one of 1 to f4 is cut in advance. For example, when the fuse f1 is cut in advance and only the transistor N1 paired with the fuse f1 is turned on, the operation as shown in the timing chart of FIG. 12 is performed.

First, when the address decode signals A1 and A2 go high, only the transistor N1 turns on. Subsequently, at time t0, when each signal / P, / EN goes low, the P-channel MOS transistor P
1 turns on, and the N-channel MOS transistor N5
Is turned off, and the node n1 is charged to a high level.

At time tE, even after the signal / P goes high and the P-channel MOS transistor P1 is turned off, the high level of the node n1 remains at the latch circuit 103.
, And is inverted twice by the latch circuit 103 and the inverter 104 to output a high-level redundancy activation signal SP.
P becomes active.

However, also in this circuit, if the addresses A1 and A2 are not redundantly replaced addresses,
When the signal / P goes low when the node N1 is grounded via any of the other transistors N2 to N4, the P-channel MOS transistor P1 turns on, and the node n1 goes high. Unnecessary current flows from the P-channel type MOS transistor P1 to the ground side via any one of the other transistors N2 to N4 because it is about to be charged.

Next, Japanese Patent Laying-Open No. 5-258590 proposes a redundancy judgment circuit as shown in FIG. In this redundancy determination circuit, unnecessary current is suppressed when redundancy needs to be relieved, that is, when one of the fuses is cut.

In this redundancy judgment circuit, each transistor t1, t2, t3 and each fuse f1, f2, f3 are connected in series by one pair,
1 ', t2', t3 'and respective fuses f1', f2 ', f3' are connected in series by one series, and each input terminal m1, m2 for inputting each address input signal A1, A2, A3. , M
3 and a fuse circuit composed of the inverters INV1, INV2, INV3, and furthermore, transfer gates c1, c2, c3 are inserted between the transistors t1, t2, t3 and the input terminals m1, m2, m3. At the same time, each transistor t1 ', t2', t3 'and each inverter INV1, INV2, I
Transfer gates c1 ', c between NV3
2 ′ and c3 ′ are inserted, and each transistor t1, t2, t3,
In order to set the gate sides of t1 ', t2', and t3 'to low level, each of the N-channel MOS transistors d1, d2, d
3, d1 ', d2', and d3 'are provided. Then, each transfer gate c1, c2, c3, c1 ', c2', c3 '
, A precharge signal P is inputted to each of the N-channel MOS transistors d1, d2, d3, d1 ', d
The gates of 2 'and d3' are configured to receive the inverted phase signal of the precharge signal P inverted by the inverter INV. As a result, when the precharge signal P goes low to precharge the node n1, each of the N-channel MOS transistors d1, d2,.
d3, d1 ', d2', d3 'are turned off.

The operation of the redundancy judgment circuit having such a configuration is shown in FIG.
4 will be described according to the timing chart.

First, when the precharge signal P goes low, the P-channel MOS transistor tp turns on. During the low level period of the precharge signal P,
Node n1 is precharged to a high level. At this time, regardless of the level of each address input signal A1, A2, A3, each transfer gate c1, c2, c3, c
1 ', c2', c3 'are all turned off, and the respective N-channel MOS transistors d1, d2, d3, d1', d2 ',
All of d3 'are on. Therefore, the gates of the transistors t1, t2, t3, t1 ', t2', t3 'are all at a low level, and all of the transistors t1, t2, t3, t1', t2 ', t3' Turns off.

On the other hand, when the precharge signal P goes high, each of the N-channel MOS transistors d1, d2,
All of d3, d1 ', d2', d3 'are turned off, and each transfer gate c1, c2, c3, c1', c2 ',
All of c3 'are turned on.

Here, for example, each address input signal A1,
When A2 and A3 are at high level, low level and low level (address "100"), each transistor t1,.
t2 'and t3' are turned on. These transistors t
Each fuse f1, f2 ', f paired with 1, t2', t3 '
Since 3 'is disconnected, the high level of the node n1 is held, and the high level redundancy activation signal SP is output.

Further, for example, each address input signal A1, A
2, A3 are at low level, high level and low level (address "010"), and when the precharge signal P is at low level, each transfer gate c1, c2, c
3, c1 ', c2', c3 'are all turned off, and the N-channel MOS transistors d1, d2, d3, d1', d2 ',
Since all of d3 'are turned on, the transistors t1, t
2, t3, t1 ', t2', and t3 'are all turned off.

When the precharge signal P goes high, each of the N-channel MOS transistors d1, d
2, d3, d1 ', d2', d3 'are all turned off, and each transfer gate c1, c2, c3, c1', c2 ',
All of the transistors c1 'and t3' are turned on.
2, t3 'is turned on. These transistors t1 ',
Since f1 'and f2 of the fuses paired with t2 and t3' are not cut, the potential of the node n1 passes to the ground via the fuses f1 'and f2 and the transistors t1' and t2. Node n1 goes low.

As described above, while the precharge signal P is at the low level and the node n1 is being precharged, all of the transistors t1, t2, t3, t1 ', t2', t3 'are turned off. Unnecessary current does not flow from the node n1 to the ground potential.

[0030]

As described above, in the conventional redundancy judging circuit shown in FIG. 9, when it is necessary to repair the redundancy, if the addresses A1 and A2 are not addresses that replace the redundancy, the node n1 is connected to each transistor. In the state where the node n1 is grounded via any one of the above, the node n1 tends to be charged to a high level, so that an unnecessary current flows from the P-channel MOS transistor P1 to the ground via any one of the transistors.

Alternatively, when it is not necessary to relieve the redundancy, none of the fuses is blown. Therefore, even if any of the transistors N1 to N4 is turned on, when the signal / P is at a low level, the P-channel MOS Transistor P
1 is turned on, and the P-channel MOS transistor P1
Unnecessary current flows from the ground to the ground.

The other conventional redundancy judgment circuit shown in FIG. 11 can suppress unnecessary current when there is no need to relieve the redundancy. If A1 and A2 are not redundantly replaced addresses, the node n1 will be charged to a high level while the node N1 is grounded via one of the transistors. Unnecessary current flows to the ground side.

Further, in another conventional redundancy judgment circuit shown in FIG. 13, although unnecessary current when redundancy needs to be relieved can be suppressed, each element in a range surrounded by a broken line in FIG. Each N-channel MOS transistor d
1, d2, d3, d1 ', d2', d3 ', and transfer gates c1, c2, c3, c1', c2 ', c3', etc., must be provided and compared with the redundancy judgment circuits of FIGS. 9 and 11. do it,
There is a disadvantage that the circuit configuration becomes complicated and the circuit scale becomes large.

Accordingly, the present invention is to solve such a conventional problem, and can suppress unnecessary current flowing through the fuse circuit regardless of the necessity of relieving redundancy. It is an object of the present invention to provide a redundancy judgment circuit and a semiconductor memory device that do not require a relatively large circuit scale.

[0035]

According to a first aspect of the present invention, a plurality of series circuits each having a switching element and a fuse connected in series are inserted between a node and a reference potential. Selectively disconnect any one of the fuses, selectively turn on each switching element according to the address, and respond to the potential of the node when the switching element paired with the blown fuse is turned on. A redundancy determination circuit that outputs a redundant activation signal
With each switching element turned off, a precharge means for precharging the potential of the node, a latch means for latching the potential of the node, and an output of the latch means are activated to activate a redundant active circuit corresponding to the output. Activating means for outputting an activation signal, wherein the potential of the node is precharged by the precharge means, and thereafter, each switching element is selectively turned on in accordance with the address, and then the potential of the node is latched by the latch means. Then, the output of the latch means is activated by the activation means.

According to such a configuration, first, when redundancy needs to be remedied, if the address is an address that replaces the redundancy, one of the transistors corresponding to this address is turned on. If the fuse paired with the node is cut in advance, the high level of the node is held, the high level of this node is latched by the latching means, and the output of this latching means is activated by the activating means to be at the high level. A corresponding redundancy activation signal is output from the activation means.

If the address is not an address which is redundantly replaced, although a current flows from the node through one of the switching elements, the potential of the node is precharged by the precharge means, and thereafter, each switching element is changed in accordance with the address. Based on the procedure of selectively turning on the node, when the current flows from the node, the pre-jersey of the potential of the node is terminated, and unnecessary current can be sufficiently reduced.

Further, when there is no need to repair redundancy,
Do not blow any of the fuses. In this state, when the node is precharged and then each switching element is selectively turned on, current flows from the node through one of the switching elements, but at this time, the pre-jersey of the potential of the node is terminated. Therefore, unnecessary current can be sufficiently reduced.

If the address is not an address that replaces the redundancy or if it is not necessary to relieve the redundancy, the potential of the node becomes the reference potential, and this reference potential is latched by the latch means. The output of the latch means is activated by the activation means. Activated, a redundant activation signal corresponding to the reference potential is output from the activating means.

As described in claim 2, each series circuit is inserted between the node and the ground potential, and the precharge means is a P-channel MOS transistor inserted between the power supply and the node. When a low-level precharge signal is input to the gate of the type MOS transistor, the node may be precharged to the power supply potential via the P-channel type MOS transistor.

Further, as described in claim 3, each series circuit is inserted between a node and a ground potential, and the precharge means comprises:
An N-channel MOS transistor inserted between a power supply and a node. When a high-level precharge signal is input to the gate of the N-channel MOS transistor, the node is connected via the N-channel MOS transistor. It may be precharged to the power supply potential.

Alternatively, as described in claim 4, each series circuit is inserted between the node and the potential of the power supply, and the precharge means is an N-channel type M inserted between the node and the ground potential.
When a high-level precharge signal is input to the gate of the N-channel MOS transistor, the node may be precharged to the ground potential via the N-channel MOS transistor.

Further, as described in claim 5, each series circuit is inserted between a node and a ground potential, the latch means inverts and outputs the potential of the node, and the activating means outputs the output of the latch means. Alternatively, the NOR logic of the signal obtained by inverting the chip internal activation signal may be obtained, and the result may be output as a redundant activation signal.

Alternatively, as described in claim 6, each series circuit is inserted between a node and a potential of a power supply, and the latch means comprises:
The activation means may invert and output the potential of the node, obtain the AND logic of the output of the latch means and the chip internal activation signal, and output the result as a redundant activation signal.

Next, the invention according to claim 7 is directed to claim 1
7. In the semiconductor memory device provided with the redundancy judgment circuit according to any one of the above items, the precharge signal applied to the precharge means is activated in response to the input of the external control signal and the external address, and the precharge means is activated. And an address decode delay means for decoding an external address into an address, delaying the address, and applying the delayed address to a switching element of each serial circuit, so that the precharge signal once activated becomes inactive. After that, the address is given to the switching element of each series circuit.

That is, in this semiconductor memory device, in response to the input of the external control signal and the external address, the timing for activating the precharge means is determined, the external address is decoded into an address, and the serial address is delayed by delaying this address. By providing the switching elements of the circuit, the node is precharged, and thereafter, the procedure of selectively turning on each switching element is realized.

The invention described in claim 8 is the first invention.
And a redundancy judgment circuit according to any one of
Mick random access type semiconductor memory device
In response to the row address strobe signal,
Activates the precharge signal applied to the
Precharge occurs to activate this precharge means.
Means and decodes the external address into an address,
Delay the dress and give it to the switching element of each series circuit.
Address decode delay means
Whether the precharge signal is disabled
Then, give the address to the switching element of each series circuit.
I have.

Again, in response to the row address strobe signal,
The timing to activate the precharge means.
Delay the address, and switch the switching element of each series circuit.
To precharge the node,
A hand to selectively turn on each switching element later
The order has been realized.

Alternatively, the ninth aspect of the present invention provides
Item 9 includes the redundancy judgment circuit according to any one of Items 1 to 6,
For dynamic random access semiconductor memory devices
In response to a change in the external address signal,
Activates the precharge signal applied to the charging means
Precharge occurs to activate this precharge means.
Means and decodes the external address into an address,
Delay the dress and give it to the switching element of each series circuit.
Address decode delay means
Whether the precharge signal is disabled
Then, give the address to the switching element of each series circuit.
I have.

Similarly, the invention according to claim 10 is
Item 8 includes the redundancy judgment circuit according to any one of Items 1 to 6,
For semiconductor memory devices of the static random access type
In response to a change in the external address signal,
Activates the precharge signal applied to the charging means
Precharge occurs to activate this precharge means.
Means and decodes the external address into an address,
Delay the dress and give it to the switching element of each series circuit.
Address decode delay means
Whether the precharge signal is disabled
Then, give the address to the switching element of each series circuit.
I have.

In the ninth and tenth aspects, the external
Activates the precharge means in response to the change of the address signal.
To determine the timing of each series circuit.
Preset nodes by applying to switching elements.
Charge and then selectively turn on each switching element.
It implements the procedure to turn on.

[0052]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a first embodiment of the redundancy judgment circuit of the present invention. In the redundancy judgment circuit of the first embodiment, the inverter 10 of the circuit of FIG.
4, a NOR circuit 11 and an inverter 12 are provided. The P-channel type MOS of the latch circuit 103
As the transistor P2, a transistor having a lower driving ability than each of the transistors N1 to N4 of the fuse circuit 101 is applied. Further, each address decode signal A1, A2, / A
The timings of 1.A2, A1./A2, /A1./A2 and the precharge signal / P are different, and the chip 12 activation signal ACT is applied to the inverter 12.

The operation of such a redundancy judgment circuit will be described with reference to the timing chart shown in FIG. Here, the fuse f1 is cut in advance, and when the address decode signals A1 and A2 become high level, only the transistor N1 paired with the fuse f1 is turned on.

First, in the period up to the time point t1, the precharge signal / P is at the high level and the P-channel type MO
The S transistor P1 is turned off, and each address decode signal A1
All of A2, / A1, A2, A1, / A2, / A1, / A2 are at low level, and all of the transistors N1 to N4 are off.

In the period from time t1 to time t2, the precharge signal / P is at the low level and the P-channel MOS transistor P1 is turned on, whereas the address decode signals A1, A2, / A1, A2, A
1 / A2, /A1./A2 are all kept at the low level, all the transistors N1 to N4 are kept off, and the node n is independent of the state of each fuse f1 to f4.
1 is precharged to high level.

At time t2, the precharge signal / P goes high, the P-channel MOS transistor P1 turns off, and the precharging of the node n1 ends.

At this time, if the addresses A1 and A2 are not redundantly replaced addresses, at the subsequent time t3, each of the other address decode signals /A1.A2, A1./A2, / except for the address decode signals A1 and A2. One of A1 / A2 becomes high level, and one of the transistors N2 to N4 paired with the uncut fuses f2 to f4 is turned on, and a current flows from the node n1 to the ground side. Node n1 goes low.

However, since the precharge period from time t1 to time t2 has ended and the P-channel MOS transistor P1 has been turned off, the current path is cut off and the current flowing from node n1 to the ground side. Can be kept sufficiently small.

When the node n1 switches from high level to low level, the latch circuit 10
3, the P-channel MOS transistor P2 is turned on, but the P-channel MOS transistor P2
2 has a lower driving capability than the transistors N1 to N4 of the fuse circuit 101, the latch circuit 103 cannot hold the potential of the node n1 and the node n1 is quickly switched to a low level. Accordingly, the latch circuit 1
The output of the inverter INV 03 goes high, the P-channel MOS transistor P2 is turned off, and the current path from the latch circuit 103 to the fuse circuit 101 is cut off. Therefore, the current from the latch circuit 103 can be sufficiently reduced.

Alternatively, if the addresses A1 and A2 are redundantly replaced addresses, only the address decode signals A1 and A2 go high at time t3, and the transistors N1 paired with the blown fuse f1 are turned on. However, no current flows from the node n1 to the ground side, and the high level of the node n1 is maintained.

The high level of the node n1 is continuously held by the latch circuit 103.
Output of the inverter INV becomes low level.

Although the node n1 is set to either the high level or the low level from the time point t1 to the time point t4, the chip internal activation signal ACT is kept at the low level until the time point t4. , Inverter 12
Is at a high level, and the output of the NOR circuit 11, that is, the redundancy activation signal SP is maintained at a low level.

At time t4, the chip internal activation signal ACT is switched to the high level, one input of the NOR circuit 11 goes to the low level, and either the high level or the low level of the node n1 becomes the NOR circuit. The signal is output as a redundancy activation signal SP via the line 11. Table 1 below shows the level of the redundant activation signal SP with respect to the level of the node n1 and the level of the chip internal activation signal ACT.

[0064]

[Table 1]

At time t5, chip internal activation signal ACT
Is switched to low level, one input of the NOR circuit 11 becomes high level, and the redundancy activation signal SP returns to low level.

As described above, in the redundancy judgment circuit of the first embodiment, during the period from time t1 to time t2, the node n1 is precharged to a high level, the current path is cut off, and at time t3, the address Since any one of the transistors N1 to N4 is turned on in accordance with A1 and A2, the node n
Unnecessary current flowing from 1 to the ground side can be suppressed. Further, the P-channel type M of the latch circuit 103
Since the OS transistor P2 has a lower driving capability than each of the transistors N1 to N4, the node n1 is quickly switched to the low level, and the P-channel MOS transistor P2
Is turned off, and the current path is cut off, so that the current from the latch circuit 103 can be sufficiently suppressed.

Further, even when there is no need to relieve the redundancy, the node n1 is not connected during the period from time t1 to time t2.
Is precharged to a high level, and at time t3, one of the transistors N1 to N4 is turned on.
Unnecessary current flowing from 1 to the ground side can be sufficiently suppressed.

The P-channel MOS transistor P
Instead of 1, an N-channel MOS transistor can be applied. In this case, the precharge signal / P
May be used.

FIG. 3 shows a second embodiment of the redundancy judgment circuit of the present invention. In the redundancy judgment circuit of the second embodiment, instead of the N-channel MOS transistors N1 to N4 in the fuse circuit 101 of FIG.
Using each of the P-channel MOS transistors P1 to P4, the node n1 is moved to the ground side,
It is connected to the ground via a channel type MOS transistor N1. The node n1 is connected to an AND circuit 22 via a latch circuit 21. The latch circuit 21 has substantially the same configuration as the latch circuit 103 of FIG. 1, but uses an N-channel MOS transistor N2 instead of the P-channel MOS transistor P2. Further, the precharge signal P applied to the N-channel MOS transistor N1 and the address decode signals A1, A2, / A1, A2, A1, / A2, / A1,. We use things that are related.

The operation of such a redundancy judgment circuit will be described with reference to the timing chart shown in FIG. Here, the fuse f1 is cut in advance, and when the address decode signals A1 and A2 become high level, only the transistor N1 paired with the fuse f1 is turned on.

First, in the period up to the time t1, the precharge signal P is at the low level and the N-channel MOS
The transistor N1 is turned off, and each address decode signal A1.
All of A2, / A1, A2, A1, / A2, / A1, / A2 are at the high level, and all of the transistors P1 to P4 are off.

During the period from time t1 to time t2, the precharge signal P goes high, and the N-channel type M
While the OS transistor N1 switches on,
Each address decode signal A1, A2, / A1, A2, A1,
/ A2, /A1./A2 remain at the high level, and all of the transistors P1 to P4 are kept off;
The node n1 is precharged to a low level regardless of the state of each of the fuses f1 to f4.

At time t2, the precharge signal P goes low, the N-channel MOS transistor N1 turns off, and the precharging of the node n1 ends.

At this time, if the addresses A1 and A2 are not addresses that are redundantly replaced, at the subsequent time t3, each of the other address decode signals / A1, A2, A1, / A2, /, excluding the address decode signals A1, A2. A1 / A2 goes low, and any of the transistors P2 to P4 that are paired with the uncut fuses f2 to f4 are turned on, and a current flows from the power supply potential Vcc to the node n1, This node n1 goes high.

However, since the precharge period from time t1 to time t2 ends, the N-channel MOS transistor N1 is turned off, and the current path is cut off, so that the power supply potential Vcc changes to the node n1. The flowing current can be kept sufficiently small.

When the node n1 switches from low level to high level, the latch circuit 10
3, the N-channel MOS transistor N2 is turned on, but the N-channel MOS transistor N2 is turned on.
2 has a lower driving capability than the transistors P1 to P4 of the fuse circuit 101, the latch circuit 103 cannot hold the potential of the node n1 and the node n1 is quickly switched to a high level. Accordingly, the latch circuit 1
The output of the inverter INV 03 goes low, the N-channel MOS transistor N2 is turned off, and the current path from the latch circuit 103 to the fuse circuit 101 is cut off. Therefore, the current from the latch circuit 103 can be sufficiently reduced.

Alternatively, if the addresses A1 and A2 are redundantly replaced addresses, only the address decode signals A1 and A2 go low at time t3, and the transistors P1 paired with the blown fuse f1 are turned on. However, no current flows from the power supply potential Vcc to the node n1, and the low level of the node n1 is maintained.

The low level of the node n1 is kept being held by the latch circuit 103.
Output of the inverter INV becomes high level.

While the node n1 is set to either the high level or the low level between the time points t1 and t4, the chip internal activation signal ACT is kept at the low level until the time point t4. , AND circuit 22
, That is, the redundancy activation signal SP maintains a low level.

At time t4, the chip internal activation signal ACT is switched to the high level, one input of the AND circuit 22 becomes the high level, and either the high level or the low level of the node n1 becomes the AND circuit. The signal is output as a redundancy activation signal SP via the line 22.

At time t5, chip internal activation signal ACT
Is switched to low level, one input of the AND circuit 22 becomes high level, and the redundancy activation signal SP returns to low level.

As described above, also in the redundancy judgment circuit of the second embodiment, the node n1 is precharged to the low level during the period from the time t1 to the time t2, and the current path is cut off. , A2, one of the transistors P1 to P4 is turned on, so that the current flowing from the power supply potential Vcc to the node n1 can be sufficiently suppressed. Also, since the N-channel MOS transistor N2 of the latch circuit 103 has a lower driving capability than each of the transistors P1 to P4, the node n1 is quickly switched to a high level, and the N-channel MOS transistor N2 is turned off. Since the current path is cut off, the current flowing from the power supply potential Vcc to the node n1 can be sufficiently suppressed.

Further, even when there is no need to relieve the redundancy, the node n1 is not connected during the period from time t1 to time t2.
Is precharged to a low level, and at time t3, one of the transistors P1 to P4 is turned on.
Unnecessary current flowing from 1 to the ground side can be sufficiently suppressed.

The N-channel MOS transistor N
Instead of 1, a P-channel MOS transistor can be used. In this case, a signal / P obtained by inverting the precharge signal P may be used.

Next, one embodiment of the semiconductor memory device of the present invention will be described.

When the redundancy judgment circuit of each of the embodiments shown in FIGS. 1 and 3 is applied to a semiconductor memory device, it is necessary to generate a precharge signal and an address decode signal in the semiconductor memory device. An embodiment as shown in FIG. 5 may be adopted.

In FIG. 5, a precharge signal generation circuit 31 receives an external control signal and an external address signal,
A precharge signal is output in response to these signals.
The address decode circuit 32 receives the external address signal delayed by the delay circuit 33, decodes the external address signal, and outputs an address decode signal.

In the dynamic random access type semiconductor memory device, in the case of redundancy determination of a row address, the precharge signal generation circuit 31 outputs a row address strobe signal / signal as shown in the timing chart of FIG. RAS and external address signal A
d, the precharge signal / P is activated at the fall of the row address strobe signal / RAS to charge the node n1 of FIG. 1 or FIG.
After the charging of the node n1 is completed, the address decode circuit 32 outputs the address decode signals A1 and A2.

As is clear from the timing chart of FIG. 6, external address signal Ad is input before row address strobe signal / RAS, but is delayed by delay circuit 33 before address decode circuit 32.
, The address decode signals A1 and A2 are active after the precharge signal / P becomes inactive. As a result, as described above, the current path is cut off, and the current flowing through the node n1 can be sufficiently reduced.

In the case of the redundancy judgment of the column address, FIG.
As shown in the timing chart of FIG. 7, the address transition detection signal ATD is generated before the column address strobe signal / CAS in accordance with the change of the external address signal Ad, so that the precharge signal generation circuit 31
An address transition detection signal ATD is inputted, and an external address signal Ad is inputted.
At the rise of TD, the precharge signal / P is activated to charge the node n1 in FIG. 1 or FIG. After the charging of the node n1 is completed and the current path is cut off, the address decode circuit 32 outputs the address decode signals A1 and A2.

Further, in the case of the semiconductor memory device of the static random access type, as shown in the timing chart of FIG. 8, before the chip select signal / CS, the address transition detection signal ATD according to the change of the external address signal Ad.
Is generated, the precharge signal generation circuit 31 inputs the address transition detection signal ATD as an external control signal and the external address signal Ad, and at the rising edge of the address transition detection signal ATD, the precharge signal generation circuit 31 The signal / P is activated to charge the node n1 in FIG. 1 or FIG. After the charging of the node n1 is completed and the current path is cut off, the address decode circuit 32 outputs the address decode signals A1 and A2.

[0092]

As described above, according to the redundancy judgment circuit of the first aspect, when it is necessary to relieve the redundancy, if the address replaces the redundancy, each transistor corresponding to this address is used. Is turned on, if the fuse paired with this transistor is cut in advance, the high level of the node is held, the high level of this node is latched by the latch means, and the output of this latch means is The activation unit activates the redundancy activation signal corresponding to the high level and outputs the redundancy activation signal.

If the address is not an address that can be replaced redundantly, although a current flows from the node through one of the switching elements, the potential of the node is precharged by the precharge means, and thereafter, each switching element is changed according to the address. Based on the procedure of selectively turning on the node, when the current flows from the node, the pre-jersey of the potential of the node is terminated, and unnecessary current can be sufficiently reduced.

Further, when there is no need to repair redundancy,
Do not blow any of the fuses. In this state, when the node is precharged and then each switching element is selectively turned on, current flows from the node through one of the switching elements, but at this time, the pre-jersey of the potential of the node is terminated. Therefore, unnecessary current can be sufficiently reduced.

If the address is not the address that replaces the redundancy or if it is not necessary to relieve the redundancy, the potential of the node becomes the reference potential, and this reference potential is latched by the latch means. The output of the latch means is activated by the activation means. Activated, a redundant activation signal corresponding to the reference potential is output from the activating means.

As described in claim 2, each series circuit is inserted between a node and a ground potential, and the precharge means is a P-channel MOS transistor inserted between a power supply and the node. When a low-level precharge signal is input to the gate of the type MOS transistor, the node may be precharged to the power supply potential via the P-channel type MOS transistor.

Further, as described in claim 3, each series circuit is inserted between the node and the ground potential, and the precharge means comprises:
An N-channel MOS transistor inserted between a power supply and a node. When a high-level precharge signal is input to the gate of the N-channel MOS transistor, the node is connected via the N-channel MOS transistor. It may be precharged to the power supply potential.

Alternatively, as described in claim 4, each series circuit is inserted between the node and the potential of the power supply, and the precharging means is an N-channel type M inserted between the node and the ground potential.
When a high-level precharge signal is input to the gate of the N-channel MOS transistor, the node may be precharged to the ground potential via the N-channel MOS transistor.

Further, as described in claim 5, each series circuit is inserted between a node and a ground potential, the latch means inverts and outputs the potential of the node, and the activating means outputs the output of the latch means. Alternatively, the NOR logic of the signal obtained by inverting the chip internal activation signal may be obtained, and the result may be output as a redundant activation signal.

Alternatively, as described in claim 6, each series circuit is inserted between the node and the potential of the power supply, and the latch means comprises:
The activation means may invert and output the potential of the node, obtain the AND logic of the output of the latch means and the chip internal activation signal, and output the result as a redundant activation signal.

Next, according to the semiconductor memory device of the present invention, in response to the input of the external control signal and the external address, the timing for activating the precharge means is determined, and the external address is decoded into an address. By delaying this address and applying it to the switching elements of each series circuit, a procedure of precharging the node and then selectively turning on each switching element is realized.

The dynamic run according to claim 8
According to the semiconductor memory device of the dumb access type, the row address
Activates the precharge means in response to the rest strobe signal.
Operation timing, delay the address and
Node to the switching element on the
Precharge, and then select each switching element
The procedure to turn on is realized.

Alternatively, the dyna according to claim 9
A semiconductor memory device that is a Mick Random Access type, and
The static random access type according to claim 10
According to a semiconductor memory device, a change in an external address signal
In response to the
The address is delayed and the switching element of each series circuit is
Precharge the node by giving it to the child
To turn on each switching element selectively after
The procedure has been realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a redundancy judgment circuit according to the present invention;

FIG. 2 is a timing chart showing signals in the redundancy judgment circuit of FIG. 1;

FIG. 3 is a block diagram showing a second embodiment of the redundancy judgment circuit of the present invention;

FIG. 4 is a timing chart showing the timing of each signal in the redundancy judgment circuit of FIG. 3;

FIG. 5 is a block diagram showing one embodiment of a semiconductor memory device of the present invention;

6 is a timing chart showing the timing of each signal in the semiconductor memory device of FIG.

FIG. 7 is a timing chart showing another timing of each signal in the semiconductor memory device of FIG. 5;

FIG. 8 is a timing chart showing another timing of each signal in the semiconductor memory device of FIG. 5;

FIG. 9 is a block diagram showing a conventional redundancy judgment circuit.

10 is a timing chart showing the timing of each signal in the redundancy judgment circuit of FIG.

FIG. 11 is a block diagram showing another conventional redundancy judgment circuit.

FIG. 12 is a timing chart showing the timing of each signal in the redundancy judgment circuit of FIG. 11;

FIG. 13 is a block diagram showing another conventional redundancy judgment circuit.

14 is a timing chart showing the timing of each signal in the redundancy judgment circuit of FIG.

[Description of Signs] 11 NOR circuit 12 Inverter 21 Latch circuit 22 AND circuit 31 Precharge signal generation circuit 32 Address decode circuit 33 Delay circuit 101 Fuse circuit 103 Latch circuit 104 Inverter A1, A2 Address A1, A2, / A1, A2, A1 / A2, / A1 / A2 Address decode signal ACT Chip internal activation signal Ad External address signal ATD Address transition detection signal / CAS Column address strobe signal / CS Chip select signal f1 to f4 Fuse INV Inverter N1 to N4 N channel Type MOS transistor n1 node P1 to P4 P-channel type MOS transistor P, / P precharge signal SP redundancy activation signal / RAS row address strobe signal

Claims (7)

[Claims] A plurality of series circuits each having a switching element and a fuse connected in series are inserted between a node and a reference potential to selectively cut any one of the fuses.
In a redundancy determining circuit for selectively turning on each switching element according to an address and outputting a redundancy activation signal corresponding to the potential of the node when the switching element paired with the blown fuse is turned on, In a state where each switching element is turned off, a precharge means for precharging the potential of the node, a latch means for latching the potential of the node, and an output of the latch means are activated to activate a redundant active circuit corresponding to the output. Activating means for outputting an activation signal, wherein the potential of the node is precharged by the precharge means, and thereafter, each switching element is selectively turned on in accordance with the address, and then the potential of the node is latched by the latch means. And a redundancy determining circuit for activating the output of the latch means by the activating means. 2. Each of the series circuits is inserted between a node and a ground potential, and the precharge means is a P-channel MOS transistor inserted between a power supply and the node, and the gate of the P-channel MOS transistor is 2. The redundancy judgment circuit according to claim 1, wherein when a low-level precharge signal is input to the node, the node is precharged to a power supply potential via the P-channel MOS transistor. 3. Each of the series circuits is inserted between a node and a ground potential, and the precharge means is an N-channel MOS transistor inserted between a power supply and the node, and a gate of the N-channel MOS transistor. 2. The redundancy judging circuit according to claim 1, wherein when a high-level precharge signal is input to the node, the node is precharged to a power supply potential via the N-channel MOS transistor. 4. Each of the series circuits is inserted between a node and a potential of a power supply, and the precharge means is an N-channel MOS transistor inserted between the node and a ground potential. 2. The redundancy judging circuit according to claim 1, wherein when a high-level precharge signal is inputted to the gate of said node, the node is precharged to the ground potential via said N-channel MOS transistor. 5. Each of the series circuits is inserted between a node and a ground potential, the latch means inverts and outputs the potential of the node, and the activating means outputs the output of the latch means and an internal chip activation signal. 2. The redundancy judging circuit according to claim 1, wherein the NOR logic of the inverted one is obtained, and the result is output as a redundancy activation signal. 6. Each of the series circuits is inserted between a node and a potential of a power supply. The latch means inverts and outputs the potential of the node. The activating means activates the output of the latch means and an internal activation signal of the chip. 2. The redundancy judgment circuit according to claim 1, wherein an AND logic is obtained and the result is output as a redundancy activation signal. 7. A semiconductor memory device comprising the redundancy judgment circuit according to claim 1, wherein a precharge signal applied to a precharge means is activated in response to an input of an external control signal and an external address. And a precharge generating means for activating the precharge means, and an address decode delay means for decoding an external address into an address, delaying the address and applying the delayed address to a switching element of each series circuit, and which is once activated. A semiconductor memory device that supplies an address to a switching element of each series circuit after a precharge signal becomes inactive.