JP2005086681A - Schmitt trigger circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a Schmitt trigger circuit arbitrarily adjusting a threshold value. <P>SOLUTION: In the Schmitt trigger circuit, threshold voltage of inverters 2, 3 is adjusted by potential control circuits 7, 8. The threshold potential of the inverter 2 becomes threshold value VIH and the threshold potential of the inverter 3 becomes the threshold value VIL. Level shifters 9, 10 amplify potential levels of output signals of the inverters 2, 3 to power source potential VDD. Consequently, a user easily adjusts the threshold values VIH, VIL to arbitrary values between the power source potential VDD and reference potential VSS, and versatility of the Schmitt trigger circuit is expanded. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a Schmitt trigger circuit, and more particularly to a Schmitt trigger circuit having different threshold potentials when the level of an input signal rises and falls.

  An input circuit of a semiconductor device receives an input signal from the outside and transmits it to an internal circuit. Usually, the threshold potential of a general-purpose input circuit is designed to be 0.5 VDD with respect to the power supply potential VDD. On the other hand, the threshold potential of the input circuit for special applications is designed to be a value corresponding to the level of the input signal.

  Therefore, it is desired that even an input circuit for a special purpose can be designed without being conscious of the level of the input signal and the user can arbitrarily set the threshold potential.

  Some conventional semiconductor devices include a level shifter that connects the source and bulk of a P-channel MOS transistor constituting a CMOS inverter to a variable power supply and converts the output signal of the inverter to a positive power supply voltage level. In this case, since the threshold potential of the inverter is variable, the operation speed of the inverter can be increased (for example, see Patent Document 1).

  There is also a semiconductor device that changes the threshold potential of a CMOS output circuit by controlling the power supply voltage of a CMOS inverter using a DA converter (see, for example, Patent Document 2).

In an input circuit of a semiconductor device, by making a threshold potential variable using a level shifter or a DA converter as described above, an input circuit designed to have a threshold potential of 0.5 VDD is used for a special purpose. Can also be used.
JP 57-17223 A JP 2000-341104 A

  In order to obtain an operation margin for an input signal having waveform distortion, a Schmitt trigger type input circuit has been proposed. In the Schmitt trigger circuit, the threshold value VIH (potential recognized as being at “H” level) when the input signal rises from “L” level to “H” level, and the input signal from “H” level to “H” level. The threshold value VIL (potential recognized as being at the “L” level) when falling to the “L” level is different. The difference between the threshold values VIH and VIL is the hysteresis voltage.

  The threshold values VIH and VIL are arbitrarily set between the power supply potential VDD and the reference potential VSS. The conventional Schmitt trigger circuit is premised on that the maximum value of the potential level of the input signal applied to the input terminal is equivalent to the power supply potential VDD and the minimum value is equivalent to the reference potential VSS.

  However, in recent years, with the expansion of the range of application products in which semiconductor integrated circuits are used, there are cases where the input signal does not satisfy the above-mentioned preconditions. For this reason, a dedicated terminal is provided in the Schmitt trigger type input circuit for special use, and the threshold values VIH and VIL of the dedicated terminal are designed in advance so as to satisfy the conditions of the input signal. However, the Schmitt trigger type input circuit designed for special applications in this way has no generality.

  In the conventional Schmitt trigger circuit, the threshold values VIH and VIL vary due to variations in the manufacturing process. For this reason, the width of the hysteresis voltage varies, which causes a problem in product management.

  Therefore, a main object of the present invention is to provide a Schmitt trigger circuit capable of arbitrarily adjusting a threshold value.

  The Schmitt trigger circuit according to the present invention includes a first potential control circuit that applies a first potential between the power supply potential and the reference potential to the first node, and a second potential between the first potential and the reference potential. A second potential control circuit for applying a first potential to the second node, and a first conductive type connected in series between the first node and a reference potential line, both of which input electrodes receive an input signal. A first inverter including a first transistor and a second transistor of the second conductivity type is connected in series between a second node and a reference potential line, and both input electrodes receive an input signal. A second inverter including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type; and when the level of the input signal rises, the level of the input signal is the threshold value of the first inverter Potential In response to the level of the output signal of the first inverter being switched from the first potential to the reference potential, the level of the output signal is switched from the first logic potential to the second logic potential. At the time of falling, in response to the level of the input signal being lower than the threshold potential of the second inverter and the level of the output signal of the second inverter being switched from the reference potential to the second potential, And a logic circuit that switches the level of the output signal from the second logic potential to the first logic potential.

In the Schmitt trigger circuit according to the present invention, a first potential control circuit that applies a first potential between the power supply potential and the reference potential to the first node, and a second potential between the first potential and the reference potential. A second potential control circuit for applying a first potential to the second node, and a first conductive type connected in series between the first node and a reference potential line, both of which input electrodes receive an input signal. A first inverter including a first transistor and a second transistor of the second conductivity type is connected in series between a second node and a reference potential line, and both input electrodes receive an input signal. A second inverter including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type; and when the level of the input signal rises, the level of the input signal is the threshold value of the first inverter potential In response to the switching of the level of the output signal of the first inverter from the first potential to the reference potential, the level of the output signal is switched from the first logic potential to the second logic potential. When the level is lowered, the level of the input signal is lower than the threshold potential of the second inverter and the level of the output signal of the second inverter is switched from the reference potential to the second potential. And a logic circuit for switching the level of the output signal from the second logic potential to the first logic potential. Therefore, the threshold potentials of the first and second inverters can be adjusted to any value between the power supply potential VDD and the reference potential VSS by the first and second potential control circuits. In other words, a Schmitt trigger circuit that allows the user to arbitrarily adjust the threshold value can be realized.

  FIG. 1 is a block diagram showing a schematic configuration of an input circuit of a semiconductor integrated circuit device according to an embodiment of the present invention. 1, the input circuit of this semiconductor integrated circuit device is a Schmitt trigger circuit including an input terminal 1, inverters 2 to 4, NOR circuits 5 and 6, potential control circuits 7 and 8, level shifters 9 and 10, and an output terminal 11. is there.

  An input signal from the outside is given to the inverters 2 and 3 through the input terminal 1. The inverter 2 has its power supply terminal connected to the power supply potential VDD line via the potential control circuit 7 and its ground terminal connected to the reference potential VSS line. The inverter 3 has its power supply terminal connected to the power supply potential VDD line via the potential control circuits 7 and 8, and its ground terminal connected to the reference potential VSS line. With such a configuration, the threshold potentials of the inverters 2 and 3 are adjusted by the potential control circuits 7 and 8. The threshold potential of the inverter 2 becomes the threshold value VIH, and the threshold potential of the inverter 3 becomes the threshold value VIL. The output signals of the inverters 2 and 3 are given to the level shifters 9 and 10, respectively.

  The level shifter 9 amplifies the potential level of the output signal of the inverter 2 to the power supply potential VDD and gives it to the inverter 4. The level shifter 10 amplifies the potential level of the output signal of the inverter 3 to the power supply potential VDD and gives it to the NOR circuit 5.

  NOR circuit 6 receives the output signals of inverter 4 and NOR circuit 5. The output signal of the NOR circuit 6 is fed to the output terminal 11 and fed back to the NOR circuit 5.

  FIG. 2 is a circuit diagram showing in detail the configuration of the Schmitt trigger circuit shown in FIG. In FIG. 2, inverter 2 includes a P channel MOS transistor 21 and an N channel MOS transistor 22. The gates of P channel MOS transistor 21 and N channel MOS transistor 22 are both connected to input terminal 1. The source and bulk of P channel MOS transistor 21 are both connected to node N1. The source and bulk of N channel MOS transistor 22 are both connected to a line of reference potential VSS. The drains of P channel MOS transistor 21 and N channel MOS transistor 22 are both connected to output node N21. Here, by configuring the channel length and channel width of P channel MOS transistor 21 and N channel MOS transistor 22 to have predetermined values, threshold value VIH (threshold potential of inverter 2) is set at node N1. It is designed to be an intermediate value between the potential and the reference potential VSS.

  Inverter 3 includes a P channel MOS transistor 23 and an N channel MOS transistor 24. The gates of P channel MOS transistor 23 and N channel MOS transistor 24 are both connected to input terminal 1. The source and bulk of P channel MOS transistor 23 are both connected to node N2. The source and bulk of N channel MOS transistor 24 are both connected to a line of reference potential VSS. The drains of P channel MOS transistor 23 and N channel MOS transistor 24 are both connected to output node N41. Here, by configuring so that the channel length and channel width of P channel MOS transistor 23 and N channel MOS transistor 24 have predetermined values, threshold value VIL (threshold potential of inverter 3) is set at node N2. It is designed to be an intermediate value between the potential and the reference potential VSS.

  The potential control circuit 7 includes a register 31, a decoder 32, selection circuits 33 and 34, and voltage dividing circuits 35 and 36. The selection circuits 33 and 34 include a plurality of switch circuits SW1 connected in parallel. The voltage dividing circuits 35 and 36 include a plurality of resistance elements R1 connected in series between the power supply potential VDD line and the reference potential VSS line.

  The register 31 is set with data for controlling the operation of the selection circuits 33 and 34. The register 31 supplies a potential setting signal to the decoder 32. The decoder 32 decodes the potential setting signal from the register 31 and outputs it to the selection circuits 33 and 34. In response to the potential setting signal from the decoder 32, the selection circuits 33 and 34 select one of the plurality of switch circuits SW1 to be conductive and make the other switch circuit SW1 nonconductive. Therefore, a potential obtained by dividing the potential difference between the power supply potential VDD and the reference potential VSS by the plurality of resistance elements R1 of the voltage dividing circuits 35 and 36 is applied to the nodes N1 and N11. Therefore, the potentials of the nodes N1 and N11 are set to arbitrary potentials between the power supply potential VDD and the reference potential VSS.

  The selection circuits 33 and 34 and the voltage dividing circuits 35 and 36 have the same configuration. That is, the potentials of the nodes N1 and N11 are the same. Here, the reason why the two selection circuits 33 and 34 and the voltage dividing circuits 35 and 36 having the same configuration are provided is that the potential of the node N1 may slightly vary from a desired value due to the consumption current of the inverter 2. Because there is. Therefore, if the potential control circuit 8 is connected to the node N1 instead of the node N11 without providing the selection circuit 34 and the voltage dividing circuit 36, the potential of the node N2 also varies depending on the potential variation of the node N1. There is a possibility that the threshold value VIL (the threshold potential of the inverter 3) may deviate from a desired value. However, by providing two selection circuits 33 and 34 and two voltage dividing circuits 35 and 36, even if the potential of node N1 fluctuates, node N2 is not affected.

  The potential control circuit 8 includes a register 41, a decoder 42, a selection circuit 43, and a voltage dividing circuit 44. The selection circuit 43 includes a plurality of switch circuits SW2 connected in parallel. The voltage dividing circuit 44 includes a plurality of resistance elements R2 connected in series between the node N11 and the line of the reference potential VSS.

  Data for controlling the operation of the selection circuit 43 is set in the register 41. The register 41 supplies a potential setting signal to the decoder 42. The decoder 42 decodes the potential setting signal from the register 41 and outputs it to the selection circuit 43. In response to the potential setting signal from the decoder 42, the selection circuit 43 selects and conducts one of the plurality of switch circuits SW2, and makes the other switch circuit SW2 non-conductive. Therefore, a potential obtained by dividing the potential difference between the potential of the node N11 and the reference potential VSS by the plurality of resistance elements R2 of the voltage dividing circuit 44 is applied to the node N2. Therefore, the potential of the node N2 is set to an arbitrary potential between the potential of the node N11 and the reference potential VSS.

  With such a configuration, the threshold value VIH (threshold potential of the inverter 2) is intermediate between the potential of the node N1, which is set to any potential between the power supply potential VDD and the reference potential VSS, and the reference potential VSS. Set to a value. The threshold value VIL (threshold potential of the inverter 3) is set to an intermediate value between the potential of the node N2 that is set to any potential between the potential of the node N11 and the reference potential VSS and the reference potential VSS. Is done.

  Here, the potential of the node N2 is set lower than the potential of the node N1. That is, the threshold value VIL determined by the inverter 3 is set to a value lower than the threshold value VIH determined by the inverter 2.

  Level shifter 9 includes P channel MOS transistors 51-56 and N channel MOS transistors 57-60. The gates of P channel MOS transistor 51 and N channel MOS transistor 57 are both connected to output node N 21 of inverter 2. The source and bulk of P channel MOS transistor 51 are both connected to node N1. The source and bulk of N channel MOS transistor 57 are both connected to a line of reference potential VSS. The drains of P channel MOS transistor 51 and N channel MOS transistor 57 are both connected to node N31.

  The gates of P channel MOS transistor 52 and N channel MOS transistor 58 are both connected to node N31. The gates of P channel MOS transistor 54 and N channel MOS transistor 59 are both connected to output node N21. The sources and bulks of P-channel MOS transistors 52 and 54 are both connected to the power supply potential VDD line. The sources and bulks of N channel MOS transistors 58 and 59 are both connected to a line of reference potential VSS. P channel MOS transistor 53 has its source connected to the drain of P channel MOS transistor 52, its bulk connected to the line of power supply potential VDD, its gate connected to node N32, and its drain connected to N channel MOS transistor 58. And the gate of P channel MOS transistor 55. P channel MOS transistor 55 has its source connected to the drain of P channel MOS transistor 54, its bulk connected to the line of power supply potential VDD, its drain connected to the drain of N channel MOS transistor 59, and node N32. Connected to.

  The gates of P channel MOS transistor 56 and N channel MOS transistor 60 are both connected to node N32. The source and bulk of P channel MOS transistor 56 are both connected to the line of power supply potential VDD. The source and bulk of N channel MOS transistor 60 are both connected to a line of reference potential VSS. The drains of P channel MOS transistor 56 and N channel MOS transistor 60 are both connected to output node N33.

  Next, the operation of the level shifter 9 will be described. First, when output node N21 is at "H" level (potential of node N1), P channel MOS transistor 51 is non-conductive, N channel MOS transistor 57 is conductive, and node N31 is at "L" level. In response, P channel MOS transistor 52 is turned on and N channel MOS transistor 58 is turned off. Further, according to the “H” level potential of output node N21, P channel MOS transistor 54 is rendered non-conductive, N channel MOS transistor 59 is rendered conductive, and node N32 is set to “L” level. In response, P channel MOS transistor 53 is turned on and P channel MOS transistor 55 is turned off. In response to node N32 attaining "L" level, P channel MOS transistor 56 is rendered conductive and N channel MOS transistor 60 is rendered non-conductive, so that output node N33 is at "H" level (power supply potential VDD). Become.

  On the other hand, when output node N21 is at "L" level, P channel MOS transistor 51 is rendered conductive, N channel MOS transistor 57 is rendered non-conductive, and node N31 is rendered "H" level. In response, P channel MOS transistor 52 is turned off, N channel MOS transistor 58 is turned on, and P channel MOS transistor 55 is turned on. Further, in response to the “L” level potential of output node N21, P channel MOS transistor 54 is rendered conductive, N channel MOS transistor 59 is rendered non-conductive, and node N32 is rendered “H” level. In response, P channel MOS transistor 53 is rendered non-conductive. In response to node N32 attaining "H" level, P channel MOS transistor 56 is rendered non-conductive and N channel MOS transistor 60 is rendered conductive, so that output node N33 is at "L" level (reference potential VSS). Become.

  As described above, the level shifter 9 amplifies a signal having a potential difference between the potential of the node N1 and the reference potential VSS into a signal having a potential difference between the power supply potential VDD and the reference potential VSS.

  Level shifter 10 includes P channel MOS transistors 61-66 and N channel MOS transistors 67-70. The gates of P channel MOS transistor 61 and N channel MOS transistor 67 are both connected to output node N 41 of inverter 3. The source and bulk of P channel MOS transistor 61 are both connected to node N2. The source and bulk of N channel MOS transistor 67 are both connected to a line of reference potential VSS. The drains of P channel MOS transistor 61 and N channel MOS transistor 67 are both connected to node N51.

  The gates of P channel MOS transistor 62 and N channel MOS transistor 68 are both connected to node N51. The gates of P channel MOS transistor 64 and N channel MOS transistor 69 are both connected to output node N41. The sources and bulks of P channel MOS transistors 62 and 64 are both connected to a line of power supply potential VDD. The sources and bulks of N channel MOS transistors 68 and 69 are both connected to a line of reference potential VSS. P channel MOS transistor 63 has its source connected to the drain of P channel MOS transistor 62, its bulk connected to the line of power supply potential VDD, its gate connected to node N52, and its drain connected to N channel MOS transistor 68. And is connected to the gate of a P-channel MOS transistor 65. P channel MOS transistor 65 has its source connected to the drain of P channel MOS transistor 64, its bulk connected to the line of power supply potential VDD, its drain connected to the drain of N channel MOS transistor 69, and node N52. Connected to.

  The gates of P channel MOS transistor 66 and N channel MOS transistor 70 are both connected to node N52. The source and bulk of P channel MOS transistor 66 are both connected to the line of power supply potential VDD. The source and bulk of N channel MOS transistor 70 are both connected to a line of reference potential VSS. The drains of P channel MOS transistor 66 and N channel MOS transistor 70 are both connected to output node N53.

  Next, the operation of the level shifter 10 will be described. First, when output node N41 is at "H" level (potential of node N2), P-channel MOS transistor 61 is non-conductive, N-channel MOS transistor 67 is conductive, and node N51 is at "L" level. In response, P channel MOS transistor 62 becomes conductive and N channel MOS transistor 68 becomes nonconductive. Further, according to the “H” level potential of output node N41, P channel MOS transistor 64 becomes non-conductive, N channel MOS transistor 69 becomes conductive, and node N52 becomes “L” level. In response, P channel MOS transistor 63 is rendered conductive and P channel MOS transistor 65 is rendered non-conductive. In response to node N52 attaining "L" level, P channel MOS transistor 66 is rendered conductive and N channel MOS transistor 70 is rendered non-conductive, so that output node N53 is rendered at "H" level (power supply potential VDD). Become.

  On the other hand, when output node N41 is at "L" level, P channel MOS transistor 61 is rendered conductive, N channel MOS transistor 67 is rendered non-conductive, and node N51 is rendered "H" level. In response, P channel MOS transistor 62 is turned off, N channel MOS transistor 68 is turned on, and P channel MOS transistor 65 is turned on. Further, according to the “L” level potential of output node N41, P channel MOS transistor 64 becomes conductive, N channel MOS transistor 69 becomes nonconductive, and node N52 becomes “H” level. In response, P channel MOS transistor 63 is rendered non-conductive. In response to node N52 attaining "H" level, P channel MOS transistor 66 is rendered non-conductive and N channel MOS transistor 70 is rendered conductive, so that output node N53 is at "L" level (reference potential VSS). Become.

  As described above, the level shifter 10 amplifies a signal having a potential difference between the potential of the node N2 and the reference potential VSS to a signal having a potential difference between the power supply potential VDD and the reference potential VSS.

  FIG. 3 is a waveform diagram for explaining the operation of the Schmitt trigger circuit. In FIG. 3, a signal SIN indicates a signal input to the input terminal 1, and a signal SOUT indicates a signal output from the output terminal 11.

  The potential of the input signal SIN rises proportionally from the reference potential VSS to the power supply potential VDD from time t0 to time t3, and falls proportionally from the power supply potential VDD to the reference potential VSS from time t3 to time t6. .

  At time t0, the output signals of the inverters 2 and 3 both become “H” level with respect to the input signal SIN of “L” level (reference potential VSS). The level shifter 9 amplifies the potential level of the output signal of the inverter 2 to the power supply potential VDD and gives it to the inverter 4. The level shifter 10 amplifies the potential level of the output signal of the inverter 3 to the power supply potential VDD and gives it to the NOR circuit 5. In response, the output signals of inverter 4 and NOR circuit 5 attain “L” level, and output signal SOUT of NOR circuit 6 attains “H” level (power supply potential VDD).

  At time t1, in response to the potential level of the input signal SIN becoming higher than the threshold value VIL, the output signal of the inverter 3 becomes “L” level. At this time, one input signal of the NOR circuit 5 (output signal of the level shifter 10) is at “L” level, but the other input signal (feedback signal from the NOR circuit 6) remains at “H” level. The output signal of the circuit 5 maintains the “L” level. Therefore, the output signal SOUT of the NOR circuit 6 holds the “H” level (power supply potential VDD).

  At time t2, in response to the potential level of the input signal SIN becoming higher than the threshold value VIH, the output signal of the inverter 2 becomes “L” level. In response, the output signal of inverter 4 becomes “H” level, and output signal SOUT of NOR circuit 6 falls to “L” level (reference potential VSS).

  At time t4, in response to the potential level of the input signal SIN becoming lower than the threshold value VIH, the output signal of the inverter 2 becomes “H” level. In response to this, the output signal of the inverter 4 becomes “L” level. At this time, one input signal of the NOR circuit 6 (output signal of the inverter 4) is at “L” level, but the other input signal (output signal of the NOR circuit 5) remains at “H” level. The output signal SOUT 6 holds the “L” level (reference potential VSS).

  At time t5, in response to the potential level of the input signal SIN becoming lower than the threshold value VIL, the output signal of the inverter 3 becomes “H” level. In response to this, the output signal of the NOR circuit 5 becomes “L” level. Therefore, output signal SOUT of NOR circuit 6 is raised to the “H” level (power supply potential VDD).

  In the conventional Schmitt trigger type input circuit, the potential control circuits 7 and 8 and the level shifters 9 and 10 are not provided. In the manufacturing process, the channel lengths and channel widths of the P-channel MOS transistors 21 and 23 and the N-channel MOS transistors 22 and 24 constituting the inverters 2 and 3 are designed to have predetermined values. For this reason, the threshold values VIH and VIL cannot be adjusted according to the level of the input signal after manufacturing.

  For example, when the power supply potential VDD = 5 V, the reference potential VSS = 0 V, the threshold value VIH = 0.6 (VDD−VSS) = 3 V, and the threshold value VIL = 0.4 (VDD−VSS) = 2 V think about. This input circuit assumes that the maximum value of the potential level of the input signal is 5V and the minimum value is 0V. However, there is a case where the input circuit is desired to be applied to an input signal having an unexpected potential level, such as an input signal having a maximum potential level of 2V and a minimum value of 0V. In this case, since the potential level of the input signal does not exceed the threshold value VIH, there is a problem that the “H” level of the input signal is not recognized at all.

  However, in this embodiment, the internal power generation circuits 7 and 8 are provided, and the user arbitrarily sets the data in the registers 31 and 41, whereby the threshold values VIH and VIL are set between the power supply potential VDD and the reference potential VSS. Can be easily adjusted to any value. Therefore, a versatile Schmitt trigger type input circuit can be realized. For this reason, it is not necessary to specially design an input circuit for a special purpose as in the prior art, and the design of the semiconductor integrated circuit device is greatly simplified.

  Furthermore, even if the threshold values VIH and VIL vary due to variations in the manufacturing process, the user can easily correct the threshold values VIH and VIL to appropriate values. This simplifies product management and improves yield.

  The relationship between the setting data of the registers 31 and 41 and the output potential of the potential control circuits 7 and 8, and the threshold values VIH and VIL are intermediate values between the output potential of the potential control circuits 7 and 8 and the reference potential VSS, respectively. Make it clear to the user. Thus, the user can derive the setting data of the registers 31 and 41 for realizing the desired threshold values VIH and VIL by simple calculation. For this reason, it is not necessary to replace the mask in the semiconductor manufacturing process as in the prior art, and the user can easily change the threshold values VIH and VIL as appropriate according to the level of the input signal.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram showing a schematic configuration of an input circuit of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing in detail a configuration of a Schmitt trigger circuit shown in FIG. 1. FIG. 3 is a waveform diagram for explaining the operation of the Schmitt trigger circuit shown in FIG. 2.

Explanation of symbols

  1 input terminal, 2-4 inverter, 5, 6 NOR circuit, 7, 8 potential control circuit, 9, 10 level shifter, 11 output terminal, 21, 23, 51-56, 61-66 P channel MOS transistor, 22, 24 , 57-60, 67-70 N channel MOS transistor, 31, 41 register, 32, 42 decoder, 33, 34, 43 selection circuit, 35, 36, 44 voltage dividing circuit.

Claims (2)

A Schmitt trigger circuit,
A first potential control circuit that applies a first potential between a power supply potential and a reference potential to the first node;
A second potential control circuit for applying a second potential between the first potential and the reference potential to a second node;
A first transistor of a first conductivity type and a second transistor of a second conductivity type, which are connected in series between the first node and the line of the reference potential and both of their input electrodes receive an input signal. A first inverter comprising:
A third transistor of the first conductivity type and a fourth transistor of the second conductivity type are connected in series between the second node and the line of the reference potential, and both of their input electrodes receive the input signal. A second inverter including a transistor; and when the level of the input signal rises, the level of the input signal exceeds the threshold potential of the first inverter and the level of the output signal of the first inverter In response to switching from the potential of 1 to the reference potential, the level of the output signal is switched from the first logic potential to the second logic potential, and when the level of the input signal decreases, the level of the input signal is In response to the level of the output signal of the second inverter being switched from the reference potential to the second potential, being lower than the threshold potential of the second inverter. And a Schmitt trigger circuit comprising a logic circuit for switching the level of the output signal from the second logic potential to the first logic potential. The first potential control circuit includes:
A first register for storing a first potential setting signal;
A first voltage dividing circuit for generating a plurality of potentials between the power supply potential and the reference potential; and a plurality of potentials generated by the first voltage dividing circuit based on the first potential setting signal Including a first selection circuit that selects the potential of any one of the first potential and sets the first potential as the first potential,
The second potential control circuit includes:
A second register for storing a second potential setting signal;
A second voltage dividing circuit for generating a plurality of potentials between the first potential and the reference potential; and a plurality of voltages generated by the second voltage dividing circuit based on the second potential setting signal. 2. The Schmitt trigger circuit according to claim 1, further comprising: a second selection circuit that selects any one of the potentials to be the second potential.

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