JP2008258966A - Vth shift circuit and d/a converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a Vth shift circuit capable of obtaining output voltage obtained by shifting input voltage by predetermined voltage without receiving process irregularity. <P>SOLUTION: The first and second transistors T1 and T2 are connected in series between a constant current source 11 connected to a high potential power supply AVD and a low potential power supply AVS. The third to fifth transistors T3 to T5 are also connected in series between the constant current source 11 and the low potential power supply AVS. Input voltage Vi is supplied to the gate of the first transistor T1, and the gate and the drain of the third transistor T3 are connected to each other. The gate and the drain of the fourth transistor T4 are connected to each other, and the drain of the fifth transistor T5 is connected. In the transistor T2 and the transistor T5, the gates are mutually connected and connected to the drain of the transistor T2 to form a current mirror circuit. A drain voltage of the connected transistors T4 and T5 is output as an output voltage Vo. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a Vth shift circuit and a D / A converter.

FIG. 5 is a circuit diagram of a conventional current output type digital-analog converter (current output type D / A converter).
The digital signal Din and the clock signal CLK are input to the decoder circuit 51 of the current output type D / A converter 50. The decoder circuit 51 decodes the digital signal Din and generates a plurality of control signals S1 corresponding to the bit number n of the digital signal Din. The plurality of control signals S1 are respectively input to the corresponding current output units 52.

  The control signal S1 is input to the inverter circuit 53 and the buffer circuit 54 of the current output unit 52, and a pair of P-channel MOS transistors TA and TB constituting a differential pair are generated by the output signals of the inverter circuit 53 and the buffer circuit 54. Complementary on / off control. The plurality of current output units 52 are configured in the same manner, and the transistor TA of each current output unit 52 is connected to the resistor R1, and the transistor TB is connected to the resistor R2.

  In the pair of transistors TA and TB, for example, the transistor TA is turned on and the transistor TB is turned off by an H level control signal S1. That is, the transistor TA of the current output unit 52 to which the H level control signal S1 is input is turned on, and a current corresponding to the number of the turned on transistors TA flows to the resistor R1. The level of the control signal S1 is determined by the digital signal Din. Therefore, a current corresponding to the digital signal Din flows through the resistor R1, that is, the D / A converter outputs a current corresponding to the digital signal Din.

  The low potential side power supply terminals of the inverter circuit 53 and the buffer circuit 54 are connected to the low potential power supply AVS via the N-channel MOS transistor TC. The gate and drain of the transistor TC are connected to each other. Thereby, the drain-source voltage of the transistor TC becomes the gate-source voltage Vgs of the transistor TC. This is because the transistors TA and TB constituting the differential pair are operated in the saturation region.

  By operating transistors TA and TB in the saturation region, the output impedance of the D / A converter does not change even if the output voltage changes. A current from the current source 55 to which both transistors TA and TB are connected flows to the resistor R1 or R2. Thereby, an output current (terminal voltages of the resistors R1 and R2) that changes linearly with respect to the change of the digital signal Din can be obtained.

  Incidentally, the external conditions of the D / A converter (the voltage of the high potential power supply AVD or the values of the resistors R1 and R2) are arbitrarily set by the user. The output transistor of the D / A converter must operate in the saturation region even when the terminal voltages of the resistors R1 and R2 reach the maximum value with respect to an external condition set arbitrarily. However, the conventional D / A converter 50 generates the power supply terminal voltages of the inverter circuit 53 and the buffer circuit 54 by the gate-source voltage Vgs of the transistor TC. Since the gate-source voltage Vgs of the transistor TC is affected by process variations, it cannot be set in accordance with changes in external conditions as described above, and there is a problem that the maximum voltage cannot be obtained. .

  The present invention has been made to solve the above-described problems, and an object of the present invention is to use a Vth shift circuit capable of obtaining an output voltage obtained by shifting an input voltage by a predetermined voltage without being subjected to process variations, and the shift circuit. It is to provide a D / A converter.

  In order to achieve the above object, the invention according to claim 1 is characterized in that first and second transistors connected in series between a constant current source connected to a high potential power source and a low potential power source, and the constant current A third to fifth transistors connected in series between a source and the low-potential power source, an input voltage is supplied to the gate of the first transistor, and the gate of the third transistor is Connected to the drain of the third transistor, the gate of the fourth transistor is connected to the drain of the fourth transistor and the drain of the fifth transistor, and the gates of the second and fifth transistors are And connected to the drain of the second transistor to form a current mirror circuit, and the fifth transistor and the fourth transistor connected to each other. A Vth shift circuit for outputting a rain voltage as an output voltage.

  According to this configuration, the output voltage is set according to the gate-source voltages of the first, third, and fourth transistors with respect to the input voltage. Since the gate-source voltage of each transistor corresponds to the threshold voltage of each transistor, an output voltage shifted from the input voltage by the threshold voltage of the transistor is obtained.

  According to a second aspect of the present invention, there are provided first and second transistors connected in series between a constant current source connected to a high potential power source and a low potential power source, the constant current source, the low potential power source, 3 to 5 connected in series, and an input voltage is supplied to the gate of the first transistor, and the gate of the third transistor is connected to the drain of the third transistor. The drain of the fourth transistor and the drain of the fifth transistor are connected, and the second and fifth transistors have their gates connected to each other and connected to the drain of the fifth transistor, A mirror circuit is configured, and a second constant current source and a sixth transistor are connected in series between the high potential power source and the low potential power source, and a gate of the sixth transistor is connected. Is connected to the drain of the second transistor, outputs an output voltage from a node between the second constant current source and the sixth transistor, and outputs the output voltage to the gate of the fourth transistor. This is a feedback Vth shift circuit. According to this configuration, the sixth transistor functions as a source grounded circuit, and the output impedance is reduced.

  The invention according to claim 3 is a decoder circuit that decodes a digital signal to generate a plurality of control signals, a plurality of current output units to which the control signals are respectively input, and the plurality of current output units, A signal generation circuit for generating a complementary signal by a control signal and a pair of transistors to which the complementary signal is input are respectively provided, and a current flowing from a transistor that is turned on based on the control signal is combined to correspond to the digital signal In the D / A converter that supplies the output current to the load, the voltage generation circuit that generates a voltage corresponding to the terminal voltage of the load, and the output voltage of the voltage generation circuit is used as the input voltage, and the input voltage is shifted The Vth shift circuit according to claim 1 or 2, wherein the signal generation circuit outputs an output voltage of the Vth shift circuit to a low potential. Is the D / A converter to supply a signal to a gate of said pair of transistors as a bell.

  According to this configuration, by supplying a signal to the gates of the pair of transistors based on the output voltage of the Vth shift circuit, the pair of transistors can be operated in the saturation region, and the maximum voltage can be output. become able to.

  According to a fourth aspect of the present invention, in the D / A converter according to the third aspect, the signal generation circuit includes an inverter circuit to which the control signal is input and a buffer circuit to which the control signal is input. The output voltage of the Vth shift circuit is supplied to the low potential side power supply terminals of the inverter circuit and the buffer circuit. According to this configuration, a low level signal corresponding to the output voltage of the Vth shift circuit can be easily supplied to the pair of transistors.

  According to the present invention, it is possible to provide a Vth shift circuit capable of obtaining an output voltage obtained by shifting an input voltage by a predetermined voltage without receiving process variations, and a D / A converter using the Vth shift circuit.

Hereinafter, specific examples of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing an example of a Vth shift circuit.
The Vth shift circuit 10 generates an output voltage Vo obtained by shifting the input voltage Vi to the low potential side by the threshold voltage Vth of the transistor.

  The input voltage Vi is supplied to the gate of the first transistor T1. The transistor T1 is a P-channel MOS transistor, its source is connected to the constant current source 11, and its constant current source is connected to the high potential power source AVD. The drain of the transistor T1 is connected to the second transistor T2. The transistor T2 is an N-channel MOS transistor, the source is connected to the low potential power source AVS, and the drain is connected to the transistor T1.

  A series circuit composed of transistors T3, T4, and T5 is connected in parallel to the series circuit of transistors T1 and T2. Specifically, the output terminal of the constant current source 11 is connected to the third transistor T3. The transistor T3 is a P-channel MOS transistor, the source is connected to the constant current source 11, the gate and the drain are connected to each other, and the drain is connected to the fourth transistor T4. The transistor T4 is a P-channel MOS transistor, the source is connected to the transistor T3, the gate and the drain are connected to each other, and the drain is connected to the fifth transistor T5.

  The transistor T5 is an N-channel MOS transistor, the source is connected to the low potential power source AVS, and the drain is connected to the transistor T4. The gate of the transistor T5 is connected to the gate and drain of the transistor T2. Therefore, the transistors T2 and T5 constitute a current mirror circuit. Then, the drain voltage of the transistor T5 is output as the output voltage Vo. The drain of the transistor T5 is connected to the gate of the transistor T4.

  In the Vth shift circuit 10 configured as described above, since the transistor T2 and the transistor T5 constitute a current mirror circuit, the currents I (T2) and I (T5) flowing through both the transistors T2 and T5 are equal (= I). Become. The transistors T1, T3, and T4 are formed such that the element parameters β (T3) and β (T4) of the transistors T3 and T4 are four times as large as the element parameter β (T1) of the transistor T1. The element parameter β is a value proportional to the ratio between the channel width W and the channel length L. Further, the transistors T1, T3, and T4 are formed so that their threshold voltages Vth (T1), Vth (T3), and Vth (T4) are equal. That is, the following is set as a condition.

I (T2) = I (T5) = I
β (T1) = β, β (T3) = β (T4) = 4β
Vth (T1) = Vth (T3) = Vth (T4) = Vth
Thus, the current I flowing through the transistor T1 and the transistors T3 and T4 is
I = β / 2 × (Vgs (T1) −Vth) ^ 2
I = (4β) / 2 × (Vgs (T3) −Vth) ^ 2
I = (4β) / 2 × (Vgs (T4) −Vth) ^ 2
It becomes. “^ 2” represents the square.

The gate-source voltages Vgs (T1), Vgs (T3), Vgs (T4) of the transistors T1, T3, T4 are
Vgs (T1) = Vth + √ (2I / β)
Vgs (T3) = Vth + (1/2) × √ (2I / β)
Vgs (T4) = Vth + (1/2) × √ (2I / β) = Vgs (T3)
It becomes. “√” represents a square root.

If the overdrive voltage √ (2I / β) is α,
Vgs (T1) = Vth + α
Vgs (T3) = Vgs (T4) = Vth + α / 2
As described above, the output voltage Vo is lower than the input voltage Vi by the gate-source voltage Vgs (T1) of the transistor T1, and is lower than the gate-source voltages Vgs (T3) and Vgs (T3) of the transistors T3 and T4. It becomes. That means
Vi + Vgs (T1) − (Vgs (T3) + Vgs (T4)) = Vo
So,
Vo = Vi + {Vth + α} −2 × {Vth + α / 2}
= Vi-Vth
It becomes.

  In this way, the Vth shift circuit 10 generates a voltage Vo that has dropped from the input voltage Vi by the threshold voltage Vth of the transistor T1 (T3, T4). Since each of the above equations does not include the high potential power supply AVD, an output voltage Vo that is correctly shifted from the input voltage Vi by the threshold voltage Vth is obtained regardless of the voltage of the high potential power supply AVD.

FIG. 2 is a circuit diagram showing another example of the Vth shift circuit.
In the Vth shift circuit 20, a constant current source 21, a capacitor C1, and a transistor T6 are added to the Vth shift circuit 10 shown in FIG.

  The constant current source 21 is connected to the high potential power source AVD, and the output terminal of the constant current source 21 is connected to the sixth transistor T6. The transistor T6 is an N-channel MOS transistor, the source is connected to the low potential power source AVS, the drain is connected to the constant current source 21, and the gate is connected to the drain of the transistor T2. In FIG. 2, the gate and drain of the transistor T5 constituting the current mirror circuit are connected to each other. A capacitor C1 is connected between the gate and drain of the transistor T6.

  This Vth shift circuit 20 also operates in the same manner as the Vth shift circuit 10 described above, and an output voltage Vo obtained by shifting the threshold voltage Vth of the transistors T1, T3, T4 from the input voltage Vi can be obtained. Further, the Vth shift circuit 20 has a smaller output impedance than the Vth shift circuit 10 in FIG.

FIG. 3 is a circuit diagram of a digital-analog converter (D / A converter) to which the Vth shift circuit 10 (or Vth shift circuit 20) is applied.
In the D / A converter 30, the digital signal Din and the clock signal CLK are input to the decoder circuit 31. The decoder circuit 31 has a decoding function and a latch function, decodes the digital signal Din to generate a plurality of control signals S1 corresponding to the number of bits n of the digital signal Din, and responds to the clock signal CLK. To latch the signal S1. The decoder circuit 31 outputs a plurality of control signals S1 to the corresponding current output units 32, respectively.

  Since the plurality of current output units 32 have the same configuration, the configuration of one current output unit 32 is shown. The control signal S1 is input to the inverter circuit 33 and the buffer circuit 34 of the current output unit 32. The high potential side power supply terminal of the inverter circuit 33 as a signal generation circuit is connected to the high potential power supply AVD, and the low potential side power supply terminal is connected to the Vth shift circuit 10. Similarly, although not shown in the figure, the high potential side power supply terminal of the buffer circuit 34 as a signal generation circuit is connected to the high potential power supply AVD, and the low potential side power supply terminal is connected to the Vth shift circuit 10. The inverter circuit 33 outputs a signal S2x obtained by logically inverting the control signal S1. The buffer circuit 34 outputs a signal S2 having a level substantially equal to the control signal S1. Therefore, the signals S2x and S2 are complementary signals. These signals S2x and S2 are supplied to the gates of the transistors TA and TB, respectively.

  The transistors TA and TB are both P-channel MOS transistors, the sources of which are connected to each other and the constant current source 35. The drain of the transistor TA is connected to the resistor R1, and the drain of the transistor TB is connected to the resistor R2.

  The Vth shift circuit 10 is connected to the reference voltage generation circuit 36. The reference voltage generation circuit 36 includes a constant current source 37 and a resistor R3. The first terminal of the constant current source 37 is connected to the high potential power source AVD, the second terminal of the constant current source 37 is connected to the first terminal of the resistor R3, and the second terminal of the resistor R3 is connected to the low potential power source AVS. ing. The constant current source 37 is set to flow a current (for example, 100 μA) proportional to the supply current (for example, 10 mA) of the constant current source 35 of the current output unit 32. The resistance R3 is set to a resistance value (for example, 10 kΩ) so that the node N1 between the resistance R3 and the constant current source 37 has the maximum terminal voltage (for example, 1 V) of the resistances R1 and R2. ing. The voltage at the node N1 is supplied to the Vth shift circuit 10 as the input voltage Vi for the Vth shift circuit 10.

  4A shows the operating state of the transistors TA and TB in the present embodiment, and FIG. 4B shows the operating state of the transistors TA and TB in the conventional example. In the conventional example, the voltage of the low potential side power supply terminal of the inverter circuit 53 and the buffer circuit 54 is generated by a transistor. For this reason, the operations of the transistors TA and TB vary depending on the process. The transistors TA and TB operate in a saturation region where the vertical axis is 0 or more. For this reason, when the maximum value of the output voltage is set to 1 V, for example, the operation is performed in the non-saturated region due to process variations.

  On the other hand, in the present embodiment, since the Vth shift circuit 10 generates the voltage Vo shifted by the threshold voltage Vth with respect to the output voltage, the states of the transistors TA and TB do not vary depending on the process. In FIG. 4A, the waveforms indicating the characteristics of FIG. 4B overlap. As described above, by using the Vth shift circuits 10 and 20 of the present embodiment, it is possible to design a circuit that is not affected by process variations.

As described above, according to the present embodiment, the following effects can be obtained.
(1) A first transistor T1 and a second transistor T2 are connected in series between the constant current source 11 connected to the high potential power source AVD and the low potential power source AVS. Further, third to fifth transistors T3 to T5 are connected in series between the constant current source 11 and the low potential power source AVS. The input voltage Vi is supplied to the gate of the first transistor T1, and the gate and drain of the third transistor T3 are connected to each other. The fourth transistor T4 has a gate and a drain connected to each other and to the drain of the fifth transistor. Transistors T2 and T5 have gates connected to each other and to the drain of transistor T2 to form a current mirror circuit. Then, the drain voltage of the connected transistors T4 and T5 is output as the output voltage Vo.

  According to this configuration, the output voltage Vo has a value corresponding to the gate-source voltages of the first, third, and fourth transistors T1, T3, and T4 with respect to the input voltage Vi. Since the gate-source voltages of the transistors T1, T3, and T4 correspond to the threshold voltage Vth of the respective transistors, they are shifted by the threshold voltage Vth of the transistors T1, T3, and T4 with respect to the input voltage Vi. The output voltage Vo can be obtained.

  (2) The second constant current source 21 and the sixth transistor T6 are connected in series between the high potential power supply AVD and the low potential power supply AVS, the drain voltage of the transistor T2 is supplied to the gate of the transistor T6, The output voltage Vo is output from a node between the two constant current sources 21 and the transistor T6. As a result, the transistor T6 functions as a source grounded circuit, and the Vth shift circuit 20 having a small output impedance is obtained.

  (3) The D / A converter 30 includes a Vth shift circuit 10 (20), and signals S2x and S2 having levels corresponding to the output voltage Vo of the Vth shift circuit 10 (20) are supplied to one transistor TA and TB. I tried to supply.

  As a result, by supplying a signal to the gates of the pair of transistors based on the output voltage of the Vth shift circuit, the pair of transistors can be operated in the saturation region, and the maximum voltage can be output. Become.

In addition, you may implement the said embodiment in the following aspects.
In the above embodiment, the shift circuits 10 and 20 are applied to the D / A converter 30, but may be applied to other circuits.

It is a circuit diagram of a Vth shift circuit. It is a circuit diagram of a Vth shift circuit. It is a circuit diagram of a D / A converter. (A) and (b) are operation | movement explanatory drawings of a transistor. It is a circuit diagram of the conventional D / A converter.

Explanation of symbols

10, 20 Vth shift circuit 11, 12 Constant current source T1-T6 Transistor Vi Input voltage Vo Output voltage Vth Threshold voltage AVD High potential power supply AVS Low potential power supply

Claims (4)

A first and a second transistor connected in series between a constant current source connected to a high potential power source and a low potential power source;
Third to fifth transistors connected in series between the constant current source and the low potential power source,
An input voltage is supplied to the gate of the first transistor;
The third transistor has a gate connected to a drain of the third transistor;
The gate of the fourth transistor is connected to the drain of the fourth transistor and the drain of the fifth transistor;
The second and fifth transistors have a gate connected to each other and a drain of the second transistor to form a current mirror circuit,
Outputting drain voltages of the fifth transistor and the fourth transistor connected to each other as an output voltage;
A Vth shift circuit characterized by the above. A first and a second transistor connected in series between a constant current source connected to a high potential power source and a low potential power source;
Third to fifth transistors connected in series between the constant current source and the low potential power source,
An input voltage is supplied to the gate of the first transistor;
The third transistor has a gate connected to a drain of the third transistor;
The drain of the fourth transistor and the drain of the fifth transistor are connected;
The second and fifth transistors have a gate connected to each other and a drain of the fifth transistor to form a current mirror circuit,
A second constant current source and a sixth transistor are connected in series between the high potential power source and the low potential power source,
The drain of the second transistor is connected to the gate of the sixth transistor;
An output voltage is output from a node between the second constant current source and the sixth transistor, and the output voltage is fed back to the gate of the fourth transistor. A decoder circuit for decoding a digital signal and generating a plurality of control signals;
A plurality of current output units to which the control signals are respectively input;
The plurality of current output units each include a signal generation circuit that generates a complementary signal by the control signal, and a pair of transistors to which the complementary signal is input, and currents flowing from transistors that are turned on based on the control signal In a D / A converter that supplies an output current corresponding to the digital signal to a load,
A voltage generation circuit for generating a voltage corresponding to the terminal voltage of the load;
The Vth shift circuit according to claim 1 or 2, wherein the output voltage of the voltage generation circuit is an input voltage, and an output voltage obtained by shifting the input voltage is output.
With
The D / A converter characterized in that the signal generation circuit supplies a signal to the gates of the pair of transistors by setting the output voltage of the Vth shift circuit to a low potential level. The signal generation circuit includes an inverter circuit to which the control signal is input and a buffer circuit to which the control signal is input.
4. The D / A converter according to claim 3, wherein an output voltage of the Vth shift circuit is supplied to a low potential side power supply terminal of the inverter circuit and the buffer circuit.

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