JP2018019223A - Single differential conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a single differential conversion circuit capable of enlarging an input and output operation range.SOLUTION: A single differential conversion circuit 11 generates a first output signal and a second output signal on the basis of an input signal. The single differential conversion circuit includes: a first level shifter 12 that generates a first level shift signal by shifting a level of the input signal and generates a second level shift signal by shifting a second output signal; a differential amplifier 13 that generates a first amplification signal that amplifies a difference of the first and second level sift signals and a second amplification signal that inverts a phase of the first amplification signal; and a second level shifter 14 that generates the first output signal by shifting the first amplification signal, generates the second output signal by shifting the second amplification signal, and supplies the second output signal to the first level shifter.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a single differential conversion circuit.

  A single differential conversion circuit that converts a single-ended signal into a differential signal includes, for example, a differential amplifier and a level shift of the output of the differential amplifier to change the phase of the differential signal (the first output signal and the first output signal). And an operational amplifier having a level shifter for generating an inverted second output signal. The differential amplifier amplifies the potential difference between the input signal and the second output signal to generate a first amplified signal and a second amplified signal. The level shifter level-shifts the first amplified signal and the second amplified signal to generate a first output signal and a second output signal.

  The differential amplifier includes a differential transistor pair composed of a pair of NMOS transistors that receives an input signal, a load transistor pair composed of a pair of PMOS transistors serving as a current path of an operating current flowing through the differential transistor pair, and a differential A constant current source connected between a source terminal of the transistor pair and a ground potential; In such a differential amplifier, a configuration is proposed in which a current source for offset voltage correction is provided between the source of a load transistor pair and a power source in order to correct the offset voltage (for example, Patent Document 1).

  On the other hand, the level shifter includes, for example, a first NMOS transistor that receives a first amplified signal at its gate terminal, a second NMOS transistor that receives a second amplified signal at its gate terminal, and a first NMOS transistor. The first current source is connected to the second NMOS transistor, and the second current source is connected to the second NMOS transistor.

JP 2008-017354 A

  The lower limit of the input range of the operational amplifier as described above is determined by the sum of the gate-source voltage of the NMOS transistor constituting the differential transistor pair of the differential amplifier and the voltage applied to the constant current source of the differential amplifier. On the other hand, the output range of the operational amplifier has an upper limit determined by the sum of the drain-source voltage of the PMOS transistor constituting the load transistor pair of the differential amplifier and the gate-source voltage of the first NMOS transistor constituting the level shifter. . Therefore, since the input range is located on the power supply voltage side and the output range is located on the ground potential side, the area where the input range and the output range overlap is narrow. Therefore, there is a problem that the input / output operation range of the single differential conversion circuit cannot be widened.

  In order to solve the above problems, an object of the present invention is to provide a single differential conversion circuit capable of widening an input / output operation range.

  A single differential conversion circuit according to the present invention is a single differential conversion circuit that generates a first output signal and a second output signal based on an input signal, and level-shifts the input signal to generate a first level shift signal. A first level shifter that generates a second level shift signal by level-shifting the second output signal, and a first amplification that amplifies a difference between the first level shift signal and the second level shift signal A differential amplifier that generates a signal and a second amplified signal obtained by inverting the phase of the first amplified signal, a level shift of the first amplified signal to generate the first output signal, and the second output signal And a second level shifter for shifting the level of the amplified signal to generate the second output signal and supplying the second output signal to the first level shifter.

  According to the present invention, it is possible to widen an input / output range in a single differential conversion circuit.

It is a block diagram which shows the structure of a single differential conversion circuit. It is a time chart which shows the example of each signal produced | generated in a single differential conversion circuit. It is a time chart which shows the example of each signal produced | generated in a single differential conversion circuit. It is a block diagram which shows the structure of the single differential conversion circuit of a comparative example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  The single differential conversion circuit 10 includes a DC cut capacitor C0, an operational amplifier 11, and a feedback resistor R0. The operational amplifier 11 includes a first level shifter 12, a differential amplifier 13, a second level shifter 14, and a CMFB (Common Mode Feedback) circuit 15.

  The first level shifter 12 includes P-channel MOS transistors M3 and M4, which are the second conductivity type, and constant current sources I1 and I2. The ground potential GND is applied to the drain terminals of the transistors M3 and M4. The source terminal of the transistor M3 is connected to the constant current source I1 through the node n1. The source terminal of the transistor M4 is connected to the constant current source I2 via the node n2.

  The input signal IN is supplied to the gate terminal of the transistor M3 through the DC cut capacitor C0. The transistor M3 shifts the level of the input signal IN to generate a level shift signal INM and sends it to the node n1. On the other hand, the second output signal OUT2 of the operational amplifier 11 is supplied as the input signal INP 'to the gate terminal of the transistor M4. The transistor M4 generates a level shift signal INP by shifting the level of the input signal INP 'and sends it to the node n2.

  The differential amplifier 13 includes N-channel MOS transistors M1 and M2, which are the first conductivity type, a constant current source I3, and P-channel MOS transistors M5 and M6. Transistors M1 and M2 constitute a differential transistor pair, and transistors M5 and M6 constitute a load transistor pair.

  The source terminals of the transistors M1 and M2 are connected to the constant current source I3. The constant current source I3 is connected to the ground potential GND. The drain terminal of the transistor M1 is connected to the drain terminal of the transistor M5 through the node n3. The drain terminal of the transistor M2 is connected to the drain terminal of the transistor M6 through the node n4. Transistors M5 and M6 have their gate terminals connected to each other and a power supply voltage VDD applied to their source terminals. A level shift signal INM is applied to the gate terminal of the transistor M1. A level shift signal INP is applied to the gate terminal of the transistor M2.

  The differential amplifier 13 generates a first amplified signal AOP1 obtained by amplifying the difference between the level shift signals INM and INP, and outputs the first amplified signal AOP1 from the node n3. Further, the differential amplifier 13 generates a second amplified signal AOP2 obtained by inverting the phase of the first amplified signal AOP1, and outputs it from the node n4.

  The second level shifter 14 includes N-channel MOS transistors M7 and M8, constant current sources I4 and I5, and resistors R1 and R2. The power supply voltage VDD is applied to the drain terminals of the transistors M7 and M8.

  The source terminal of the transistor M7 is connected to the constant current source I4 via the node n5. The source terminal of the transistor M8 is connected to the constant current source I5 via the node n6. The constant current sources I4 and I5 are connected to the ground potential GND, respectively.

  The first amplified signal AOP1 is supplied to the gate terminal of the transistor M7. The transistor M7 shifts the level of the first amplified signal AOP1 to generate the first output signal OUT1, and outputs it from the node n5. The second amplified signal AOP2 is supplied to the gate terminal of the transistor M8. The transistor M8 shifts the level of the second amplified signal AOP2 to generate the second output signal OUT2, and outputs it from the node n6.

  The output line of the first output signal OUT1 is connected to the gate terminal of the transistor M3 of the first level shifter 12 via the feedback resistor R0. The output line of the second output signal OUT2 is connected to the gate terminal of the transistor M4 of the first level shifter 12.

  Between the connection line of the transistor M7 and the constant current source I4 and the connection line of the transistor M8 and the constant current source I5, resistors R1 and R2 connected in series are connected. A common mode voltage Vcm that is an average voltage of the first output signal OUT1 and the second output signal OUT2 is output from a node n7 between the resistor R1 and the resistor R2 and supplied to the CMFB circuit 15.

  The CMFB circuit 15 supplies the differential voltage Vcb, which is the difference between the common mode voltage Vcm and the reference voltage Vref supplied from the outside, to the gate terminals of the transistors M5 and M6 constituting the load transistor pair of the differential amplifier 13. Thus, the CMFB circuit 15 controls the gate potentials of the transistors M5 and M6, and operates the differential amplifier 13 so that the common mode voltage Vcm and the reference voltage Vref are equal.

  Next, the operation of the single differential conversion process executed by the single differential conversion circuit 10 will be described with reference to the time charts of FIGS.

  An input signal IN having a sine wave signal waveform as shown in FIG. 2 is supplied to the gate terminal of the transistor M3 of the first level shifter 12 via the DC cut capacitor C0. The first level shifter 12 shifts the level of the input signal IN to generate a level shift signal INM. For example, a signal obtained by level-shifting the input signal IN by the voltage indicated by “α” in FIG. 2 in the positive direction (that is, the direction in which the voltage level increases) is generated as the level shift signal INM.

  On the other hand, an input signal INP ′ having a signal waveform opposite in phase to the input signal IN as shown in FIG. 3 is supplied to the gate terminal of the transistor M4 of the first level shifter 12. The first level shifter 12 generates a level shift signal INP by shifting the level of the input signal INP ′. For example, a signal obtained by level-shifting the input signal INP ′ by the voltage indicated by “α” in FIG. 3 in the positive direction (that is, the direction in which the voltage level increases) is generated as the level shift signal INP.

  The differential amplifier 13 generates a signal obtained by amplifying the difference between the level shift signals INM and INP as the first amplified signal AOP1. The differential amplifier 13 generates a signal obtained by inverting the phase of the first amplified signal AOP1 as the second amplified signal AOP2.

  As shown by the arrows in FIG. 2, the first amplified signal AOP1 has a signal level that decreases as the signal level of the level shift signal INM increases, and increases as the signal level of the level shift signal INM decreases. Signal waveform.

  As indicated by the arrows in FIG. 3, the second amplified signal AOP2 has a signal level that decreases as the signal level of the level shift signal INP increases, and increases as the signal level of the level shift signal INP decreases. Signal waveform.

  The first amplified signal AOP1 is supplied to the gate terminal of the transistor M7 of the second level shifter 14. The second level shifter 14 shifts the level of the first amplified signal AOP1 to generate the output signal OUT1. For example, a signal obtained by level-shifting the first amplified signal AOP1 in the negative direction (that is, the direction in which the voltage level decreases) by the voltage indicated by “β” in FIG. 2 is generated as the first output signal OUT1.

  The second amplified signal AOP2 is supplied to the gate terminal of the transistor M8 of the second level shifter 14. The second level shifter 14 shifts the level of the second amplified signal AOP2 to generate the output signal OUT2. For example, a signal obtained by level-shifting the second amplified signal AOP2 in the negative direction (that is, the direction in which the voltage level decreases) by the voltage indicated by “β” in FIG. 3 is generated as the second output signal OUT2.

  As described above, the first level shifter 12 generates a level shift signal INM by level shifting the input signal IN, and the level shift signal INM is supplied to the differential amplifier 13. Therefore, compared to the case where the first level shifter 12 is not provided, a signal having a signal level that is lower by the amount of the level-shifted voltage (“α” in FIG. 2) can be used as the input signal IN. That is, the input range of the operational amplifier 11 is shifted downward by the level shift by the first level shifter 12.

  FIG. 4 is a block diagram illustrating a configuration of a single differential conversion circuit 20 as a comparative example that does not include the first level shifter 12.

  The single differential conversion circuit 20 includes a DC cut capacitor C0, an operational amplifier 21, and a feedback resistor R0. The operational amplifier 21 includes a differential amplifier 23, a level shifter 24, and a CMFB circuit 25.

  The differential amplifier 23 includes N-channel MOS transistors M1 and M2 constituting a differential transistor pair, a constant current source I3, and P-channel MOS transistors M5 and M6 constituting a load transistor pair. An input signal IN is supplied to the gate terminal of the transistor M1. An input signal INP ′ is supplied to the gate terminal of the transistor M2.

  The differential amplifier 23 generates a first amplified signal AOP1 obtained by amplifying the difference between the input signals IN and INP, and outputs the first amplified signal AOP1 from the node n3. Further, the differential amplifier 13 generates a second amplified signal AOP2 obtained by inverting the phase of the first amplified signal AOP1, and outputs it from the node n4.

  The input / output operation range of the operational amplifier 21 is a region where the input voltage range and the output voltage range of the operational amplifier 21 overlap. The input voltage range is located closer to the power supply potential VDD than the ground potential GND. On the other hand, the output voltage range is located closer to the ground potential GND than the power supply potential VDD. Accordingly, the input / output operation range of the operational amplifier 21 is from the lower limit value of the input voltage range to the upper limit value of the output voltage range.

  The lower limit value of the input voltage range of the operational amplifier 21 is determined by the sum of the gate-source voltage of the transistor M1 and the voltage applied to the current source I3. When the gate-source voltage of the transistor M1 is Vgs1, and the voltage applied to the current source I3 is VI3, the lower limit value Vmin of the input voltage range is Vmin = Vgs1 + VI3.

  On the other hand, the output voltage range of the operational amplifier 21 has an upper limit value obtained by subtracting the drain-source voltage of the transistor M6 and the gate-source voltage of the transistor M7 from the power supply voltage VDD. When the drain-source voltage of the transistor M6 is Vds6 and the gate-source voltage of the transistor M7 is Vgs7, the upper limit value Vmax of the output voltage range is Vmax = VDD− (Vds6 + Vgs7).

  On the other hand, in the operational amplifier 11 of the present invention shown in FIG. 1, the first level shifter 12 shifts the level of the input signal IN in the direction in which the voltage level increases by the voltage indicated by “α” in FIG. A shift signal INM is generated and supplied to the differential amplifier 13. Therefore, the lower limit value Vmin of the input voltage range of the operational amplifier 11 is Vmin = Vgs1 + VI3-α.

  As described above, the operational amplifier 11 in FIG. 1 is shifted from the operational amplifier 21 in FIG. 4 to the lower side of the input voltage range by the voltage value “α” (that is, the voltage level is lower). It becomes. Therefore, according to the single differential conversion circuit 10 of the present invention, the input / output operation range of the operational amplifier 11 can be widened as compared with the case where the first level shifter 12 is not provided.

  In addition, this invention is not limited to the said embodiment. For example, in the above-described embodiment, the example in which the first level shifter 12 includes the P-channel MOS transistors M3 and M4 and the constant current sources I1 and I2 has been described. However, the configuration of the first level shifter 12 is not limited to this, and has a function of level-shifting the input signal IN and the second output signal OUT2 and supplying them to the differential transistor pair (transistors M1 and M2) of the differential amplifier 13. Anything is fine.

  In the above embodiment, the case where the first conductivity type is the N type and the second conductivity type is the P type, which is the opposite conductivity type to the first conductivity type (N type), is not limited to this. The first conductivity type may be P-type and the second conductivity type may be N-type.

  Further, in the above-described embodiment, an example in which the single differential conversion circuit 10 outputs the first output signal OUT1 and the second output signal OUT2 has been described. However, it may be configured to output only one side of the output signal. According to such a configuration, the single differential conversion circuit 10 of the present invention can be used as a buffer amplifier.

10 single differential conversion circuit 11 operational amplifier 12 first level shifter 13 differential amplifier 14 second level shifter 15 CMFB circuit

Claims (4)

A single differential conversion circuit for generating a first output signal and a second output signal based on an input signal,
A first level shifter for level-shifting the input signal to generate a first level-shifted signal and level-shifting the second output signal to generate a second level-shifted signal;
A differential amplifier that generates a first amplified signal obtained by amplifying a difference between the first level shifted signal and the second level shifted signal, and a second amplified signal obtained by inverting the phase of the first amplified signal;
The first amplified signal is level shifted to generate the first output signal, the second amplified signal is level shifted to generate the second output signal, and the second output signal is converted to the first level shifter. A second level shifter for supplying to
A single differential conversion circuit comprising: The differential amplifier includes a differential transistor pair including a first transistor and a second transistor of a first conductivity type,
The first level shifter includes a third transistor and a fourth transistor of a second conductivity type that are opposite to the first conductivity type,
The third transistor has a source terminal connected to the gate terminal of the first transistor, receives the input signal supplied to the gate terminal, and supplies the first level shift signal to the gate terminal of the first transistor,
The fourth transistor has a source terminal connected to the gate terminal of the second transistor, receives the second output signal supplied to the gate terminal, and supplies the second level shift signal to the gate terminal of the second transistor. The single differential conversion circuit according to claim 1. The differential amplifier has a load transistor pair serving as a current path of a current flowing through the differential transistor pair,
The load transistor pair includes a second transistor and a sixth transistor of the second conductivity type whose gate terminals are connected to each other.
The second level shifter is:
The gate terminal is connected to the drain terminal of the first transistor and the drain terminal of the fifth transistor, and the first amplified signal is supplied to the gate terminal and outputs the first output signal. A seventh transistor;
The gate terminal is connected to the drain terminal of the second transistor and the drain terminal of the sixth transistor. The gate terminal is supplied with the second amplified signal and outputs the second output signal. An eighth transistor;
The single differential conversion circuit according to claim 2, further comprising:   And a common feedback circuit for supplying a control voltage corresponding to a potential difference between a reference voltage and an intermediate voltage between the first output signal and the second output signal to the gate terminals of the fifth transistor and the sixth transistor. The single differential conversion circuit according to claim 3.

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