JP2003188692A - Flip-flop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize a flip-flop circuit. <P>SOLUTION: A data holding circuit is formed by inverters G5, G6, the connection point between an output of the inverter G5 and an input of the inverter G6 is rendered operable as a node Q, and the connection point between an output of the inverter G6 and an input of the inverter G5 is rendered operable as a node QN. An nMOS transistor M4 driven by a data signal and an nMOS transistor M3 driven by a clock CK2 are connected in series between the node Q and a ground terminal. An nMOS transistor M1 driven by an inverted signal of the data signal and an nMOS transistor M2 driven by the clock CK2 are connected in series between the node QN and the ground terminal. A minute width pulse generating circuit generates a minute width pulse shorter than the time width of an inputted clock CK1 and supplies it as the clock CK2. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit to which a latch circuit having a small occupied area is applied.

[0002]

2. Description of the Related Art Memory circuits are a major part of today's digital integrated circuits. The reason for this is that with the miniaturization of devices, it has become possible to incorporate a wide variety of functions on the same chip, and as a result, it becomes more necessary to store intermediate results between them on the same chip in a form that enables high-speed access, and This is because the amount of data is also increasing rapidly.

Conventionally, this kind of memory circuit has been realized by a latch circuit or a flip-flop circuit. The latch circuit is a circuit that takes in new data while the level of the clock signal is high or low. Although the circuit scale is small, it is necessary to pay attention to the timing of capturing data when designing. On the other hand, the flip-flop circuit is a circuit for capturing new data at the rising edge or the falling edge of the clock signal. Although the circuit scale is larger than that of the latch circuit, there is an advantage that the timing design is easy.

[0004]

In recent years, a circuit format has been proposed which combines the small area of a latch circuit and the ease of timing design of a flip-flop circuit. The circuit example and the timing sequence are shown in FIGS. 15 and 16, respectively. In the circuit shown in FIG. 15, a CMOS transmission gate type latch circuit is driven by a minute time width pulse signal (minute width pulse signal) synchronized with the rising edge of the clock to operate as an edge trigger flip-flop circuit.

However, such a conventional circuit has a problem that it cannot be sufficiently miniaturized because the latch circuit which is a constituent element of the circuit is of the transmission gate type.

Therefore, it is an object of the present invention to enable miniaturization of a latch circuit which is a memory circuit which constitutes a flip-flop circuit.

[0007]

In order to solve such a problem, the present invention comprises first and second circuits for inverting and outputting an input signal, the output terminal of the first circuit and the second circuit. Data holding circuit in which a connection point with the input terminal of the second circuit is provided as a first data input terminal, and a connection point between the output terminal of the second circuit and the input terminal of the first circuit is provided as a second data input terminal And the first nMO driven by the data signal
A second nMO driven by a second clock signal generated based on the S-transistor and the first clock signal
An S transistor is driven by a first data input control section in which a first data input terminal and a ground terminal are connected in series, a third nMOS transistor driven by an inverted signal of a data signal, and a second clock signal. A fourth data input control unit in which a fourth nMOS transistor is connected in series between the second data input terminal and the ground terminal,
A clock supply circuit for generating a pulse signal having a time width shorter than that of the first clock signal when the first clock signal is input and supplying the pulse signal as a second clock signal to the data input control unit is provided. .

Here, the clock supply circuit includes a first inverter circuit that delays and inverts the first clock signal, and a first inverter circuit.
Second inverter circuit which delays and inverts the output of the inverter circuit of FIG.
And a two-input NOR circuit that outputs as a clock signal.

The present invention also provides a first nMOS transistor driven by a second clock signal, a second nMOS transistor driven by a data signal, and a first nMOS transistor.
A first data input control section in which a third nMOS transistor driven by the clock signal is connected in series between the first data input terminal and the ground terminal, and a fourth nMOS driven by the second clock signal. A transistor, a fifth nMOS transistor driven by the inverted signal of the data signal, and a sixth nMOS transistor driven by the first clock signal, connected in series between the second data input terminal and the ground terminal; When the data input control unit and the first clock signal are input, the input first clock signal is supplied to the data input control unit, and a delayed inversion signal of the first clock signal is generated as a second clock signal. A clock supply circuit for supplying the data input control unit is provided.

Here, the clock supply circuit includes a first inverter circuit that delays and inverts the first clock signal, and a first inverter circuit.
The second inverter circuit delays and inverts the output of the inverter circuit and the third inverter circuit that delays and inverts the output of the second inverter circuit and outputs it as the second clock signal.

Further, the first and second circuits of the data holding circuit are each constituted by an inverter circuit. Further, the first circuit of the data holding circuit is composed of an inverter circuit, the second circuit is composed of a 2-input NAND circuit, and the output terminal of the inverter circuit is connected to the first input terminal of the 2-input NAND circuit. The point is provided as the first data input terminal, and the second input terminal of the 2-input NAND circuit is provided as the input terminal of the clear signal for setting the logical value of the first data input terminal to "0". . In addition, the first and second data outputs the data input via the first and second data input control units and held in the data holding circuit to the outside via the first and second data input terminals, respectively. An output gate is provided.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a diagram showing a first embodiment of a flip-flop circuit according to the present invention.
1 shows a circuit configuration of a flip-flop circuit using an M-type latch circuit. FIG. 2 is a timing chart showing the timing of each part of the flip-flop circuit shown in FIG.

In FIG. 1, inverter circuits G1 and G2 are provided.
The 2-input NOR circuit G3 is a very small pulse generation circuit A1.
Are configured. The minute pulse generator circuit A1 is shown in FIG.
The clock signal CK1 shown in (b) is input, and the minute width pulse signal CK2 shown in FIG. 2 (c) is generated at the rising edge thereof. Further, in FIG. 1, the inverter circuits G5 and G6 form a data holding circuit. The data holding circuit connects its input terminal and output terminal to the node Q,
Connect with QN and save the data written via the same node.

Further, the inverter G4 inputs the data signal D and outputs an inverted signal thereof. The nMOS transistors M1, M2, M3, M4 form a data input control unit, and each nMOS transistor M
1, M2, M3, M4 are controlled by the data signal D or its inverted signal, or the minute width pulse signal CK2. A flip-flop circuit is configured by the data holding circuit and the data input control unit described above. In the minute width pulse generation circuit A1, the inverted signal of the clock signal CK1 and the signal delayed by the inverter circuit G2 are divided into two.
It is input to the input NOR circuit G3. As a result, at the moment when the clock signal CK1 changes from 0 to 1, 2-input NO
Both of the two input signals of the R circuit G3 can be set to 0 for a short period of time, and the pulse signal CK2 having a minute time width can be generated accordingly. The timing chart shown in FIG. 2 schematically shows that the minute width pulse signal CK2 is generated at the rising edge of the clock signal CK1.

Four nMOS transistors M1, M2
The data input control unit composed of M3 and M4 switches the operation mode of the latch circuit B1 between holding and passing according to the logical value of the minute width pulse signal CK2. The logic value of the minute width pulse signal CK2 and each control device (M1, M2, M
Table 1 shows the correspondence between the conduction state of M3, M4) and the operation mode of the latch circuit B1.

[0016]

[Table 1]

In Table 1, the pass mode is 1 for CK2,
The holding mode corresponds to the case where CK2 is 0. Therefore, the clock signal CK is generated by the minute width pulse generation circuit A1.
At the rising edge of 1, the clock signal CK2 is changed from 0 → 1 →
By instantly switching to 0, the latch circuit B1 is switched to C
It can be operated as an edge trigger flip-flop circuit of K1. From the above, in the present embodiment, R
By adopting the AM type latch circuit, the latch circuit itself can be miniaturized, and the latch circuit can be operated as a flip-flop by the minute width pulse, so that a flip-flop circuit smaller than the conventional one can be realized.

(Second Embodiment) FIG. 3 is a diagram showing a second embodiment of the present invention, which is a RAM type latch circuit B.
2 shows a configuration of a flip-flop circuit using 2. In the second embodiment, the flip-flop circuit of the first embodiment described above is modified, and a clear input terminal CLR is newly added so that the data held in the data holding circuit is transferred to the node Q. It can be set to 0. In the second embodiment, the data holding circuit is composed of an inverter circuit G5 and a 2-input NAND circuit G7. The output of the inverter circuit G5 and the 2-input NAND circuit G
One of the inputs of 7 is connected to the node Q, and the inverter circuit G
The input of 5 and the output of the 2-input NAND circuit G7 are connected to the node QN.
Connect to.

The input 1 of the 2-input NAND circuit G7 is 1
One is connected to the clear input terminal CLR. This causes the clear signal input to the clear input terminal CLR to have a logical value of 0.
Therefore, the data held in the data holding circuit is transferred to the node Q.
Can be set to 0 and the node QN can be set to 1. When operating as a flip-flop, the clear signal input to the clear input terminal CLR is set to the logical value 1.

(Third Embodiment) FIG. 4 is a diagram showing a third embodiment of the present invention, which is a RAM type latch circuit B.
3 shows a circuit configuration of a flip-flop circuit using No. 3. FIG. 5 is a timing chart showing the operation timing of each part of the flip-flop circuit shown in FIG. In FIG. 4, the inverters G1, G2 and G8 form a delayed inverted clock generation circuit A2. The delayed inverted clock generation circuit A2 receives the clock signal CK1 as an input and delays and inverts the clock signal CK1 to output a clock signal CKBd. Here, the inverter circuits G5 and G6 constitute a data holding circuit as shown in the first embodiment, and their input terminals and output terminals are connected by the nodes Q and QN, and the same node is connected. Save the data written through. Further, the inverter G4 inputs the data signal D,
The inverted signal is output. Further, the nMOS transistors M1, M2, M3, M4, M5 and M6 form a data input control section.

Each of the nMOS transistors M1 and M
2, M3, M4, M5 and M6 are controlled by the data signal D or its inverted signal, the clock signal CK1 or its delayed inverted clock signal CKBd, and nM
The source terminals of the OS transistors M3 and M4 are connected to the ground terminal. In the delayed inverted clock generation circuit A2, the clock signal CK1 is input to the three-stage inverter circuit chain, and the delayed and inverted clock signal CKBd is generated as the output. The timing relationship between CK and CKBd is schematically shown in the timing chart of FIG.

Six nMOS transistors M1, M2
The data input control unit consisting of M3, M4, M5 and M6 is
Depending on the logical values of CK1 and CKBd, the latch circuit B3
Switch the operating mode of between holding and passing. CK1
Table 2 shows the correspondence between the logical value of CKBd, the conduction state of each device, and the operation mode of the latch circuit.

[0023]

[Table 2]

In Table 2, the passing modes are CK1 and CK.
Both Bd correspond to a logical value of 1, and the holding mode corresponds to all other cases. Therefore, as shown in the timing chart of FIG. 5, switching between the passing mode and the holding mode is performed by simply delaying the original clock signal CK1.
This can be easily realized by generating the inverted clock signal CKBd and making a slight timing in which both are 1. As a result, the minute width pulse generation circuit A1 as shown in the first embodiment is unnecessary, the additional circuit for internal clock signal generation can be made small, and the entire flip-flop circuit can be miniaturized. .

(Fourth Embodiment) FIG. 6 shows a fourth embodiment of the present invention.
Is a diagram showing an embodiment of a RAM type latch circuit B4.
1 shows a circuit configuration of a flip-flop circuit using the. The present embodiment is a modification of the flip-flop circuit of the third embodiment of FIG. 4, in which a clear input terminal CLR is newly added so that the data held in the data holding circuit is set to 0 at node Q. It was made possible.

In the fourth embodiment, the data holding circuit is composed of an inverter circuit G5 and a 2-input NAND circuit G7. Output of inverter circuit G5 and 2-input NAND
One of the inputs of the circuit G7 is connected to the node Q, and the input of the inverter circuit G5 and the output of the two-input NAND circuit G7 are connected to the node QN. Also, one of the inputs of the 2-input NAND circuit G7 is connected to the clear input terminal CLR. Accordingly, by setting the clear signal input to the clear input terminal CLR to the logical value 0, the data held in the data holding circuit can be set to 0 at the node Q and 1 at the node QN.
When operating as a flip-flop, the clear signal input to the clear input terminal CLR is set to the logical value 1.

(Fifth Embodiment) FIGS. 7 and 8 are views showing a fifth embodiment of the present invention. A register file having a 16-bit width and 16 lines using a RAM type latch circuit is shown. Is shown. Here, FIG. 7 shows the overall structure of the register file. Reference numeral B-0-0 in FIG.
The circuit block indicated by B-15-15 represents a RAM type latch circuit. In FIG. 7, 16 latch circuits arranged in the row direction constitute one 16-bit width register,
Sixteen of these are arranged in the column direction. In FIG.
Inverter circuits G1 and G2 and 3-input NOR circuit G1
, G12, ..., G26 form a minute width pulse signal generation circuit. Then, this minute width pulse signal generation circuit generates a minute width pulse CK2 from the clock signal CK1, and the latch circuit BX (X = 0-0 to 15-
Supply to 15). In addition, the 3-input NOR circuits G11 and G1
2, ..., G26 are decoded signals dec [0], d
ec [1], ..., Dec [15] are input respectively, and {D15, DN15 ,.
Controls whether to write the data given by D0, DN0}.

FIG. 8 shows a RAM type latch circuit BX (X = 0-0-0) with clear used in the register file shown in FIG.
15-15). This latch circuit BX
Since (X = 0-0 to 15-15) is used in the second embodiment of FIG. 3, its detailed description is omitted. Note that FIG.
The output gates denoted by reference symbols GY and GYN output the data at nodes Q and QN to external buses Y and YN, respectively, in response to a read signal from read control terminal OE. Where OE =
Data is output when 1 and high impedance is output when OE = 0. The same applies to the following embodiments.

In the fifth embodiment, the decode signal de
The register to be written is designated by c [0], dec [1], ..., Dec [15], and the clock signal C
By raising K1, the set value can be written to the data input terminals D and DN of the latch circuit BX on the designated register. In this way, the minute width pulse signal C
Each latch circuit BX (X = 0-0 to 15-15) by K2
Can be used as a flip-flop that stores data at the rising edge of the clock signal CK1.

According to the fifth embodiment, a part of the minute width pulse generating circuit and the decoding circuit can be shared.
Moreover, since the memory circuit element can be miniaturized by the RAM type latch circuit, the circuit scale of the entire register file can be reduced as compared with the case where the conventional master-slave type flip-flop circuit and the decoder circuit are combined.
Here, the master-slave type flip-flop circuit is a flip-flop circuit in which two stages of latch circuits are connected in series and driven by clock signals of opposite phases. Since the master-slave flip-flop circuit is in the data passing mode and the data storing mode exclusively to each other, the data can be taken in at the rising edge or the falling edge of the clock signal. That is, the master-slave flip-flop circuit can be an edge-triggered flip-flop. However, since two latch circuits are required, the circuit scale becomes large.

(Sixth Embodiment) FIGS. 9 and 10 show
It is a figure which shows the 6th Embodiment of this invention, Comprising: It is a 16-bit width using a RAM type latch circuit, and shows a register file of 16 lines. Here, FIG. 9 shows the overall structure of the register file. Circuit blocks B-0-0 to B-15-15 shown in FIG. 9 are flip-flop circuits using a RAM type latch circuit. Figure 9
In the above, 16 flip-flop circuits arranged in the row direction constitute one 16-bit width register, and 16 of them are arranged in the column direction. Further, the 2-input NOR circuits G31, G32, ..., G46 of FIG. 9 receive the applied clock signal CK from the decode signals dec [0], dec.
Gating with [1], ..., dec [15],
Supply to the register of the row you want to write.

FIG. 10 is a diagram showing a flip-flop circuit used in the register file of FIG. The flip-flop circuit shown in FIG. 10 is similar to the flip-flop circuit shown in the third embodiment shown in FIG.
Data is stored at the falling edge of. In the sixth embodiment, the decode signal dec
The data input terminal of the flip-flop circuit BX on the designated register is designated by designating the register of the row to be written by [0], dec [1], ..., Dec [15] and raising the clock signal CK. The set value can be written in D and DN. Since the flip-flop circuit to which the RAM type latch circuit is applied is small, the area occupied by the entire register file can be reduced as compared with the case of using the conventional master-slave type flip-flop circuit.

(Seventh Embodiment) FIGS. 11 and 12 are views showing a seventh embodiment of the present invention, in which a register file having a 16-bit width and 16 lines using a RAM type latch circuit is provided. It is shown. Here, FIG. 11 shows the overall structure of the register file. Circuit blocks B-0-0 to B-15-15 shown in FIG. 11 are RAM type latch circuits. In FIG. 11, 16 latch circuits arranged in the row direction constitute one 16-bit width register, and 16 of them are arranged in the column direction. Further, the inverter circuits G1 and G2 of FIG. 11 and the 2-input NOR circuit G31,
G32 to G61, G62 (for example, two 2-input NOR circuits G31, G32 as one set, 16 sets of 2-input NO in total)
R circuit) constitutes a delayed inverted clock signal generation circuit, generates a delayed and inverted clock signal CKBd from the clock signal CK1, and generates the latch circuit BX.
(X = 0-0 to 15-15). Also, 2 input NO
The R circuits G31, G32 to G61, G62 have decode signals dec [0], dec [1], ..., Dec [1.
5] as an input, / CK (CK bar: logically inverted value of CK) and / CKBd (CKBd bar: logically inverted value of CKBd) are gated, and each latch circuit BX (X = 0-
0 to 15-15) are supplied with the clock signals CK1 and CKBd.

FIG. 12 shows the configuration of a RAM type latch circuit BX (X = 0-0 to 15-15) with a clear used for a register file. The latch circuit BX (X =
0-0 to 15-15) are used in the fourth embodiment of FIG. 6, and detailed description thereof will be omitted. In the seventh embodiment of FIG. 11, the decode signals dec [0], dec
[1], ..., Dec [15] designates the register of the row to be written and raises the clock signal CK1 to set the value set to the data input terminals D and DN of the latch circuit BX on the register. You can write
As described above, in the seventh embodiment, the two clock signals having different timings and polarities are generated and supplied to the respective latch circuits, so that the latch circuits are supplied with the clock signal CK1.
It can be used as a flip-flop that stores data at the rising edge of.

With the configuration of the seventh embodiment, a part of the delay / inverted clock generation circuit and the decoding circuit can be shared, and the memory circuit element can be miniaturized by the RAM type latch circuit. Compared with a combination of a slave flip-flop and a decoder circuit,
The circuit scale of the entire register file can be reduced.

(Eighth Embodiment) FIGS. 13 and 14 are views showing an eighth embodiment of the present invention, showing a 16-bit width, 16-register register file using a RAM type latch circuit. It is a thing. Here, FIG. 13 shows the overall structure of the register file. In addition, circuit blocks B-0-0 to B-15-15 shown in FIG. 13 represent flip-flop circuits using a RAM type latch circuit.
In FIG. 13, 16 flip-flop circuits arranged in the row direction constitute one 16-bit width register, and 16 pieces of these are arranged in the column direction. 2-input NOR of FIG.
The circuits G31, G32, ..., G46 decode the clock signal / CK (CK bar) obtained from the clock signal CK via the inverter circuit G30 into the decode signal dec.
Gating is performed with [0], dec [1], ..., Dec [15], and the data is supplied to the register of the row to be written.

FIG. 14 is a diagram showing a flip-flop circuit used for the register file. Since this flip-flop circuit is used in the fourth embodiment of FIG. 6, detailed description thereof will be omitted. In the eighth embodiment,
Decode signals dec [0], dec [1], ..., D
By specifying the register of the row to be written by ec [15] and raising the clock signal CK, the set value can be written to the data input terminals D and DN of the flip-flop circuit on the specified register. RA
Since the flip-flop circuit to which the M-type latch circuit is applied is small, the occupied area of the entire register file can be reduced as compared with the case of using the conventional master-slave flip-flop circuit.

As described above, in the present embodiment, the basic latch circuit has a RAM type configuration, and the activation / inactivation of the write path to the RAM is instantaneously switched by two clock signals with different timings. Is made possible. Further, the clock supply circuit that supplies the clock signal to the latch circuit may simply delay and invert the first clock signal to generate the second clock signal,
It is not necessary to generate a minute pulse as in the conventional example. By adopting such a configuration, the latch circuit can be downsized, and the clock supply circuit can be simplified to downsize the entire flip-flop circuit. Therefore, the area occupied by the entire digital integrated circuit can be reduced, and the circuit speed and power consumption can be reduced.

[0039]

As described above, according to the present invention, the data holding circuit is composed of the first and second circuits for inverting and outputting the input signal, and the output terminal of the first circuit and the second circuit. Is provided as a first data input terminal, and a connection point between the output terminal of the second circuit and the input terminal of the first circuit is provided as a second data input terminal. And a second nMOS transistor driven by a second clock signal generated based on the first clock signal as a first data input control section and a first data input terminal. A third nMOS transistor connected in series between the ground terminals and driven by the inverted signal of the data signal and a fourth nMOS transistor driven by the second clock signal. Is connected in series between the second data input terminal and the ground terminal as a second data input control section, while the clock supply circuit inputs the first clock signal, the time shorter than the time width of the first clock signal. Since the pulse signal having the width is generated and supplied as the second clock signal to the first and second data input control units, the latch circuit including the data holding circuit and the data input control unit can be downsized. become.

The present invention also provides a first nMOS transistor driven by a second clock signal, a second nMOS transistor driven by a data signal, and a first nMOS transistor.
Third nMOS transistor driven by the second clock signal is connected in series between the first data input terminal and the ground terminal as a first data input control unit, and is driven by the second clock signal. Transistor, fifth nM driven by inverted signal of data signal
The OS transistor and the sixth nMOS transistor driven by the first clock signal are connected in series as a second data input control unit between the second data input terminal and the ground terminal, and the clock supply circuit uses the first clock signal. When the signal is input, the input first clock signal is supplied to the data input control unit, and a delayed inverted signal of the first clock signal is generated and supplied as the second clock signal to the data input control unit. Therefore, the size of the latch circuit can be reduced, and the clock supply circuit can simply delay and invert the first clock signal to generate the second clock signal. Can be made compact.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a flip-flop circuit according to the present invention.

FIG. 2 is a timing chart of the flip-flop circuit of FIG.

FIG. 3 is a circuit diagram showing a second embodiment of a flip-flop circuit.

FIG. 4 is a circuit diagram showing a third embodiment of a flip-flop circuit.

5 is a timing chart of the flip-flop circuit of FIG.

FIG. 6 is a circuit diagram showing a fourth embodiment of a flip-flop circuit.

FIG. 7 is a circuit diagram showing a fifth embodiment of the present invention.

8 is a circuit diagram showing a configuration of a latch circuit used in the register file of FIG.

FIG. 9 is a circuit diagram showing a sixth embodiment of the present invention.

10 is a circuit diagram showing a configuration of a flip-flop circuit used in the register file of FIG.

FIG. 11 is a circuit diagram showing a seventh embodiment of the present invention.

12 is a circuit diagram showing a configuration of a latch circuit used in the register file of FIG.

FIG. 13 is a circuit diagram showing an eighth embodiment of the present invention.

14 is a circuit diagram showing a configuration of a flip-flop circuit used in the register file of FIG.

FIG. 15 is a circuit diagram showing a configuration of a conventional circuit.

16 is a timing chart of the conventional circuit shown in FIG.

[Explanation of reference numerals] G1, G2, G4, G5, G6, G8 ... Inverter circuit, G3, G30 to G62 ... 2-input NOR circuit, G7 ...
2-input NAND circuit, G11 to G26 ... 3-input NOR circuit, GY, GYN ... Output gate, M1-M6 ... nMOS
Transistors, B-0-0 to B-15-15 ... Latch circuit (or flip-flop circuit).

Claims (7)

[Claims] 1. A first and a second for inverting and outputting an input signal
And a connection point between the output terminal of the first circuit and the input terminal of the second circuit is provided as a first data input terminal, and the output terminal of the second circuit and the input terminal of the first circuit. And a data holding circuit having a connection point to and as a second data input terminal, a first nMOS transistor driven by a data signal, and a second clock signal generated based on the first clock signal. A first data input control section in which a second nMOS transistor is connected in series between the first data input terminal and a ground terminal; and a third nM driven by an inverted signal of the data signal.
A second data input control section in which an OS transistor and a fourth nMOS transistor driven by the second clock signal are connected in series between the second data input terminal and a ground terminal; and the first clock signal Is input to generate a pulse signal having a time width shorter than the time width of the first clock signal and supply the pulse signal to the first and second data input control units as the second clock signal. A flip-flop circuit characterized by the above. 2. The clock supply circuit according to claim 1, wherein the clock supply circuit delays and inverts the first clock signal, and the second inverter circuit delays and inverts an output of the first inverter circuit. And a two-input NOR circuit that inputs the outputs of the first and second inverter circuits, calculates a logical sum, and supplies an inverted signal of the logical sum signal as the second clock signal. Characteristic flip-flop circuit. 3. A first and a second circuit for inverting and outputting an input signal, wherein a connection point between the output terminal of the first circuit and the input terminal of the second circuit is provided as a first data input terminal,
And a data holding circuit having a connection point between the output terminal of the second circuit and the input terminal of the first circuit as a second data input terminal, and a second clock signal generated based on the first clock signal. A first nMOS transistor driven by
A first data input control in which a second nMOS transistor driven by a data signal and a third nMOS transistor driven by the first clock signal are connected in series between the first data input terminal and a ground terminal. And a fourth nMO driven by the second clock signal.
An S transistor, a fifth nMOS transistor driven by the inverted signal of the data signal, and a sixth nMOS transistor driven by the first clock signal are connected in series between the second data input terminal and the ground terminal. A second data input control unit, and a first clock signal that is input when the first clock signal is input to the first and second data input control units, and the first clock signal And a clock supply circuit for generating the delayed inverted signal of and supplying it to the first and second data input control units as the second clock signal. 4. The clock supply circuit according to claim 3, wherein the clock supply circuit delays and inverts the first clock signal, and a second inverter circuit delays and inverts an output of the first inverter circuit. And a third inverter circuit which delays and inverts the output of the second inverter circuit and supplies it as the second clock signal. 5. The flip-flop circuit according to claim 1, wherein the first and second circuits of the data holding circuit are each formed of an inverter circuit. 6. The data holding circuit according to claim 1, wherein the first circuit is an inverter circuit, the second circuit is a two-input NAND circuit, and the output of the inverter circuit is the same. A connection point between the terminal and the first input terminal of the 2-input NAND circuit is provided as the first data input terminal, and the second input terminal of the 2-input NAND circuit is connected to the first data input terminal. A flip-flop circuit provided as an input terminal of a clear signal for setting a logical value to "0". 7. The data according to claim 1 or 3, wherein the data input via the first and second data input control units and held in the data holding circuit are the first and second data input terminals. A flip-flop circuit having first and second output gates for outputting to the outside via the.