JP2001068974A - Two-input two-output clocked cmos inverter and d flip- flop - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a D flip-flop whose occupied area in an integrated circuit can be much more reduced. SOLUTION: The D flip-flop consists of series connection of two clocked CMOS inverters and 2-input 2-output clocked CMOS inverters in place of two clocked CMOS static latch circuits each consisting of a MOS inverter, which is simultaneously turned on/off synchronously with biphase clock pulses that are inverted from each other. The 2-input 2-output clocked CMOPS inverter is an inverter where P-MOS and N-MOS transistors(TRs) 23, 24 that are simultaneously turned on/off synchronously with biphase clock pulses that are inverted from each other are connected between two bias sources and a circuit consisting of parallel connection of CMOS inverters 21, 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-input two-output clocked CMOS inverter and a D flip-flop using a clocked CMOS inverter.

[0002]

2. Description of the Related Art Conventionally, as a D flip-flop using a clocked CMOS inverter, for example, FIG.
The following are known. This D flip-flop is a circuit having one input data terminal D, one clock pulse terminal CLK, one output data terminal Q, and one output data terminal QN when viewed from the outside.

The clock supplied to the clock terminal CLK is passed through the CMOS inverters 35 and 36 to be a clock CK, and is inverted by the CMOS inverter 35 to be a clock CKN.

First, when the clock CK is at a low level (hereinafter, referred to as
L), and at the same time, when the clock CKN becomes a high level (hereinafter referred to as H), in the clocked CMOS static latch circuit 31, the clocked CMOS inverter 311 is turned on and the clocked CMOS inverter 313 is turned off. Therefore, the data at the input data terminal D is written. On the other hand, in the clocked CMOS static latch circuit 32, since the clocked CMOS inverter 321 is turned off and the clocked CMOS inverter 323 is turned on, the flip-flop including the inverter 322 and the clocked CMOS inverter 323 controls the clocked CMOS inverter. The data previously captured from the static latch circuit 31 is held, and the previous data is output to the output Q.

Here, when the clock CK goes high and at the same time the clock CKN goes low, the clocked CMOS
In the static latch circuit 31, a clocked CMOS
The inverter 311 is turned off and the clocked CMOS
Since the inverter 313 is turned on, the written data is held by the flip-flop including the inverter 312 and the clocked CMOS inverter 313. On the other hand, in the clocked CMOS static latch circuit 32, the clocked CMOS inverter 321 is turned on.
And the clocked CMOS inverter 323 becomes OF
Since the state becomes F, the data held by the clocked CMOS static latch circuit 31 is fetched, and at the same time, the fetched data is read out to the output Q.

[0006]

This D flip-flop has four clocked CMOS inverters 311, 3
13, 321, 323 are the four MOs shown in FIG.
Each of the six CMOS inverters 35, 36, 312, 322, 33, and 34 is composed of two MOS transistors shown in FIG.
Since the entire flip-flop is composed of 28 (= 16 + 12) MOS transistors, the area occupied by the D flip-flop in the integrated circuit could not be reduced further.

An object of the present invention is to solve the above problems and provide a D flip-flop using a clocked CMOS inverter, which can reduce the area occupied in an integrated circuit. Is to do.

[0008]

SUMMARY OF THE INVENTION A two-input two-output clocked CMOS inverter according to the present invention comprises one P-MOS transistor and one N-MOS which are simultaneously turned on / off by two-phase clock pulses having opposite phases. Each of the transistors is a CMOS comprising one P-MOS transistor and one N-MOS transistor.
It is characterized in that it is connected between a circuit formed by connecting two inverters in parallel and two bias sources.

A D flip-flop according to the present invention is a D flip-flop in which two clocked CMOS static latch circuits each including two clocked CMOS inverters and one CMOS inverter are connected in series, and the four clocked CMOSs are provided. Of the inverter,
2. A two-input two-output clocked CMOS inverter according to claim 1, wherein clocked CMOS inverters that are turned on / off simultaneously in synchronization with two-phase clock pulses having a mutually opposite phase relationship are replaced with each other. .

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The configuration of the D flip-flop according to the present embodiment is different from that of the conventional D flip-flop in comparison. That is, in the conventional example, as shown in FIG.
Clocked CMOS inverters 311, 313, 3
21,323 and six CMOS inverters 35,36,
In the present embodiment, as shown in FIG. 1, two 2-input / 2-output clocked CMOS inverters 3 and 4 and 6 CMOS inverters 35, 36 and 312 are provided. , 322, 33, and 34. In FIG. 1, the same parts as those in FIG. 3 are denoted by the same reference numerals. That is, the D flip-flop according to the present embodiment is different from the clocked CMOS inverter 3 shown in FIG.
13 and 321 are replaced by a two-input two-output clocked CMOS inverter 3 and the clocked CMOS inverters 311 and 323 of FIG.

The configurations of the two-input two-output clocked CMOS inverters 3 and 4 are substantially the same, and as shown in FIG. 2, a circuit obtained by connecting CMOS inverters 21 and 22 in parallel, and A P-MOS transistor 23 as a switch element is connected between the power supply and the power supply,
NM as a switch element between this circuit and ground
The OS transistor 24 is connected.

Next, the operation of the two-input two-output clocked CMOS inverters 3 and 4 will be described. When the clock C becomes H and the clock CN becomes L at the same time, the P-MOS transistor 23 and the N-MOS transistor 24 become conductive, so that the output X is output with the level of the input terminal A inverted and output. For Y, the level of the input terminal B is inverted and output. When the clock C becomes L and the clock CN becomes H at the same time, the P-MOS transistor 23 and the N-MOS transistor 24 become non-conductive, so that the outputs X and Y become high impedance.

Next, the operation of the D flip-flop shown in FIG. 1 will be described. The clock supplied to the clock terminal CLK is passed through the CMOS inverters 35 and 36 to become the clock CK, and is inverted by the CMOS inverter 35 to become the clock CKN.

First, the clock CK goes low, and at the same time,
When the clock CKN becomes H, the two-input two-output clocked CMOS inverter 4 is turned on and the two-input two-output clocked CMOS inverter 3 is turned off. The data is written, while the clocked CMOS static latch circuit at the subsequent stage
And a flip-flop comprising a two-input two-output clocked CMOS inverter 4 retains previously captured data and outputs the previous data to an output Q.

Here, when the clock CK goes high and at the same time the clock CKN goes low, the two-input two-output clocked CMOS inverter 4 turns off and the two-input two-output clocked CMOS inverter 3 turns on. ,
The clocked CMOS static latch circuit in the preceding stage holds the written data by a flip-flop including an inverter 312 and a 2-input / 2-output clocked CMOS inverter 3. On the other hand, clocked CMO
When the S inverter 321 is turned ON, the clocked CMO
Since the S inverter 323 is turned off, the clocked CMOS static latch circuit at the subsequent stage captures the data held by the clocked CMOS static latch circuit at the previous stage, and reads out the captured data to the output Q.

In this embodiment, an example has been described in which a two-input two-output clocked CMOS inverter is used as a component of the D flip-flop.
MOS inverters can be used as one of a limited type of basic gates in a gate array, since the gate array is intended to simplify design with a regular structure.

The D flip-flop operable as described above comprises two 2-input 2-output clocked CMOS inverters 3 and 4 each composed of six MOS transistors shown in FIG. 2 and six CMOS inverters 35 and 36. , 31
2, 322, 33, and 34 are two Ms shown in FIG.
Since the D flip-flop was constituted by OS transistors, the entire D flip-flop could be constituted by 24 (= 12 + 12) MOS transistors.

On the other hand, the conventional D flip-flop is constituted by 28 MOS transistors as described above.

Therefore, the D flip-flop according to the present embodiment can reduce four MOS transistors as compared with the conventional D flip-flop, and therefore, the area occupied by the D flip-flop in the integrated circuit can be reduced. Could be smaller.

[0021]

As described above, according to the present invention,
With the above configuration, the area occupied by the D flip-flop in the integrated circuit can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a two-input two-output clocked CMOS inverter 3, 4 in FIG.

FIG. 3 is a block diagram illustrating an example of a configuration of a conventional D flip-flop.

4 is a clocked MOS inverter 311, 3 of FIG.
It is a circuit diagram which shows an example of a structure of 13,321,323.

FIG. 5 shows the CMOS inverters 35, 36, 31 of FIG.
FIG. 2 is a circuit diagram showing a configuration of the circuits 2,322,33,34.

[Explanation of symbols]

3,42 2-input 2-output clocked CMOS inverter 33,34,35,36,312,322 CMOS inverter

Claims (2)

[Claims] 1. One P-MOS transistor and one N-MOS transistor, which are simultaneously turned on / off by two-phase clock pulses having opposite phases, are replaced with one P-MOS transistor and one N-MO transistor, respectively.
A two-input, two-output clocked C, which is connected between a circuit formed by connecting two CMOS inverters formed of S transistors in parallel and two bias sources.
MOS inverter. 2. A clocked CM comprising two clocked CMOS inverters and one CMOS inverter
In a D flip-flop in which two OS static latch circuits are connected in series, a clocked CMOS inverter which is turned on / off simultaneously in synchronization with a two-phase clock pulse having an opposite phase relationship among the four clocked CMOS inverters A D flip-flop, wherein each of the D flip-flops is replaced with the two-input two-output clocked CMOS inverter according to claim 1.