TWI667884B - Clock circuit and method of operating the same - Google Patents

Abstract

Embodiments of the present invention provide a clock circuit including a first latch, a second latch, a first trigger circuit, and a clock trigger circuit. The first latch generates a first latched output signal based on the first control signal, the enable signal, and the output clock signal. The second latch is coupled to the first latch and configured to generate an output clock signal in response to the second control signal. The first trigger circuit is coupled to the first latch and the second latch and configured to adjust the output clock signal in response to at least the first latch output signal or the reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by the first node, configured to generate the first control signal in response to the input clock signal, and configured to be based on at least the first control The first latch and the first trigger circuit are controlled by signals.

Description

Clock circuit and method of operating same

Embodiments of the present invention relate to a clock circuit and an operation method thereof.

The semiconductor integrated circuit (IC) industry has produced a variety of digital devices to solve problems in multiple different regions. Some of these digital devices, such as clock circuits, are configured to generate one or more clock signals. As ICs become smaller and more complex, the operating voltages of these digital devices continue to decrease, affecting IC performance.

Some embodiments of the present application provide a clock circuit including: a first latch configured to generate a first latch output signal based on a first control signal, an enable signal, and an output clock signal; a second latch The first latch is coupled to the first latch and configured to generate the output clock signal in response to the second control signal; the first trigger circuit is coupled to the first latch and the The second latch is configured to adjust the output clock signal at least in response to the first latched output signal or the reset signal; and the clock trigger circuit is coupled to the first node by the first node The first latch and the first trigger circuit are configured to generate the response in response to inputting a clock signal a first control signal and configured to control the first latch and the first trigger circuit based at least on the first control signal.

In addition, other embodiments of the present application provide a clock circuit including: a first latch configured to generate a first latch output signal based on a first control signal, an enable signal, and an output clock signal; a latch coupled to the first latch and configured to generate the output clock signal in response to the second control signal; a first trigger circuit coupled to the first latch And the second latch, and configured to adjust the output clock signal at least in response to the first latch output signal or the reset signal; the clock trigger circuit coupled by the first node Up to the first latch and the first trigger circuit configured to generate the first control signal in response to a first clock signal having a first voltage swing, and configured to be based at least on Controlling the first latch and the first trigger circuit; and the level shifter circuit coupled to the clock trigger circuit at least, and configured to generate a second clock signal of the two voltage swings, the second voltage Moving said first clock signal is different from the first voltage swing.

In addition, another embodiment of the present application provides a method for operating a clock circuit, the method comprising: receiving a first clock signal by a clock trigger circuit; and converting to a first voltage in response to an enable signal from a second voltage level Leveling the first latch output signal from the first voltage level to the second voltage level by a first latch, the second voltage level being different from the first voltage level In response to the first clock signal transitioning from the first voltage level to the second voltage level, causing the clock trigger circuit to pull the first node from the first voltage level to The pulling of the first node by the second voltage level thereby causing the first control signal of the clock trigger circuit to transition from the first voltage level to the second voltage level, The clock trigger circuit is connected to the input end of the first latch and the first trigger circuit by the first node, and the first control signal from the clock trigger circuit is from the first node Feedback back to the input of the first latch; and in response to the first clock signal transitioning to the second voltage level and in response to the first latched output signal transitioning to the The second voltage level is used by the first trigger circuit to cause the output clock signal to transition from the second voltage level to the first voltage level.

100‧‧‧ integrated circuit

101, 200, 400, 500, 800‧‧‧ clock circuits

102, 201A‧‧‧Latch circuit

104‧‧‧SRAM status circuit

106, 201C‧‧‧SRAM state trigger circuit

108, 201D, 801D‧‧‧SRAM state latch circuit

110, 201B‧‧‧ clock trigger circuit

112‧‧‧SRAM circuit

116‧‧‧Latch control circuit

120‧‧‧Output terminal

122‧‧‧Feedback path

202, 228, 602, 616‧‧ ‧ inverter

204‧‧‧"or" gate

206‧‧‧"Reverse" gate

208‧‧‧"Anti-or" gate

210, 214, 222, 226, 502, 604, 614‧‧‧ NMOS transistors

212, 216, 218, 220, 224, 402, 504, 506, 510, 512, 520, 606, 608, 610, 612, 802 ‧ ‧ PMOS transistors

300, 700‧‧‧ Timing Chart

600‧‧‧bit shift circuit

900‧‧‧ method

902, 904, 906, 908, 910, 912, 914, 916, 916, 918, 920, 922, 924‧‧‧ operations

CEB, CKPB, CKPBI, CKPI, CLK, CLKB, CLKB1, CLK_EN, CLK_ENB, CLK_LS, CLK_LSB, RSTCKB‧‧‧ signals

N1, N2, N3, N4, N5, 6-N1, 6-N2‧‧‧ nodes

Nout‧‧‧ output terminal

T0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, t19, t20‧‧

VDD, VDDM‧‧‧ supply voltage

The aspects of the present disclosure will be best understood from the following detailed description. It should be noted that various features are not drawn to scale according to standard practice in the art. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

1 is a block diagram of a clock circuit in accordance with some embodiments.

2 is a circuit diagram of a clock circuit in accordance with some embodiments.

3 is a timing diagram of various signals of a clock circuit in accordance with some embodiments.

4 is a circuit diagram of a clock circuit in accordance with some embodiments.

FIG. 5 is a timing diagram of various signals of a clock circuit in accordance with some embodiments.

6 is a circuit diagram of a level shifter circuit in accordance with some embodiments.

7 is a timing diagram of various signals of a clock circuit in accordance with some embodiments.

8 is a circuit diagram of a clock circuit in accordance with some embodiments.

9A-9B are flow diagrams of a method of operating a clock circuit, such as the clock circuit of FIG. 1, FIG. 2, FIG. 4, FIG. 5, or FIG. 8, in accordance with some embodiments.

The following disclosure provides different embodiments or examples for implementing the features of the subject matter provided. Specific examples of components, materials, values, steps, configurations, etc. are described below to simplify the disclosure. Of course, these are examples only and are not limiting. Covers other components, materials, values, steps, configurations, and more. For example, in the following description, the formation of the first feature above or over the second feature may comprise an embodiment in which the first feature and the second feature are formed in direct contact, and may also include additional features at the first feature and The second features are formed such that the first feature and the second feature may not be in direct contact with the embodiment. In addition, the present disclosure may repeat reference numerals and/or letters in various examples. This repetition is for the purpose of simplification and clarity, and is not intended to indicate the relationship between the various embodiments and/or configurations discussed.

In addition, spatial relative terms such as "below", "below", "lower", "above", "upper", and the like can be used in this article to facilitate description. The relationship of one element or feature to another element or feature is shown in the drawings. In addition to the orientation depicted in the drawings, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly accordingly.

According to some embodiments, the clock circuit includes a first latch, a second latch, a first trigger circuit, and a clock trigger circuit. The first latch is configured to generate a first latched output signal based on the first control signal, the enable signal, and the output clock signal. The second latch is coupled to the first latch and configured to generate an output clock signal in response to the second control signal. The first trigger circuit is coupled to the first latch and the second And a latch configured to adjust the output clock signal in response to at least the first latched output signal or the reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by the first node, configured to generate the first control signal in response to the input clock signal, and configured to be based on at least the first control The first latch and the first trigger circuit are controlled by signals.

In some embodiments, each of the first latch and the first trigger circuit is controlled by using a clock trigger circuit, each of which is controlled by a single clock enable path. By controlling the first latch and the first trigger circuit using a single clock enable path, the clock circuit of the present disclosure is less susceptible to process, voltage, and temperature (PVT) than other methods. In some embodiments, by using a clock trigger circuit to control each of the first latch circuit and the first trigger circuit, the clock circuit of the present disclosure changes in a larger PVT than other methods. There is no race under the scope (race free). In some embodiments, by using a clock trigger circuit to control each of the first latch and the first trigger circuit, the clock circuit of the present disclosure changes the clock swing compared to other methods. Better resistance. In some embodiments, the clock circuit of the present disclosure has a larger operating voltage range than other methods by using a clock trigger circuit with a level shifter circuit.

Clock circuit

FIG. 1 is a block diagram of an integrated circuit 100 in accordance with some embodiments. In the embodiment of FIG. 1, the integrated circuit 100 is a static random access memory (SRAM) macro. SRAM is used as an example, and other types of memory are within the scope of various embodiments.

The integrated circuit 100 includes a clock circuit 101 connected to the SRAM circuit 112. The clock circuit 101 is configured to receive the signal CLK and the signal CEB and output the signal CKPB to the SRAM circuit 112 at the output terminal 120. The clock circuit 101 is configured to generate a signal CKPB based on the signal CLK and the signal CEB. Signal CKPB is the generated clock signal that can be used by SRAM circuit 112.

The signal CLK is an internal clock signal of the integrated circuit 100. The signal CEB is a chip enable bar (CEB) signal that indicates that the SRAM circuit 112 is in an active or inactive state. In some embodiments, the CEB signal is logic high when the SRAM circuit 112 is inactive, and the CEB signal is logic low when the SRAM circuit 112 is active.

SRAM circuit 112 is configured to receive signal CKPB. SRAM circuit 112 is configured to store data, read data, or retain data based on signal CKPB. In some embodiments, signal CKPB can be used by SRAM circuit 112 as a clock signal indicative of the state of SRAM circuit 112. In some embodiments, the state of SRAM circuit 112 includes one or more of a write state, a read state, or a standby state. SRAM is used for the example of SRAM circuit 112, and other types of memory for circuit 112 are within the scope of various embodiments.

The clock circuit 101 includes a latch circuit 102, an SRAM state circuit 104, and a clock trigger circuit 110.

The latch circuit 102 is coupled to the SRAM state circuit 104 and the clock trigger circuit 110. The latch circuit 102 is configured to receive the signal CLKB, the signal CKPB, and the signal CEB.

The latch circuit 102 is configured to generate a signal CLK_EN in response to the signal CLKB, the signal CKPB, and the signal CEB. The latch circuit 102 is configured to latch or store the state of the signal CEB, and thus the latch circuit 102 is referred to as a CEB latch. road. In some embodiments, latch circuit 102 is configured to be reset by signal CKPB. The signal CLK_EN is an enable clock signal that controls the SRAM state circuit 104. The signal CLKB is a trigger signal generated by the clock trigger circuit 110. In some embodiments, signal CLKB is an inverted clock signal (eg, signal CLK).

The SRAM state circuit 104 is coupled to the latch circuit 102, the clock trigger circuit 110, and the SRAM circuit 112. The SRAM state circuit 104 is configured to receive the signal CLK_EN, the signal CLKB, and the signal RSTCKB. The SRAM state circuit 104 is configured to latch or store the state of the signal CKPB. The signal RSTCKB is a reset signal. In some embodiments, SRAM state circuit 104 is configured to be reset by signal RSTCKB. In some embodiments, signal RSTCKB is triggered to change the logic state based on tracking bit line signals (not shown). SRAM state circuit 104 is configured to generate signal CKPB. SRAM state circuit 104 is configured to output signal CKPB to latch circuit 102 by being coupled to latch circuit 102 via feedback path 122.

The SRAM state circuit 104 includes an SRAM state trigger circuit 106 and an SRAM state latch circuit 108.

The SRAM state trigger circuit 106 is coupled to the latch circuit 102, the SRAM state latch circuit 108, and the clock trigger circuit 110. The SRAM state trigger circuit 106 is configured to receive the signal CLK_EN, the signal CLKB, and the signal RSTCKB. In some embodiments, SRAM state trigger circuit 106 is configured to control the state of SRAM state latch circuit 108 by at least signal RSTCKB, signal CLKB, or signal CLK_EN.

The SRAM state latch circuit 108 is coupled to the latch circuit 102 via the feedback path 122 and coupled to the SRAM state trigger circuit 106. In some embodiments, SRAM state trigger circuit 106 is part of SRAM state latch circuit 108, and vice versa. The SRAM state latch circuit 108 is configured to generate a clock signal CKPB based at least on the signal RSTCKB, the signal CLKB, or the signal CLK_EN. The SRAM state latch circuit 108 is configured to latch or store the state of the signal CKPB. In some embodiments, SRAM state latch circuit 108 is reset by signal RSTCKB.

The clock trigger circuit 110 is coupled to the SRAM state trigger circuit 106 and the latch circuit 102. The clock trigger circuit 110 is configured to receive the signal CLK. The clock trigger circuit 110 is configured to generate a signal CLKB in response to the signal CLK. The clock trigger circuit 110 is configured to control each of the latch circuit 102 and the SRAM state trigger circuit 106 by a single trigger signal (e.g., signal CLKB). The clock trigger circuit 110 is a single trigger circuit as compared to other methods using a separate trigger circuit.

In some embodiments, each of latch circuit 102 and SRAM state trigger circuit 106 is subjected to a single trigger circuit as compared to other methods of controlling a corresponding latch circuit using a separate trigger circuit that generates a corresponding separate trigger signal. (eg, clock trigger circuit 110) and a corresponding single trigger signal (eg, signal CLKB) control.

In some embodiments, by using the clock trigger circuit 110 to control each of the latch control circuit 116 and the SRAM state trigger circuit 106 by a single signal, the clock circuit 101 is less susceptible than other methods. Affected by changes in PVT. In some embodiments, clock circuit 101 is compared to other methods by being more susceptible to PVT variations and using clock trigger circuit 110 to control each of latch control circuit 116 and SRAM state trigger circuit 106. There is no competition for a larger range of PVT variations. In some embodiments, by being less susceptible to PVT changes Influence, and by using the clock trigger circuit 110 to control each of the latch control circuit 116 and the SRAM state trigger circuit 106, the clock circuit 101 is more resistant to clock swing variations than other methods. Sex. In some embodiments, the clock circuit 101 is compared to each of the latch control circuit 116 and the SRAM state trigger circuit 106 by being more susceptible to PVT variations and by using the clock trigger circuit 110. Other methods have a larger operating voltage range.

2 is a circuit diagram of a clock circuit 200 in accordance with some embodiments.

The clock circuit 200 is an embodiment of the clock circuit 101 of FIG. Components that are the same as or similar to those of one or more of FIG. 1 and FIGS. 3 to 9 (shown below) are given the same reference numerals, and thus detailed description thereof is omitted.

The clock circuit 200 includes a latch circuit 201A, a clock trigger circuit 201B, an SRAM state trigger circuit 201C, an SRAM state latch circuit 201D, and an inverter 202.

The latch circuit 201A is one embodiment of the latch circuit 102 of FIG. 1, and a similar detailed description is omitted. The clock trigger circuit 201B is one embodiment of the clock trigger circuit 110 of FIG. 1, and a similar detailed description is omitted. The SRAM state trigger circuit 201C is one embodiment of the SRAM state trigger circuit 106 of FIG. 1, and a similar detailed description is omitted. The SRAM state latch circuit 201D is one embodiment of the SRAM state latch circuit 108 of FIG. 1, and a similar detailed description is omitted.

The inverter 202 is connected between the latch circuit 201A and the SRAM state latch circuit 201D. The input terminal of inverter 202 is configured to receive signal CKPI. The output terminal of inverter 202 is configured to output signal CKPBI. In some embodiments, the signal CKPBI is an inverted version of the signal CKPI. Inverter 202 is configured to generate signal CKPBI based on signal CKPI.

The latch circuit 201A includes an "OR" gate 204, a "NAND" gate 206, and a "NOR" gate 208.

The first input terminal of OR gate 204 is configured to receive signal CLKB. The first input terminal of the OR gate 204, the NMOS terminal of the NMOS transistor 210, the NMOS terminal of the PMOS transistor 212, and the source terminal of the NMOS transistor 214 are coupled to each other at the node N1. The signal CLKB is the voltage of the node N1.

The second input terminal of the OR gate 204 is configured to receive the signal CLK_EN. The second input terminal of the OR gate 204, the output terminal of the "reverse OR" gate 208, and the gate terminal of the NMOS transistor 214 are coupled to each other at the node N2. The signal CLK_EN is the voltage of the node N2.

The output terminal of the OR gate 204 is configured to output an OR signal (not labeled). The OR gate 204 is configured to generate an OR signal (not labeled) based on the signal CLK_EN and the signal CLKB.

The first input terminal of the "reverse" gate 206 is directly coupled to the output terminal of the OR gate 204. The first input terminal of the "reverse" gate 206 is configured to receive an "OR" output signal (not labeled) from the OR gate 204. The second input terminal of the "reverse" gate 206 is directly coupled to the output terminal of the inverter 202. The second input terminal of the "reverse" gate 206 is configured to receive the signal CKPBI. The output terminal of the "reverse" gate 206 is configured to output a signal CLK_ENB. The "Reverse" gate 206 is configured to generate a signal CLK_ENB based on the signal CKPBI and the OR signal (not labeled).

The first input terminal of the "OR" gate 208 is configured to receive the signal CEB. The second input terminal of the "OR" gate 208 is configured to receive the signal CLK_ENB. The second input terminal of the "reverse" gate 208 is directly coupled to the output of the "reverse" gate 206. child. The output terminal of the "OR" gate 208 is configured to output the signal CLK_EN to node N2. The "reverse" gate 208 is configured to set the voltage at node N2. The voltage at node N2 is the signal CLK_EN. The "OR" gate 208 is configured to generate a signal CLK_EN based on the signal CEB and the signal CLK_ENB. Other logic gate configurations, logic gate numbers, or logic gate types of the clock circuit 200 are within the scope of the present disclosure.

The clock trigger circuit 201B includes an NMOS transistor 210 and a PMOS transistor 212.

The gate terminal of NMOS transistor 210 is configured to receive a clock signal CLK. The NMOS transistor 210 is turned on or off based on the signal CLK. The source terminal of the NMOS transistor 210 is coupled to a supply reference voltage VSS.

The gate terminal of PMOS transistor 212 is configured to receive a clock signal CLK. The PMOS transistor 212 is turned on or off based on the signal CLK. The source terminal of the PMOS transistor 212 is coupled to the supply voltage VDD. NMOS transistor 210, together with PMOS transistor 212, acts as an inverter configured to set the voltage at node N1. The voltage at node N1 is signal CLKB.

The SRAM state trigger circuit 201C includes an NMOS transistor 214, a PMOS transistor 216, a PMOS transistor 218, a PMOS transistor 220, and an NMOS transistor 222.

The gate terminal of NMOS transistor 214 is configured to receive signal CLK_EN from "reverse OR" gate 208. NMOS transistor 214 is controlled by "reverse OR" gate 208 and is turned "on" or "off" based on signal CLK_EN. The source terminal of the NMOS transistor 214 is coupled to at least the node N1. The NMOS terminal of the NMOS transistor 214, the 汲 terminal of the PMOS transistor 216, the 汲 terminal of the PMOS transistor 218, and the PMOS transistor The 汲 terminal of the body 220, the 汲 terminal of the NMOS transistor 222, and the input terminal of the inverter 228 are coupled to each other at the node N3.

The gate terminal of the PMOS transistor 216 is coupled to the gate terminal of the NMOS transistor 210. The gate terminal of PMOS transistor 216 is configured to receive clock signal CLK. The PMOS transistor 216 is turned on or off based on the signal CLK. In some embodiments, each of the gate terminal of PMOS transistor 216, the gate terminal of PMOS transistor 212, and the gate terminal of NMOS transistor 210 are coupled together. The source terminal of PMOS transistor 216, the source terminal of PMOS transistor 218, and the NMOS terminal of PMOS transistor 224 are coupled to each other at node N4.

The gate terminal of PMOS transistor 218 is configured to receive signal CLK_EN. The PMOS transistor 218 is turned on or off based on the signal CLK_EN. In some embodiments, the gate terminal of PMOS transistor 218 is coupled to node N2. In some embodiments, the gate terminal of PMOS transistor 218, the gate terminal of NMOS transistor 214, the output terminal of "reverse" gate 208, and the second input terminal of OR gate 204 are Nodes N2 are coupled to each other.

The gate terminal of PMOS transistor 220 is configured to receive signal RSTCKB. The PMOS transistor 220 is turned on or off based on the signal RSTCKB. The source terminal of the PMOS transistor 220 is coupled to the supply voltage VDD.

The gate terminal of the NMOS transistor 222 is coupled to the gate terminal of the PMOS transistor 220. The gate terminal of NMOS transistor 222 is configured to receive signal RSTCKB. The NMOS transistor 222 is turned on or off based on the signal RSTCKB. The source terminal of the NMOS transistor 222 is coupled to the NMOS terminal of the NMOS transistor 226. The 汲 terminal of the NMOS transistor 222 and the 汲 terminal of the PMOS transistor 220 Sub-coupled. PMOS transistor 220, together with NMOS transistor 222, acts as an inverter that is configured to set the voltage at node N3. The voltage at node N3 is the signal CKPB. In some embodiments, node N3 corresponds to output terminal Nout of clock circuit 200. In some embodiments, by positioning the PMOS transistor 220 in the current position, when the PMOS transistor 220 and the NMOS transistor 222 are turned on or off, the node N3 is caused to float, thereby generating a dynamic logic type clock circuit ( Dynamic logic type clock circuit).

The SRAM state latch circuit 201D includes a PMOS transistor 224, an NMOS transistor 226, and an inverter 228.

The gate terminal of PMOS transistor 224 is configured to receive signal CKPI from inverter 228. The PMOS transistor 224 is turned on or off based on the signal CKPI. In some embodiments, the gate terminal of PMOS transistor 224 is coupled to each of a gate terminal of NMOS transistor 226, an output terminal of inverter 228, and an input terminal of inverter 202. The source terminal of the PMOS transistor 224 is coupled to the supply voltage VDD. The 汲 terminal of the PMOS transistor 224 is coupled to at least the node N4.

Each of the gate terminal of the NMOS transistor 226, the output terminal of the inverter 228, and the input terminal of the inverter 202 is coupled to each other at the node N5. The voltage of the node N5 is the signal CKPI. The NMOS transistor 226 is turned on or off based on the signal CKPI. The source terminal of the NMOS transistor 226 is coupled to the supply reference voltage VSS.

The input terminal of inverter 228 is configured to receive signal CKPB. The output terminal of inverter 228 is configured to output signal CKPI. In some embodiments, the signal CKPI is an inverted version of the signal CKPB. Inverter 228 is configured to generate signal CKPI based on signal CKPB. Inverter 228 is configured to be set by signal CKPI Set the voltage of node N5. In some embodiments, signal CKPI corresponds to a feedback signal that is fed back to PMOS transistor 224 of SRAM state latch circuit 201D. Other transistor configurations, transistor numbers, or transistor types of the clock circuit 200 are within the scope of the present disclosure.

Waveform

3 is a timing diagram 300 of a waveform of a clock circuit, such as clock circuit 200 of FIG. 2 or clock circuit 400 of FIG. 4, in accordance with some embodiments.

At time t0, signal CEB transitions from logic high to logic low, and signal CLK_ENB is logic low.

At time t1, signal CEB is logic low.

At time t2, in response to signal CEB transitioning to logic low and signal CLK_ENB being logic low, signal CLK_EN generated by "reverse" gate 208 transitions from logic low to logic high. In response to the signal CLK_EN transitioning from logic low to logic high, the NMOS transistor 214 is turned "on", thereby connecting the node N3 to the node N1, and the PMOS transistor 218 is turned off, thereby disconnecting the node N3 from the node N4. In some embodiments, signal CLK_EN corresponds to the stored or latched state of signal CEB of CEB latch circuit 201A.

At time t3, signal CLK_EN is logic high and signal CLK transitions from logic low to logic high.

At time t4, signal CLK is logic high, signal CLKB transitions from logic high to logic low, and signal CKPB transitions from logic high to logic low.

In response to signal CLK being logic high, NMOS transistor 210 is turned "on" and PMOS transistor 212 and PMOS transistor 216 are turned "off". By making NMOS Crystal 210 is turned "on", pulling node N1 to VSS and causing signal CLKB to transition from logic high to logic low. However, since node N1 is connected to node N3 via NMOS transistor 214, node N3 is also pulled to VSS by turning NMOS transistor 210 on, causing signal CKPB to transition from logic high to logic low.

At time t5, signal CLKB is logic low and signal CKPB is logic low. In response to signal CKPB being logic low, signal CKPI transitions from logic low to logic high by inverter 228.

At time t6, signal CKPI is logic high and signal CLK_ENB transitions from logic low to logic high. In response to the signal CKPB being logic low, the inverter 228 causes the signal CKPI to be logic high by inverting the signal CKPB, thereby turning the NMOS transistor 226 on. However, the NMOS transistor 222 has been turned on by the logic high signal RSTCKB. Therefore, by turning on the NMOS transistor 226, the NMOS transistor 226 and the NMOS transistor 222 boost the signal CKPB to maintain a logic low, thereby enhancing the signal CKPI to become a logic high.

At time t7, the signal CLK_EN transitions to a logic high, causing the signal CLK_EN to transition from a logic high to a logic low. In other words, the "anti-OR" gate 208 outputs a logic low signal (CLK_EN) in response to the signal CLK_ENB transitioning to logic high and the signal CEB being logic low.

At time t8, signal CLK_EN is logic low. In response to signal CLK_EN being logic low, NMOS transistor 214 is turned off, thereby disconnecting node N3 from node N1, and PMOS transistor 218 is turned "on", thereby connecting node N3 to node N4.

At time t9, the signal CEB transitions from a logic low to a logic high.

At time t10, signal CLK transitions from a logic high to a logic low. In response to the signal CLK transitioning from logic high to logic low, the NMOS transistor 210 begins to turn off. And the PMOS transistor 212 and the PMOS transistor 216 start to turn on.

At time t11, signal CLK is logic low, signal CEB is logic high, and signal CLKB transitions from logic low to logic high. In response to signal CLK being logic low, NMOS transistor 210 is turned off and PMOS transistor 212 and PMOS transistor 216 are turned "on". By turning PMOS transistor 212 on, node N1 is pulled toward supply voltage VDD and signal CLKB transitions from logic low to logic high. Switched on by PMOS transistor 216, node N3 is coupled to node N4 via PMOS transistor 216.

At time t12, the signal RSTCKB transitions from a logic high to a logic low. In response to the signal RSTCKB transitioning from logic high to logic low, NMOS transistor 222 begins to turn off and PMOS transistor 220 begins to turn "on".

At time t13, signal RSTCKB is logic low, signal CLKB is logic high, and signal CKPB transitions from logic low to logic high. In response to signal RSTCKB being logic low, NMOS transistor 222 is turned off, thereby causing NMOS transistor 226 to be disconnected from node N3 via NMOS transistor 222. In response to the signal RSTCKB being logic low, the PMOS transistor 220 is turned on, pulling the node N3 toward the supply voltage VDD, thereby causing the signal CKPB to transition from a logic low to a logic high. In other words, the SRAM state latch circuit 201D is reset to logic high by the signal RSTCKB.

At time t14, signal CKPB is logic high.

At time t15, in response to signal CKPB being logic high at time t14, inverter 228 causes signal CKPI to transition from logic high to logic low by inverting signal CKPB.

At time t16, signal CKPI is logic low and signal CLK_ENB transitions from logic high to logic low. In response to signal CKPI being logic low, PMOS transistor 224 is turned "on" and NMOS transistor 226 is turned "off". By making PMOS transistor 224 Turned on, node N4 is pulled toward supply voltage VDD. However, node N4 is coupled to node N3 via PMOS transistor 218 and PMOS transistor 216. Therefore, in addition to the PMOS transistor 220, the PMOS transistor 224 pulls the node N3 toward the supply voltage VDD. In other words, PMOS transistor 224 boosts signal CKPB to maintain a logic high.

At time t17, signal CLK_ENB is logic low, and signal RSTCKB transitions from logic low to logic high in response to signal CKPI being logic low. By transitioning the signal RSTCKB from logic low to logic high, the PMOS transistor 220 is turned off and the NMOS transistor 222 is turned "on". However, node N3 and signal CKPB are maintained at supply voltage VDD via one or more of PMOS transistor 216, PMOS transistor 218, and PMOS transistor 224, and NMOS transistor 226 is turned off and node N3 is not pulled toward VSS. .

At time t18, signal RSTCKB is logic high and signal CKPB is logic high.

Clock circuit

FIG. 4 is a circuit diagram of a clock circuit 400 in accordance with some embodiments.

The clock circuit 400 is a variation of the clock circuit 200 of FIG. 2, and thus a similar detailed description is omitted.

In some embodiments, clock circuit 400 is a static clock generation circuit. Clock circuit 400 is one embodiment of clock circuit 101 of FIG.

The PMOS transistor 402 of the clock circuit 400 replaces the PMOS transistor 220 at a different location than the clock circuit 200 of FIG. In other words, PMOS transistor 402 is similar to PMOS transistor 220, but is positioned in different locations. For example, PMOS transistor 402 is coupled in parallel with PMOS transistor 224 between supply voltage VDD and node N4. By locating the PMOS transistor 402 to couple to the section The point N4 is such that the node N3 does not float when the PMOS transistor 402 and the NMOS transistor 222 are turned on or off, thereby generating a static logic type clock circuit.

The gate terminal of PMOS transistor 402 is configured to receive signal RSTCKB. The PMOS transistor 402 is turned on or off based on the signal RSTCKB. In some embodiments, the gate of PMOS transistor 402 is coupled to the gate of NMOS transistor 222. The source terminal of the PMOS transistor 402 is coupled to the supply voltage VDD. In some embodiments, the source terminal of PMOS transistor 402 is coupled to the source terminal of PMOS transistor 224.

The NMOS terminal of the PMOS transistor 402, the source terminal of the PMOS transistor 216, the source terminal of the PMOS transistor 218, and the NMOS terminal of the PMOS transistor 224 are coupled to each other at the node N4.

By not including the PMOS transistor 220, the node N3 of the clock circuit 400 is not pulled to the supply voltage VDD based only on the signal RSTCKB. For example, the PMOS transistor 402 is coupled to the node N3 by the PMOS transistor 218 or the PMOS transistor 216 driven by the corresponding signal CLK_EN or signal CLK. Thus, PMOS transistor 402 and PMOS transistor 218 or PMOS transistor 216 are configured to pull node N3 toward supply voltage VDD based on signal RSTCKB and signal CLK_EN or signal CLK, respectively.

The timing diagram 300 of the waveform is applied to the clock circuit 200 and the clock circuit 400 of FIG. 2, and thus a similar detailed description is omitted. However, some operations of the PMOS transistor 402 are different from the PMOS transistor 220, and thus are described below. For the sake of brevity, a detailed description of similar operations of the clock circuit 400 and the clock circuit 200 is thus omitted.

At time t12, the signal RSTCKB transitions from a logic high to a logic low. In response to signal RSTCKB transitioning from logic high to logic low, NMOS transistor 222 begins to turn off and PMOS transistor 402 begins to turn "on".

At time t13, signal RSTCKB is logic low, signal CLKB is logic high, and signal CKPB transitions from logic low to logic high. In response to signal RSTCKB being logic low, NMOS transistor 222 is turned off, thereby causing NMOS transistor 226 to be disconnected from node N3 via NMOS transistor 222. In response to signal RSTCKB being logic low, PMOS transistor 402 is turned "on", thereby connecting node N4 to node N3 via PMOS transistor 216 and PMOS transistor 218. Thus, PMOS transistor 402 pulls node N3 to supply voltage VDD via node N4, thereby causing signal CKPB to transition from a logic low to a logic high. In other words, the SRAM state latch circuit is reset to logic high by the signal RSTCKB.

At time t14, signal CKPB is logic high.

At time t15, in response to signal CKPB being logic high at time t14, inverter 228 causes signal CKPI to transition from logic high to logic low by inverting signal CKPB.

At time t16, signal CKPI is logic low and signal CLK_ENB transitions from logic high to logic low. In response to signal CKPI being logic low, PMOS transistor 224 is turned "on" and NMOS transistor 226 is turned "off". By turning PMOS transistor 224 on, PMOS transistor 224 also pulls node N4 toward supply voltage VDD. Thus, an additional path to pull node N4 and node N3 toward supply voltage VDD is generated by turning on PMOS transistor 224. In other words, PMOS transistor 224 boosts signal CKPB to maintain a logic high.

At time t17, the signal CLK_ENB is logic low and the signal RSTCKB In response to the signal CKPI is logic low and transitions from logic low to logic high. By transitioning the signal RSTCKB from logic low to logic high, the PMOS transistor 402 is turned off and the NMOS transistor 222 is turned "on". However, node N3 and signal CKPB are maintained at supply voltage VDD via one or more of PMOS transistor 216, PMOS transistor 218, and PMOS transistor 224, and NMOS transistor 226 is turned off and node N3 is not pulled toward VSS. .

At time t18, signal RSTCKB is logic high and signal CKPB is logic high.

FIG. 5 is a circuit diagram of a clock circuit 500 in accordance with some embodiments.

The clock circuit 500 is implemented using a dual-rail circuit having two different voltage domains (eg, signal CLK and signal CLK_LS). For example, in some embodiments, the signal CLK is a clock signal having a low voltage domain, and the signal CLK_LS is a clock signal having a high voltage domain. In some embodiments, the clock circuit 500 is further implemented with a clock level shifter (eg, level shifter circuit 600) for a dual rail memory design.

The clock circuit 500 is a variation of the clock circuit 200 of FIG. 2, and thus a similar detailed description is omitted. Compared with the clock circuit 200 of FIG. 2, the clock circuit 500 does not include the PMOS transistor 212, the PMOS transistor 224, and the PMOS transistor 220, but the clock circuit 500 further includes an NMOS transistor 502, a PMOS transistor 504, and a PMOS. The transistor 506, the PMOS transistor 510, the PMOS transistor 512, and the PMOS transistor 520. Clock circuit 500 is an embodiment of clock circuit 101 of FIG.

The gate terminal of NMOS transistor 502 is configured to receive signal CLK_LS. In some embodiments, the signal CLK_LS is generated by a level shifter circuit, The level shifter circuit is such as the level shifter circuit 600 of FIG. The NMOS transistor 502 is turned on or off based on the signal CLK_LS. The source terminal of the NMOS transistor 502 is coupled to the supply reference voltage VSS. The source terminal of the NMOS transistor 502 is coupled to the source terminal of the NMOS transistor 210. The NMOS terminal of the NMOS transistor 502, the 汲 terminal of the PMOS transistor 504, the 汲 terminal of the NMOS transistor 210, the source terminal of the NMOS transistor 214, and the first input terminal of the OR gate 204 The two are coupled to each other at node N1.

The gate terminal of PMOS transistor 504 is configured to receive signal CLK_LS. The PMOS transistor 504 is turned on or off based on the signal CLK_LS. The source terminal of the PMOS transistor 504 is coupled to the NMOS terminal of the PMOS transistor 506.

The gate terminal of PMOS transistor 506 is configured to receive signal CLK. The PMOS transistor 506 is turned on or off based on the signal CLK. The source terminal of the PMOS transistor 506 is coupled to the supply voltage VDDM. In some embodiments, the supply voltage VDDM is greater than the supply voltage VDD. In some embodiments, the supply voltage VDDM is less than the supply voltage VDD. In some embodiments, the supply voltage VDDM has a voltage swing in the range of VDDM to VSS. In some embodiments, the supply voltage VDD has a voltage swing in the range of VDD to VSS.

NMOS transistor 210, NMOS transistor 502, PMOS transistor 504, and PMOS transistor 506 are configured together to set the voltage at node N1. The voltage of node N1 corresponds to signal CLKB.

Compared with the clock circuit 200 of FIG. 2, the PMOS transistor 510 of FIG. 5 is inserted between the source terminal of the PMOS transistor 216 and the node N4, and thus the source terminal of the PMOS transistor 216 is not directly coupled to Node N4. PMOS The gate terminal of crystal 510 is configured to receive signal CLK_LS. The PMOS transistor 510 is turned on or off based on the signal CLK_LS. The NMOS terminal of PMOS transistor 510 is coupled to the source terminal of PMOS transistor 216. The source terminal of the PMOS transistor 510, the NMOS terminal of the PMOS transistor 512, and the source terminal of the PMOS transistor 218 are coupled to each other at the node N4.

The PMOS transistor 512 replaces the PMOS transistor 224 of the clock circuit 200 of FIG. The source terminal of the PMOS transistor 512 is coupled to the supply voltage VDDM. The gate terminal of PMOS transistor 512 is configured to receive signal CKPI. The PMOS transistor 512 is turned on or off based on the signal CKPI. In some embodiments, the gate terminal of PMOS transistor 512 is coupled to node N5.

The PMOS transistor 520 replaces the PMOS transistor 220 of the clock circuit 200 of FIG. The source terminal of the PMOS transistor 512 is coupled to the supply voltage VDDM. The gate terminal of PMOS transistor 520 is configured to receive signal RSTCKB. The PMOS transistor 520 is turned on or off based on the signal RSTCKB. The gate terminal of the PMOS transistor 520 is coupled to the gate terminal of the NMOS transistor 222. In some embodiments, the gate terminal of PMOS transistor 512 is coupled to node N5. The NMOS terminal of the PMOS transistor 520, the 汲 terminal of the NMOS transistor 214, the 汲 terminal of the PMOS transistor 216, the 汲 terminal of the PMOS transistor 218, the 汲 terminal of the NMOS transistor 222, and the inverter 228 Each of the input terminals are coupled together at node N3. In some embodiments, by positioning the PMOS transistor 520 in the current position, when the PMOS transistor 520 and the NMOS transistor 222 are turned "on" or "off", the node N3 is caused to float, thereby generating a dynamic logic type clock circuit.

In some embodiments, the clock circuit 500 has a larger operating voltage range than other methods by using the dual rail memory design of the clock circuit 500. Wai.

Level shifter circuit

FIG. 6 is a circuit diagram of a level shifter circuit 600 in accordance with some embodiments.

The level shifter circuit 600 can be used with one or more of the clock circuit 101 of FIG. 1, the clock circuit 500 of FIG. 5, or the clock circuit 800 of FIG. 8 (described below). For example, in some embodiments, the level shifter circuit 600 is coupled to the NMOS transistor 502, the PMOS transistor 504, and the PMOS transistor 510 of the clock circuit 500 or the clock circuit 800, and the level shift is The circuit 600 is configured to output the signal CLK_LS to the NMOS transistor 502 of the clock circuit 500 or the clock circuit 800, the PMOS transistor 504, and the PMOS transistor 510.

In some embodiments, the clock circuit 500 of FIG. 5 or the clock circuit 800 of FIG. 8 is further implemented with a clock level shifter (eg, level shifter circuit 600) for a dual track memory design. In some embodiments, the level shifter circuit 600 can be used to generate the signal CLK_LS (Figs. 5, 7, and 8).

The level shifter circuit 600 is a clock level shifter circuit configured to shift the clock signal from a low voltage domain using the supply voltage VDD to a high voltage domain using the supply voltage VDDM.

The level shifter circuit 600 is configured to receive the signal CLK on an input terminal (not labeled) and output a signal CLK_LS on an output terminal (not labeled). The signal CLK corresponds to the input signal of the level shifter circuit 600, and the signal CLK_LS corresponds to the output signal of the level shifter circuit 600. The level shifter circuit 600 is configured to generate a signal CLK_LS based on the signal CLK.

The signal CLK_LS corresponds to the level offset version of the signal CLK. In some embodiments, the voltage level of the signal CLK of the level shifter circuit 600 is less than the level. The voltage level of the signal CLK_LS of the offset circuit 600. In some embodiments, the voltage level of the signal CLK of the level shifter circuit 600 is greater than the voltage level of the signal CLK_LS of the level shifter circuit 600.

The level shifter circuit 600 includes an inverter 602, an NMOS transistor 604, a PMOS transistor 606, a PMOS transistor 608, a PMOS transistor 610, a PMOS transistor 612, an NMOS transistor 614, and an inverter 616.

The input terminal of inverter 602 is configured to receive signal CLK. Each of the input terminal of the inverter 602, the gate terminal of the PMOS transistor 606, and the gate terminal of the NMOS transistor 604 are coupled to each other. The output terminal of inverter 602 is configured to output signal CLKB1. In some embodiments, signal CLKB1 is an inverted version of signal CLK. Inverter 602 is configured to generate signal CLKB1 based on signal CKPI. In some embodiments, signal CLKB1 corresponds to signal CLKB of FIGS. 1 through 5 and FIGS. 7 through 8. The inverter 602 is coupled to the supply voltage VDD. In some embodiments, inverter 602 is a CMOS inverter type that is coupled to supply voltage VDD and reference voltage VSS.

The gate terminal of NMOS transistor 604 is configured to receive clock signal CLK. The source terminal of the NMOS transistor 604 is coupled to the supply reference voltage VSS. The NMOS terminal of NMOS transistor 604, the NMOS terminal of PMOS transistor 606, the gate terminal of PMOS transistor 610, and the input terminals of inverter 616 are coupled together at node 6-N1.

The gate terminal of PMOS transistor 606 is configured to receive a clock signal CLK. The source terminal of the PMOS transistor 606 is coupled to the NMOS terminal of the PMOS transistor 608.

The source terminal of the PMOS transistor 608 is coupled to the supply voltage VDDM. The gate terminal of the PMOS transistor 608, the NMOS terminal of the NMOS transistor 614, and the NMOS terminal of the PMOS transistor 612 are coupled to each other at the node 6-N2. The gate terminal of PMOS transistor 608 is configured to receive the voltage at node 6-N2. In some embodiments, PMOS transistor 608 is turned "on" or "off" based on the voltage at node 6-N2.

NMOS transistor 604, PMOS transistor 606, and PMOS transistor 608 are configured to set the voltage at node 6-N1, which corresponds to signal CLK_LSB. For example, in some embodiments, if NMOS transistor 604 is turned on, NMOS transistor 604 is configured to pull node 6-N1 toward reference voltage VSS. For example, in some embodiments, if PMOS transistor 606 and PMOS transistor 608 are turned on, PMOS transistor 606 and PMOS transistor 608 are configured to pull node 6-N1 toward supply voltage VDDM.

The source terminal of the PMOS transistor 610 is coupled to the supply voltage VDDM. The NMOS terminal of PMOS transistor 610 is coupled to the source terminal of PMOS transistor 612. The gate terminal of PMOS transistor 610 is coupled to at least node 6-N1. The voltage at node 6-N1 corresponds to signal CLK_LSB. The gate terminal of PMOS transistor 610 is configured to receive signal CLK_LSB. In some embodiments, PMOS transistor 610 is turned "on" or "off" based on the voltage at node 6-N1, which corresponds to signal CLK_LSB.

The gate terminal of PMOS transistor 612 is configured to receive signal CLKB1 from inverter 602. Each of the gate terminal of the PMOS transistor 612, the gate terminal of the NMOS transistor 614, and the output terminal of the inverter 602 is coupled to each other.

The gate terminal of NMOS transistor 614 is configured to receive signal CLKB1 from inverter 602. The source terminal of the NMOS transistor 614 is coupled to the supply reference Press VSS.

NMOS transistor 614, PMOS transistor 610, and PMOS transistor 612 are configured to set the voltage at node 6-N2, which corresponds to signal CLK_LSB. For example, in some embodiments, if NMOS transistor 614 is turned on, NMOS transistor 614 is configured to pull node 6-N2 toward reference voltage VSS. For example, in some embodiments, if PMOS transistor 610 and PMOS transistor 612 are turned on, PMOS transistor 610 and PMOS transistor 612 are configured to pull node 6-N2 toward supply voltage VDDM.

The input terminal of inverter 616 is configured to receive signal CLK_LSB from node 6-N1. The output terminal of inverter 616 is configured to output signal CLK_LS. In some embodiments, signal CLK_LS is an inverted version of signal CLK_LSB. Inverter 616 is configured to generate signal CLK_LS based on signal CLK_LSB. The inverter 616 is coupled to the supply voltage VDDM. In some embodiments, inverter 616 is a CMOS inverter type that is coupled to supply voltage VDDM and reference voltage VSS. The signal CLK_LS corresponds to the output signal of the level shifter circuit 600. The signal CLK_LS is a level offset version of the signal CLK. For example, the signal CLK_LS is a high voltage domain clock signal using the supply voltage VDDM, and the signal CLK is a low voltage domain clock signal using the supply voltage VDD.

7 is a timing diagram 700 of a waveform of a clock circuit, such as clock circuit 500 of FIG. 5 or clock circuit 800 of FIG. 8, in accordance with some embodiments.

At time t0, signal CEB transitions from a logic high to a logic low.

At time t1, signal CEB is logic low.

At time t2, the signal CEB changes to a logic low and the signal CLK_ENB is logic low, and the signal CLK_EN generated by the "reverse OR" gate 208 transitions from a logic low to a logic high. In response to the signal CLK_EN transitioning from logic low to logic high, the NMOS transistor 214 is turned "on", thereby connecting the node N3 to the node N1, and the PMOS transistor 218 is turned off, thereby disconnecting the node N3 from the node N4. In some embodiments, signal CLK_EN corresponds to the stored or latched state of signal CEB of CEB latch circuit 201A.

At time t3, signal CLK_EN is logic high and signal CLK transitions from logic low to logic high. In response to signal CLK transitioning from logic low to logic high, NMOS transistor 210 is turned "on" and PMOS transistor 606 and PMOS transistor 216 are turned "off". By turning on the NMOS transistor 210, the NMOS transistor 210 pulls the node N1 toward VSS, causing the signal CLKB to transition from a logic high to a logic low.

At time t4, the signal CLK is logic high, the signal CLK_LS transitions from a logic low to a second logic high level (eg, supply voltage VDDM), the signal CLKB transitions from a logic high to a logic low, and the signal CKPB is at a second logic high level ( For example, the supply voltage VDDM) transitions to a logic low.

In response to the signal CLK_LS transitioning from a logic low to a second logic high level (eg, supply voltage VDDM), NMOS transistor 502 is turned "on" and PMOS transistor 604 and PMOS transistor 610 are turned "off". By turning on NMOS transistor 502, NMOS transistor 502 assists NMOS transistor 210 to pull node N1 toward VSS, thereby causing signal CLKB to transition from logic high to logic low.

In response to signal CLK being logic high, NMOS transistor 210 is turned "on" and node N3 is pulled toward reference voltage VSS, causing signal CKPB to transition from a second logic high level (eg, supply voltage VDDM) to a logic low.

At time t5, signal CLKB is logic low and signal CLK_LS is at The second logic high level and the signal CKPB is logic low. In response to the signal CKPB being logic low, the signal CKPI is transitioned from logic low to second logic high level by inverter 228.

At time t6, signal CKPI is at a second logic high level and signal CLK_ENB transitions from a logic low to a logic high. In response to the signal CKPB being logic low, the inverter 228 causes the signal CKPI to be at the second logic high level by inverting the signal CKPB, thereby turning the NMOS transistor 226 on. However, the NMOS transistor 222 has been turned on by the signal RSTCKB at the second logic high level. Therefore, by turning on the NMOS transistor 226, the NMOS transistor 226 and the NMOS transistor 222 boost the signal CKPB to maintain a logic low, thereby enhancing the signal CKPI to be at the second logic high level.

At time t7, the signal CLK_EN transitions to a logic high, causing the signal CLK_EN to transition from a logic high to a logic low. In other words, the "anti-OR" gate 208 outputs a logic low signal (CLK_EN) in response to the signal CLK_ENB transitioning to logic high and the signal CEB being logic low.

At time t8, signal CLK_EN is logic low. In response to signal CLK_EN being logic low, NMOS transistor 214 is turned off, thereby disconnecting node N3 from node N1, and PMOS transistor 218 is turned "on", thereby connecting node N3 to node N4.

At time t9, the signal CEB transitions from a logic low to a logic high.

At time t10, signal CLK transitions from a logic high to a logic low. In response to signal CLK transitioning from logic high to logic low, NMOS transistor 210 begins to open and PMOS transistor 506 and PMOS transistor 216 begin to turn "on". Node N3 is coupled to node N4 by turning on PMOS transistor 216.

At time t11, signal CLK is logic low and CLK_LS transitions from a second logic high level to a logic low. In response to signal CLK is logic low, NMOS transistor Body 210 is disconnected and PMOS transistor 506 and PMOS transistor 216 are turned "on". In response to signal CLK_LS transitioning from a second logic high level (eg, supply voltage VDDM) to a logic low, NMOS transistor 502 begins to open, and PMOS transistor 604 and PMOS transistor 610 begin to turn "on". By turning on PMOS transistor 506, PMOS transistor 506 and PMOS transistor 504 begin to pull node N1 toward supply voltage VDDM.

At time t12, signal RSTCKB transitions from a second logic high level to a logic low. In response to the signal RSTCKB transitioning from a second logic high level to a logic low, the NMOS transistor 222 is turned off, thereby causing the NMOS transistor 222 to be disconnected from the node N3. In response to the signal RSTCKB transitioning from a second logic high level to a logic low, the PMOS transistor 520 is turned "on". When the PMOS transistor 520 is turned on, the PMOS transistor 520 pulls the node N3 toward the supply voltage VDDM.

At time t13, signal CLK_LS is logic low, causing NMOS transistor 502 to turn off, and PMOS transistor 504 and PMOS transistor 510 are turned on, thereby causing signal CLKB to transition from a logic low to a second logic high level (eg, Supply voltage VDDM). For example, by turning on the PMOS transistor 504 and the PMOS transistor 510, the PMOS transistor 504 assists the PMOS transistor 506 to pull the node N1 toward the supply voltage VDDM, thereby causing the signal CLKB to transition from a logic low to a second logic high. quasi. The node N3 is connected to the node N4 via the PMOS transistor 216 and the PMOS transistor 510 by being turned on by the PMOS transistor 216 and the PMOS transistor 510.

At time t14, the signal RSTCKB is logic low and the signal CKPB transitions from a logic low to a second logic high level. In response to the signal RSTCKB being logic low, the NMOS transistor 222 is turned off, thereby causing the NMOS transistor 226 to pass through the NMOS. The transistor 222 is disconnected from the node N3. In response to the signal RSTCKB being logic low, the PMOS transistor 520 is turned on, pulling the node N3 toward the supply voltage VDDM, thereby causing the signal CKPB to transition from a logic low to a second logic high level. In other words, the SRAM state latch circuit is reset to the second logic high level by the signal RSTCKB.

At time t15, signal CLKB is logic high.

At time t16, the signal CKPB is at the second logic high level.

At time t17, in response to the signal CKPB being at the second logic high level, the signal CKPI transitions from the second logic high level to a logic low.

At time t18, signal CKPI is logic low and signal CLK_ENB transitions from logic high to logic low. In response to signal CKPI being logic low, PMOS transistor 512 is turned "on" and NMOS transistor 226 is turned "off". By turning on the PMOS transistor 512, the node N4 is pulled toward the supply voltage VDD. However, node N4 is coupled to node N3 via two paths; via PMOS transistor 218 and via PMOS transistor 216 and PMOS transistor 510. Therefore, in addition to the PMOS transistor 520, the PMOS transistor 216, the PMOS transistor 510, the PMOS transistor 218, and the PMOS transistor 512 pull the node N3 toward the supply voltage VDDM. In other words, the PMOS transistor 520 boosts the signal CKPB to remain at the second logic high level.

At time t19, signal CLK_ENB is logic low, and signal RSTCKB transitions from logic low to second logic high level in response to signal CKPI being logic low. By transitioning the signal RSTCKB from a logic low to a second logic high level, the PMOS transistor 520 is turned off and the NMOS transistor 222 is turned "on". However, the node N3 and the signal CKPB are maintained at the supply voltage VDDM via one or more of the PMOS transistor 216, the PMOS transistor 510, the PMOS transistor 218, and the PMOS transistor 512, and the NMOS transistor 226 is turned off and will not Node N3 is pulled to VSS.

At time t20, signal RSTCKB is at a second logic high level (eg, supply voltage VDDM) and signal CKPB is at a second logic high level.

Clock circuit

FIG. 8 is a circuit diagram of a clock circuit 800 in accordance with some embodiments.

The clock circuit 800 is a variant of the clock circuit 400 of FIG. 4 and the clock circuit 500 of FIG. 5, and thus a similar detailed description is omitted. In other words, the clock circuit 800 combines the features of the clock circuit 400 and the clock circuit 500. For example, clock circuit 800 utilizes static clock circuit 400 of FIG. 4 in combination with the level shifter feature of clock circuit 500 of FIG.

The clock circuit 800 is implemented using a static two-track circuit having two different voltage domains (eg, signal CLK and signal CLK_LS). In some embodiments, the clock circuit 800 is further implemented with a clock level shifter (eg, level shifter circuit 600) for the dual track memory design. Clock circuit 800 is one embodiment of clock circuit 101 of FIG.

The PMOS transistor 802 of the clock circuit 800 replaces the PMOS transistor 520 at a different location than the clock circuit 500 of FIG. In other words, PMOS transistor 802 is similar to PMOS transistor 520, but is positioned in different locations. For example, the PMOS transistor 802 is coupled in parallel with the PMOS transistor 512 between the supply voltage VDDM and the node N4. By locating the PMOS transistor 802 to be coupled to the node N4, the node N3 does not float when the PMOS transistor 802 and the NMOS transistor 222 are turned "on" or "off", thereby generating a static logic type circuit.

The gate terminal of PMOS transistor 802 is configured to receive signal RSTCKB. The PMOS transistor 802 is turned on or off based on the signal RSTCKB. In some embodiments, the gate of PMOS transistor 82 and NMOS transistor 222 The gate is coupled. The source terminal of the PMOS transistor 802 is coupled to the supply voltage VDDM. In some embodiments, the source terminal of PMOS transistor 802 is coupled to the source terminal of PMOS transistor 512. The NMOS terminal of PMOS transistor 802, the source terminal of PMOS transistor 510, the source terminal of PMOS transistor 218, and the NMOS terminal of PMOS transistor 512 are coupled to each other at node N4.

By not including the PMOS transistor 520, the node N3 of the clock circuit 800 is not pulled to the supply voltage VDDM based only on the signal RSTCKB. For example, the PMOS transistor 802 is coupled to the node N3 by the PMOS transistor 218 (which is driven by the signal CLK_EN) or by the PMOS transistor 510 and the PMOS transistor 216 (which is driven by the corresponding signal CLK_LS and the signal CLK). . Thus, in the first configuration, PMOS transistor 802 and PMOS transistor 218 are configured to pull node N3 to supply voltage VDDM based on signal RSTCKB and signal CLK_EN. In a second configuration, PMOS transistor 802, PMOS transistor 510, and PMOS transistor 216 are configured to pull node N3 toward supply voltage VDDM based on signal RSTCKB, signal CLK_LS, and signal CLK, respectively. In some embodiments, the supply voltage VDD is in the range of from about 0.3 volts to about 1.3 volts. In some embodiments, the supply voltage VDDM is in a range from about 0.3 volts to about 1.3 volts.

In some embodiments, the clock circuit 800 has a larger operating voltage range than other methods by using the dual rail memory design of the clock circuit 800.

The timing diagram 700 of the waveform is applied to the clock circuit 500 and the clock circuit 800 of FIG. 5, and thus a similar detailed description is omitted. However, some operations of the PMOS transistor 802 are different from the PMOS transistor 520, and thus are described below. Simple A detailed description of the similar operation of the clock circuit 800 and the clock circuit 500 is omitted here.

At time t12, signal RSTCKB transitions from a second logic high level (eg, supply voltage VDDM) to a logic low. In response to signal RSTCKB transitioning from a second logic high level to a logic low, NMOS transistor 222 begins to turn off and PMOS transistor 802 begins to turn "on".

At time t13, signal CLKB transitions from a logic low to a logic high.

At time t14, the signal RSTCKB is logic low and the signal CKPB transitions from a logic low to a second logic high level. In response to signal RSTCKB being logic low, NMOS transistor 222 is turned off, thereby causing NMOS transistor 226 to be disconnected from node N3 via NMOS transistor 222. In response to signal RSTCKB being logic low, PMOS transistor 802 is turned "on", thereby connecting node N4 to node N3 via PMOS transistor 510, PMOS transistor 216, and PMOS transistor 218. Thus, PMOS transistor 802 pulls node N3 to supply voltage VDD via node N4, thereby transitioning signal CKPB from a logic low to a second logic high level. In other words, the SRAM state latch circuit 801D is reset to the second logic high level by the signal RSTCKB.

At time t15, signal CLKB is logic high.

At time t16, the signal CKPB is at the second logic high level.

At time t17, in response to signal CKPB being at a second logic high level at time t16, inverter 228 causes signal CKPI to transition from a second logic high level to a logic low by inverting signal CKPB.

At time t18, signal CKPI is logic low and signal CLK_ENB transitions from logic high to logic low. In response to signal CKPI being logic low, PMOS transistor 512 is turned "on" and NMOS transistor 226 is turned "off". By making PMOS transistor 512 Turned on, PMOS transistor 512 also pulls node N4 toward supply voltage VDDM. Thus, an additional path to pull node N4 and node N3 toward supply voltage VDDM is generated by turning on PMOS transistor 512. In other words, the PMOS transistor 512 boosts the signal CKPB to remain at the second logic high level.

At time t19, signal CLK_ENB is logic low, and signal RSTCKB transitions from logic low to second logic high level in response to signal CKPI being logic low. By transitioning the signal RSTCKB from a logic low to a second logic high level, the PMOS transistor 802 is turned off and the NMOS transistor 222 is turned "on". However, the node N3 and the signal CKPB are maintained at the supply voltage VDDM via one or more of the PMOS transistor 216, the PMOS transistor 218, the PMOS transistor 510, and the PMOS transistor 512, and the NMOS transistor 226 is turned off and will not Node N3 is pulled to VSS.

At time t20, the signal RSTCKB is at the second logic high level and the signal CKPB is at the second logic high level.

method

9 is a flow diagram of a method of operating a clock circuit, such as the clock circuit of FIGS. 1-2, 4-5, or 8, in accordance with some embodiments. It should be understood that additional operations may be performed before, during, and/or after the method 900 depicted in FIG. 9, and some other processes may be described briefly herein. It should be understood that the method 900 utilizes features of one or more of the timing diagram 300 of FIG. 3, the level shifter circuit 600 of FIG. 6, or the timing diagram 700 of FIG.

In operation 902 of method 900, the first clock signal (CLK) is received by clock trigger circuit 201B. In some embodiments, operation 902 further includes receiving an enable signal (CEB) by the first latch (CEB latch circuit 201A).

In operation 904 of method 900, the first latch (CEB latch circuit) 201A) in response to the enable signal (signal CEB) transitioning from a second voltage level (VDD) to a first voltage level (VSS), causing the first latch output signal (CLK_EN) to transition from the first voltage level to The second voltage level. In some embodiments, the second voltage level is different than the first voltage level. In some embodiments, operation 904 is performed by an "anti-OR" gate 208.

In operation 906 of method 900, clock trigger circuit 201B transitions the first node (VSS) to a second voltage level (VDD) from the first voltage level (CLK) to the first node (eg, Node N1) pulls from a first voltage level to a second voltage level. In some embodiments, pulling the first node of operation 906 thereby causes the first control signal (CLKB) of the clock trigger circuit 201B to transition from the first voltage level to the second voltage level. In some embodiments, the clock trigger circuit 201B is coupled to the input of the first latch (eg, latch circuit 201A) and the first trigger circuit (eg, SRAM state) by a first node (eg, node N1) Trigger circuit 201C). In some embodiments, the first control signal (CLKB) from the clock trigger circuit 201B is fed back from the first node (node N1) to the input of the first latch (latch circuit 201A).

In some embodiments, operation 906 further includes turning on NMOS transistor 210 and pulling node N1 toward the reference voltage in response to signal CLK transitioning from the first voltage level to the second voltage level at time t3 (FIG. 3). VSS, thereby causing signal CLKB to transition from a second voltage level to a first voltage level at time t4 (FIG. 5).

In operation 908 of method 900, a first trigger circuit (eg, SRAM state trigger circuit 201C) causes an output clock signal (eg, signal CKPB) to transition from a second voltage level to a first voltage level.

In some embodiments, operation 908 includes a first trigger circuit (eg, The SRAM state trigger circuit 201C) outputs a clock signal in response to the first clock signal (CLK) transitioning to the second voltage level and in response to the first latch output signal (CLK_EN) transitioning to the second voltage level (eg, , signal CKPB) transitions from the second voltage level to the first voltage level. For example, in some embodiments, operation 908 further includes turning on the first N-type transistor (eg, NMOS transistor 214) in response to the first latched output signal (eg, signal CLK_EN) thereby A node (eg, node N3) is coupled to the first node (eg, node N1), in response to signal CLK transitioning from a first voltage level to a second voltage level at time t3 (FIG. 3) to cause a second N-type The transistor (NMOS transistor 210) is turned on and pulls the first node (node N1) toward the reference voltage VSS, which also pulls the second node (node N3) toward the first voltage level VSS, thereby causing the signal CKPB to be Time t5 (Fig. 3) transitions from the second voltage level to the first voltage level.

In operation 910 of method 900, the first latch (latch circuit 201A) causes the inverted first latch to be inverted in response to the output clock signal (CKPB) transitioning from the second voltage level to the first voltage level. The output signal (eg, signal CLK_ENB) transitions from a first voltage level to a second voltage level. In some embodiments, operation 910 is performed by "reverse" gate 206 in response to at least signal CKPBI.

In operation 912 of method 900, the first latch (latch circuit 201A) transitions from the first voltage level (VSS) to the second voltage level in response to the inverted first latched output signal (CLK_ENB) ( VDD) causes the first latched output signal (CLK_EN) to transition from the second voltage level to the first voltage level. In some embodiments, operation 912 is performed by "reverse OR" gate 208 at time t7 (FIG. 3).

In operation 914 of method 900, an inverter (eg, inverter 228) transitions from a second voltage level to a first voltage level in response to an output clock signal (CKPB). The second control signal (CKPI) is converted from the first voltage level to the second voltage level. In some embodiments, operation 914 is performed at time t5 (FIG. 3).

In operation 916 of method 900, the enable signal (CEB) transitions from a first voltage level to a second voltage level. In some embodiments, operation 916 is performed at time t9 (Fig. 3).

In operation 918 of method 900, the clock trigger circuit (NMOS transistor 210 / PMOS transistor 212) is first to respond to the first clock signal (CLK) transitioning from the second voltage level to the first voltage level. The node (node N1) is pulled from the second voltage level to the first voltage. In some embodiments, pulling the first node of operation 918 thereby causes the first control signal (CLKB) of the clock trigger circuit 201B to transition from the second voltage level to the first voltage level.

In operation 920 of method 900, the reset signal (eg, signal RSTCKB) transitions from the second voltage level in response to the output clock signal (eg, signal CKPB) transitioning from the second voltage level to the first voltage level. Is the first voltage level. In some embodiments, operation 920 occurs in response to at least a second control signal (CKPI) transitioning from a first voltage level to a second voltage level.

In operation 922 of method 900, the first trigger circuit (SRAM state trigger circuit 201C) causes the output clock signal (CKPB) to be self-converted from the second voltage level to the first voltage level in response to the reset signal (RSTCKB). The first voltage level transitions to a second voltage level.

In some embodiments, operation 922 includes breaking the second N-type transistor (eg, NMOS transistor 222) in response to the reset signal (eg, signal RSTCKB) transitioning from the second voltage level to the first voltage level. Turning on, thereby causing the second node (eg, node N3) to be disconnected from the third N-type transistor (eg, NMOS transistor 226) Open the connection.

In some embodiments, the operation 922 further includes: in response to the reset signal (eg, the signal RSTCKB) transitioning from the second voltage level to the first voltage level VSS to cause the first P-type transistor (eg, the PMOS transistor 220) Turning on, thereby pulling the second node (eg, node N3) to the second voltage level of the supply voltage VDD.

In operation 924 of method 900, the reset signal (eg, signal RSTCKB) is responsive to the output clock signal (eg, signal CKPB) transitioning from the first voltage level VSS to the second voltage level VDD from the first voltage level. The quasi-conversion to the second voltage level. In some embodiments, operation 924 occurs at least in response to the second control signal (CKPI) transitioning from the second voltage level to the first voltage level. For example, in some embodiments, operation 924 occurs after time t16 of FIG. 3 corresponding to transition of second control signal CKPI to a first voltage level, the operation turning off NMOS transistor 226 and preventing NMOS transistor 226 pulls the second node (node N3) toward the first voltage level.

In some embodiments, operation 924 includes causing the second N-type transistor (eg, NMOS transistor 222) to be connected in response to the reset signal (eg, signal RSTCKB) transitioning from the first voltage level to the second voltage level. The second node (e.g., node N3) is thereby connected to the third N-type transistor (NMOS transistor 226).

In some embodiments, operation 924 further includes causing the first P-type transistor (eg, PMOS transistor 220) to transition from the first voltage level to the second voltage level in response to the reset signal (eg, signal RSTCKB). Disconnected thereby disconnecting the second node (eg, node N3) from the third N-type transistor (NMOS transistor 226) or supply voltage VDD.

Although method 900 is described above with respect to Figures 2 through 3, it should be understood that the method 900 utilizes features of one or more of Figures 4 through 5, 6, or 7. For example, in some embodiments, method 900 is used with clock circuit 500 of FIG. 5 and level offset circuit 600 of FIG. In these embodiments, operation 902 of method 900 further includes receiving, by the clock trigger circuit, a second clock signal (CLK_LS) having a second voltage swing (VDDM), the second voltage swing being different from the first time The first voltage swing of the pulse signal (VDD). Moreover, in these embodiments, other operations of method 900 will be performed by at least a first clock signal (CLK) or a second clock signal (CLK_LS), and the second voltage level VDD is replaced by a supply voltage VDDM. For example, in some embodiments, causing the clock trigger circuit to pull the first node includes causing the clock trigger circuit to change the first node from the third voltage level to the first voltage level in response to the second clock signal Pulling from a first voltage level to a third voltage level, the third voltage level being different from the first voltage level and the second voltage level.

One aspect of the present specification relates to a clock circuit. The clock circuit includes: a first latch configured to generate a first latch output signal based on the first control signal, the enable signal, and the output clock signal; and a second latch coupled to the a first latch, configured to generate the output clock signal in response to the second control signal; a first trigger circuit coupled to the first latch and the second latch, And configured to adjust the output clock signal at least in response to the first latch output signal or the reset signal; and the clock trigger circuit is coupled to the first latch by the first node And the first trigger circuit configured to generate a first control signal in response to the input clock signal, and configured to control the first latch and the at least based on the first control signal The first trigger circuit. In some embodiments, the clock trigger circuit includes: a first P-type transistor having a source coupled to a first supply voltage, a gate of the first P-type transistor configured to receive the lose Entering a clock signal, and a drain of the first P-type transistor is coupled to the first latch and the first trigger circuit by the first node; and a first N-type transistor, The gate is configured to receive the input clock signal, the source of the first N-type transistor is coupled to a second supply voltage different from the first supply voltage, and the first N-type A drain of the transistor is coupled to the first latch, the first flip-flop circuit, and the drain of the first P-type transistor by the first node. In some embodiments, the first latch includes an OR logic gate including: a first input terminal of the OR logic gate configured to receive the first control signal and coupled to at least Connected to the first node; a second input terminal of the OR logic gate configured to receive the first latch output signal and coupled to at least a second node; and the OR logic An output terminal of the gate configured to output an OR signal based on the first latch output signal and the first control signal. In some embodiments, the first latch further includes a "reverse" logic gate, including: a first input terminal of the "reverse" logic gate coupled to the OR logic gate The output terminal, the first input terminal of the "reverse" logic gate is configured to receive the OR signal; the second input terminal of the "reverse" logic gate is configured Receiving an inverted second control signal; and an output terminal of the "reverse" logic gate configured to output a first "based on the inverted second control signal and the OR signal" In contrast to the output signal. In some embodiments, the first latch further includes an "reverse" logic gate, including: a first input terminal of the "reverse" logic gate configured to receive the enable signal; a second input terminal of the "reverse" logic gate configured to receive the first "reverse" output signal and coupled to the output terminal of the "reverse" logic gate; and the And an output terminal of the logic gate configured to output based on the enable signal and the first "reverse" output signal The first latch output signal, the output terminal of the "reverse" logic gate is coupled to the second node, and the "reverse OR" logic gate is configured to set the second The voltage of the node, the voltage of the second node corresponding to the first latch output signal. In some embodiments, the second latch includes an inverter having an input terminal and an output terminal, the input terminal of the inverter being configured to receive the output clock signal and coupled to a third node of the first trigger circuit; and the output terminal of the inverter is configured to output the second control signal in response to the output clock signal. In some embodiments, the second latch further includes: a first P-type transistor having a source coupled to the first supply voltage, a drain of the first P-type transistor and the first a second node of the trigger circuit is coupled, and a gate of the first P-type transistor is coupled to the output terminal of the inverter and configured to receive the second control signal; and first An N-type transistor having a source coupled to a second supply voltage different from the first supply voltage, a drain of the first N-type transistor coupled to the third node of the first trigger circuit And the gate of the first N-type transistor is coupled to the output terminal of the inverter and configured to receive the second control signal. In some embodiments, the first trigger circuit includes: a first N-type transistor having a source coupled to the first node, and a gate of the first N-type transistor configured to receive The first latch output signal is coupled to the first latch by a second node, and the drain of the first N-type transistor is coupled to the third node of the first flip-flop circuit; And a first P-type transistor having a source coupled to a fourth node of the first flip-flop circuit, a gate of the first P-type transistor configured to receive the input clock signal, and The drain of the first P-type transistor is coupled to the drain of the first N-type transistor by the third node of the first flip-flop circuit. In some embodiments, the first trigger circuit further includes: a second P-type battery a crystal having a source coupled to the fourth node of the first flip-flop circuit, a gate of the second P-type transistor configured to receive the first latch output signal, and the The drain of the second P-type transistor is performed by the third node of the first flip-flop circuit and the drain of the first N-type transistor and the drain of the first P-type transistor Coupling. In some embodiments, the first trigger circuit further includes: a second N-type transistor, a source thereof is coupled to the second latch, and a gate of the second N-type transistor is configured Receiving the reset signal, and the drain of the second N-type transistor is coupled to the third node of the first flip-flop circuit; and the third P-type transistor, the source and the first The supply voltage is coupled, the gate of the third P-type transistor is configured to receive the reset signal, and one of the following configurations: the drain of the third P-type transistor is The third node of the first flip-flop circuit is coupled to the drain of the second N-type transistor; or the drain of the third P-type transistor is provided by the first flip-flop circuit The fourth node is coupled to the source of the first P-type transistor.

Another aspect of the present specification relates to a clock circuit. The clock circuit includes: a first latch configured to generate a first latch output signal based on the first control signal, the enable signal, and the output clock signal; and a second latch coupled to the a first latch, configured to generate the output clock signal in response to the second control signal; a first trigger circuit coupled to the first latch and the second latch, And configured to adjust the output clock signal at least in response to the first latch output signal or the reset signal; the clock trigger circuit is coupled to the first latch by the first node and The first trigger circuit is configured to generate the first control signal in response to a first clock signal having a first voltage swing, and is configured to control the at least based on the first clock signal a first latch and the first touch And a level shifter circuit coupled to at least the clock trigger circuit and configured to generate a second clock signal having a second voltage swing, the second voltage swing being different from The first voltage swing of the first clock signal. In some embodiments, the clock trigger circuit includes: a first N-type transistor having a source coupled to a first supply voltage, a gate of the first N-type transistor configured to receive the a first clock signal, and a drain of the first N-type transistor is coupled to the first latch and the first trigger circuit by the first node; and a second N-type transistor a source at least coupled to the first supply voltage, a gate of the second N-type transistor configured to receive the second clock signal, and a second N-type transistor The pole is coupled to the first latch, the first trigger circuit, and the drain of the first N-type transistor by the first node. In some embodiments, the clock trigger circuit further includes: a first P-type transistor having a source coupled to a second supply voltage different from the first supply voltage, and the first P-type power a gate of the crystal configured to receive the first clock signal; and a second P-type transistor having a source coupled to a drain of the first P-type transistor, the second P-type a gate of the crystal is configured to receive the second clock signal, and a drain of the second P-type transistor is coupled to the first latch and the first trigger by the first node The circuit, the drain of the first N-type transistor, and the drain of the second N-type transistor are coupled. In some embodiments, the first trigger circuit includes: a first N-type transistor having a source coupled to the first node, and a gate of the first N-type transistor configured to receive The first latch output signal is coupled to the first latch by a second node, and the drain of the first N-type transistor is coupled to the third node of the first flip-flop circuit; And a first P-type transistor, the gate of the first P-type transistor configured to receive the first clock signal, and the first P-type transistor The third node of the first trigger circuit is coupled to the drain of the first N-type transistor. In some embodiments, the first trigger circuit further includes: a second P-type transistor, a source of which is coupled to a fourth node of the first flip-flop circuit, and a gate of the second P-type transistor a state of receiving the second clock signal, and a drain of the second P-type transistor is coupled to a source of the first P-type transistor; and a third P-type transistor, the source of which is borrowed The fourth node of the first flip-flop circuit is coupled to the source of the second P-type transistor, and the gate of the third P-type transistor is configured to receive the first And latching the output signal, and the drain of the third P-type transistor is performed by the third node of the first flip-flop circuit and the drain of the first N-type transistor and the first The drain of the P-type transistor is coupled. In some embodiments, the first trigger circuit further includes: a second N-type transistor, a source thereof is coupled to the second latch, and a gate of the second N-type transistor is configured Receiving the reset signal, and the drain of the second N-type transistor is coupled to the third node of the first flip-flop circuit; and the fourth P-type transistor, the source and the first The supply voltage is coupled, the gate of the fourth P-type transistor is configured to receive the reset signal, and one of the following configurations: the drain of the fourth P-type transistor is The third node of the first flip-flop circuit is coupled to the drain of the second N-type transistor; or the drain of the fourth P-type transistor is coupled to the first trigger circuit The fourth node is coupled to the source of the second P-type transistor and the source of the third P-type transistor.

Another aspect of the present specification is directed to a method of operating a clock circuit. The method includes: receiving, by a clock trigger circuit, a first clock signal; and responding to the enabling signal from a second voltage level to a first voltage level, and causing the first latch output signal by the first latch Transitioning from the first voltage level to the second voltage level, The second voltage level is different from the first voltage level; the clock is triggered in response to the first clock signal transitioning from the first voltage level to the second voltage level The circuit pulls the first node from the first voltage level to the second voltage level, and pulls the first node to thereby cause the first control signal of the clock trigger circuit to be from the first The voltage level is converted to the second voltage level, and the clock trigger circuit is connected to the input end of the first latch and the first trigger circuit by the first node, and from the clock trigger circuit The first control signal is fed back from the first node to the input end of the first latch; and in response to the first clock signal being converted to the second voltage level and responding Converting the output clock signal from the second voltage level to the first voltage level by the first trigger circuit when the first latch output signal is converted to the second voltage level. In some embodiments, the method further includes: in response to the output clock signal transitioning from the second voltage level to the first voltage level, causing the reset signal to be from the second voltage level Converting to the first voltage level; causing the output clock signal to be from the first voltage level in response to the reset signal transitioning from the second voltage level to the first voltage level Converting to the second voltage level; and causing the reset signal to be from the first voltage level in response to the output clock signal transitioning from the first voltage level to the second voltage level Quasi-transition to the second voltage level. In some embodiments, the converting the output clock signal from the second voltage level to the first voltage level by the first trigger circuit comprises: responding to the first latch output signal The first N-type transistor is turned on, thereby coupling the second node to the first node and pulling the second node toward the first voltage level. In some embodiments, the output clock signal is caused by the first trigger circuit in response to the reset signal being converted from the second voltage level to the first voltage level. Converting the first voltage level to the second voltage level includes: disconnecting the second N-type transistor in response to the reset signal transitioning from the second voltage level to the first voltage level Thereby disconnecting the second node from the third N-type transistor; and causing the first P to be converted from the second voltage level to the first voltage level in response to the reset signal The type transistor is turned on, thereby pulling the second node toward the second voltage level of the first supply voltage. In some embodiments, the reset signal is converted from the first voltage level to the said response to the output clock signal transitioning from the first voltage level to the second voltage level. The second voltage level includes: turning on the second N-type transistor in response to the reset signal transitioning from the first voltage level to the second voltage level, thereby Connecting a second node to the third N-type transistor; and disconnecting the first P-type transistor in response to the reset signal transitioning from the first voltage level to the second voltage level Thereby disconnecting the second node from the first supply voltage.

A number of embodiments have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, various transistors are shown as specific dopant types for illustrative purposes (eg, N-type metal oxide semiconductors or P-type metal oxide semiconductors (N-type Metal Oxide Semiconductor/P-type Metal Oxide) Semiconductor (NMOS/PMOS). Embodiments of the present disclosure are not limited to a particular type. Selecting different dopant types for a particular transistor is within the scope of various embodiments. Low or high logic for the various signals described above. Values are also used to illustrate. The various embodiments are not limited to a particular logic value when the signal is activated and/or deactivated. The selection of different logic values is within the scope of various embodiments. In various embodiments, the transistor acts as a switch. The switching circuit used in the crystal is within the scope of various embodiments. In various embodiments, the source of the transistor can be configured as 汲 The pole and the drain can be configured as a source. Therefore, the terms source and drain are used interchangeably. The various signals are generated by corresponding circuits, but the circuit is not shown for simplicity.

Various figures show capacitor circuits using discrete capacitors for illustration. An equivalent circuit can be used. For example, capacitive elements, circuits, or networks (eg, combinations of capacitors, capacitive elements, devices, circuits, etc.) can be used in place of discrete capacitors. The above description includes illustrative steps, but the steps are not necessarily performed in the order shown. Depending on the spirit and scope of the disclosed embodiments, steps, replacement steps, order of changing steps, and/or elimination steps may be added as needed.

The foregoing has outlined the features of several embodiments so that those of ordinary skill in the art can better understand the embodiments of the invention. It will be appreciated by those skilled in the art that the embodiments of the present invention can be used as a basis for designing or modifying other methods and structures for achieving the same objectives and/or achieving the same advantages. A person skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the disclosure, and those skilled in the art can carry out the invention without departing from the spirit and scope of the disclosure. Make changes, substitutions and changes.

Claims (10)

A clock circuit includes: a first latch configured to generate a first latch output signal based on a first control signal, an enable signal, and an output clock signal; a second latch coupled to the a first latch, configured to generate the output clock signal in response to the second control signal; a first trigger circuit coupled to the first latch and the second latch, And configured to adjust the output clock signal at least in response to the first latch output signal or the reset signal; and the clock trigger circuit is coupled to the first latch by the first node And the first trigger circuit configured to generate the first control signal in response to an input clock signal, and configured to control the first latch based on at least the first control signal and The first trigger circuit. The clock circuit of claim 1, wherein the clock trigger circuit comprises: a first P-type transistor, a source coupled to the first supply voltage, the first P-type transistor The gate is configured to receive the input clock signal, and the drain of the first P-type transistor is coupled to the first latch and the first trigger circuit by the first node And a first N-type transistor having a gate configured to receive the input clock signal, a source of the first N-type transistor coupled to a second supply voltage different from the first supply voltage And the drain of the first N-type transistor is performed by the first node and the first latch, the first trigger circuit, and the drain of the first P-type transistor Coupling. The clock circuit of claim 1, wherein the first latch comprises: an OR gate, comprising: a first input terminal of the OR logic gate configured to receive The first control signal is coupled to the first node; the second input terminal of the OR logic gate is configured to receive the first latch output signal and is coupled to at least the second node; The output terminal of the OR logic gate is configured to output or output a signal based on the first latch output signal and the first control signal. The clock circuit of claim 1, wherein the second latch comprises: an inverter having an input terminal and an output terminal, the input terminal of the inverter being configured to receive The output clock signal is coupled to a third node of the first trigger circuit; and the output terminal of the inverter is configured to output the second in response to the output clock signal Control signal. The clock circuit of claim 1, wherein the first trigger circuit comprises: a first N-type transistor, a source of which is coupled to the first node, the first N-type transistor The gate is configured to receive the first latch output signal and is coupled to the first latch by a second node, and the first N-type transistor has a drain and the first a third node of the trigger circuit is coupled; and a first P-type transistor, the source of which is coupled to the fourth node of the first trigger circuit, and the gate of the first P-type transistor is configured to receive The input clock signal, And the drain of the first P-type transistor is coupled to the drain of the first N-type transistor by the third node of the first flip-flop circuit. A clock circuit includes: a first latch configured to generate a first latch output signal based on a first control signal, an enable signal, and an output clock signal; a second latch coupled to the a first latch, configured to generate the output clock signal in response to the second control signal; a first trigger circuit coupled to the first latch and the second latch, And configured to adjust the output clock signal at least in response to the first latch output signal or the reset signal; the clock trigger circuit is coupled to the first latch by the first node and The first trigger circuit is configured to generate the first control signal in response to a first clock signal having a first voltage swing, and is configured to control the at least based on the first clock signal The first latch and the first trigger circuit; and a level shifter circuit coupled to the clock trigger circuit at least, and configured to generate a second clock signal having a second voltage swing The second voltage swing is different from the first clock signal Said first voltage swing. The clock circuit of claim 6, wherein the clock trigger circuit comprises: a first N-type transistor, a source coupled to the first supply voltage, the first N-type transistor The gate is configured to receive the first clock signal, and the drain of the first N-type transistor is coupled to the first latch and the first trigger circuit by the first node And a second N-type transistor having a source coupled to the first supply voltage at least a gate of the second N-type transistor configured to receive the second clock signal, and a drain of the second N-type transistor by the first node and the first latch The first trigger circuit and the drain of the first N-type transistor are coupled. The clock circuit of claim 6, wherein the first trigger circuit comprises: a first N-type transistor, a source of which is coupled to the first node, the first N-type transistor The gate is configured to receive the first latch output signal and is coupled to the first latch by a second node, and the first N-type transistor has a drain and the first a third node of the trigger circuit is coupled; and a first P-type transistor, the gate of the first P-type transistor is configured to receive the first clock signal, and the first P-type transistor The drain is coupled to the drain of the first N-type transistor by the third node of the first flip-flop circuit. A method for operating a clock circuit, the method comprising: receiving a first clock signal by a clock trigger circuit; and responding to the first voltage by activating the signal from a second voltage level to a first voltage level Translating the first latched output signal from the first voltage level to the second voltage level, the second voltage level being different from the first voltage level; in response to the first time Converting the pulse signal from the first voltage level to the second voltage level, causing the clock trigger circuit to pull the first node from the first voltage level to the second voltage level, The pulling of the first node thereby causes the first control signal of the clock trigger circuit to change from the first voltage level to the second voltage level, and the clock trigger circuit is The first node is connected to the input end of the first latch and the first trigger circuit, and the clock is triggered from the clock The first control signal of the circuit is fed back from the first node to the input end of the first latch; and in response to the first clock signal being converted to the second voltage level and Relating to the first trigger circuit to cause the output clock signal to transition from the second voltage level to the first voltage level in response to the first latch output signal transitioning to the second voltage level . The method for operating a clock circuit according to claim 9, further comprising: resetting the signal in response to the output clock signal transitioning from the second voltage level to the first voltage level Converting from the second voltage level to the first voltage level; and outputting the clock signal in response to the reset signal transitioning from the second voltage level to the first voltage level Converting from the first voltage level to the second voltage level; and causing the resetting in response to the output clock signal transitioning from the first voltage level to the second voltage level The signal transitions from the first voltage level to the second voltage level.