KR101893388B1 - Voltage Switching Circuit - Google Patents

Abstract

The voltage switching circuit according to the present invention includes: a voltage enable signal generator for outputting a first voltage enable signal having a control signal fixedly delayed and a second voltage enable signal varying the control signal; And a switch control circuit for outputting a first voltage or a second voltage in response to the first and second voltage enable signals; And a control signal generator for outputting the control signal in response to an input signal.

Description

[0001] The present invention relates to a voltage switching circuit,

The present invention relates to a semiconductor device, and more particularly to a voltage switching circuit of a semiconductor integrated circuit.

The voltage switching circuit 10 according to the related art will be described with reference to FIGS. 1A to 1B.

In Fig. 1A, the voltage switching circuit 10 includes a control signal generating section 11 and a switch control circuit section 12. Fig.

The control signal generator 11 generates the control signal OUT in response to the input signal IN. 1B, the switch control circuit portion 12 includes a seventh inverter IV7 for inverting the control signal OUT, an eighth inverter IV8 for inverting the output signal of the seventh inverter IV7, A first switch SW1 connected between node A and node A and outputting a first voltage VBB to node A in response to an output signal of seventh inverter IV7 and a second switch SW2 connected between node A and second voltage VSS, And a second switch SW2 connected to the node A and outputting a second voltage VSS in response to an output signal of the eighth inverter IV8.

The voltage switching circuit 10 according to the related art controls the first switch SW1 and the second switch SW2 in response to the control signal OUT that has passed through the seventh inverter IV7 and the eighth inverter IV8 And outputs the first voltage VBB or the second voltage VSS to the node A. At this time, the voltage switching circuit 10 according to the related art has a structure in which the signal delay amount of the seventh inverter IV7 and the signal delay amount of the eighth inverter IV8 are fixed and the voltages of the seventh inverter IV7 and the eighth inverter IV8 The timing margin of the output signal can not be ensured and the first voltage VBB or the second voltage VSS is simultaneously output to the node A, thereby generating an overcurrent.

The present invention provides a voltage switching circuit that prevents simultaneous connection of dissimilar voltages, thereby reducing overcurrent.

A voltage switching circuit according to an embodiment of the present invention includes a voltage enable signal generator for outputting a first voltage enable signal having a control signal fixedly delayed and a second voltage enable signal varying the control signal; And a switch control circuit for outputting a first voltage or a second voltage in response to the first and second voltage enable signals; And a control signal generator for outputting the control signal in response to an input signal.

The voltage switching circuit according to another embodiment of the present invention includes a first voltage enable signal having a fixed logic level transition time and a second voltage enable signal having a logic level transition time varying according to a logic level transition of the control signal. A voltage enable signal generator for generating a voltage signal; And a switch control circuit for outputting a first voltage or a second voltage in response to the first and second voltage enable signals; And a control signal generator for outputting the control signal in response to an input signal.

According to the present invention, unnecessary currents can be reduced by preventing the simultaneous connection of different voltages to prevent overcurrent, and damage to the semiconductor device due to overcurrent can be prevented.

Figures 1A-1B illustrate voltage switching circuits,
2 is a block diagram of a voltage switching circuit according to an embodiment of the present invention;
3 is a circuit diagram of a voltage switching circuit according to an embodiment of the present invention,
4 is a timing diagram of a voltage switching circuit according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

2 is a block diagram of a voltage switching circuit 100 in accordance with an embodiment of the present invention.

Referring to FIG. 2, the voltage switching circuit 100 according to the embodiment of the present invention is as follows.

The voltage switching circuit 100 includes a control signal generating unit 110 and a switch control circuit unit 120. The switch control circuit unit 120 includes a voltage enable signal generating unit 121 and a switch unit 122. The voltage enable signal generating unit 121 includes a first delay unit 1221 and a second delay unit 1222 ).

The control signal generator 110 generates the control signal OUT in response to the input signal IN. The input signal IN may be a test mode signal. The control signal generator 110 receives the input signal IN in the embodiment of the present invention and generates a control signal OUT having the same logical level transition and performs a buffer operation.

The switch control circuit unit 120 selectively outputs the first voltage VBB or the second voltage VSS in response to the control signal OUT.

The voltage enable signal generator 121 generates the first and second voltage enable signals VBBEN and VSSEN in response to the control signal OUT. The first voltage enable signal VBBEN and the second voltage enable signal VSSEN are at a low level when one of the signals is at a high level. That is, the first voltage enable signal VBBEN and the second voltage enable signal VSSEN are complementary. The voltage enable signal generator 121 outputs the logic level transition time of the first voltage enable signal VBBEN and outputs the second voltage enable signal VSSEN to the voltage enable signal generator 121 The logic level transition time is varied and output. The voltage enable signal generating unit 121 fixes the logic level transition time of the first voltage enable signal VBBEN and changes the logic level transition time of the second voltage enable signal VSSEN, The enable signal VBBEN and the second voltage enable signal VSSEN are prevented from outputting the same logic level at the same time due to the logic level transition.

The first delay unit 1221 delays the control signal OUT to generate a first voltage enable signal VBBEN that is complementary to the control signal OUT. When the control signal OUT transitions from a low level to a high level, the first voltage enable signal VBBEN transitions from a high level to a low level, and when the control signal OUT transitions from a high level to a low level, The enable signal VBBEN transits from a low level to a high level. The first delay unit 1221 is fixed to have the same logic level transition time of the first voltage enable signal VBBEN.

The second delay unit 1222 generates a second voltage enable signal VSSEN whose logic level is shifted in the same manner as the control signal OUT in response to the control signal OUT and the first voltage enable signal VBBEN do. When the control signal OUT transitions from a low level to a high level, the second voltage enable signal VSSEN transitions from a low level to a high level. When the control signal OUT transitions from a high level to a low level, The enable signal VSSEN transits from a high level to a low level.

When the logic level of the first voltage enable signal VBBEN is changed to output the first voltage VBB from the switch unit 122, the second delay unit 1222 inverts the logic of the first voltage enable signal VBBEN, Before the level transition, the logic level of the second voltage enable signal VSSEN is transited.

When the logic level transition starts to stop the first voltage enable signal VBBEN from outputting the first voltage VBB from the switch unit 122, the second delay unit 1222 outputs the first voltage enable signal VBBEN, Level transition of the second voltage enable signal VSSEN is completed after a predetermined time after the first voltage enable signal VBBEN completes the logic level transition in response to the first voltage enable signal VBBEN.

3 is a circuit diagram of a voltage switching circuit 100 according to an embodiment of the present invention.

The voltage switching circuit 100 according to the embodiment of the present invention will be described with reference to FIG.

The voltage switching circuit 100 includes a control signal generating unit 110 and a switch control circuit unit 120.

The control signal generating unit 110 is connected between the first inverter IV1 for inverting the input signal IN and the first node n1 and the power source voltage VDD and receives the power source voltage VDD at the bulk terminal A first PMOS transistor P1 receiving the input signal IN at the gate terminal thereof; a second PMOS transistor P1 connected between the second node n2 and the power source voltage VDD and receiving the power source voltage VDD at the bulk terminal thereof, The second PMOS transistor P2 receives the output signal of the inverter IV1. The first PMOS transistor P2 is connected between the first node n1 and the third node n3. The PMOS transistor P2 receives the power supply voltage VDD at its bulk terminal, The third PMOS transistor P3 receives the second voltage VSS. The third PMOS transistor P3 receives the second voltage VSS. The second PMOS transistor P3 is connected between the second node n2 and the fourth node n4. A fourth PMOS transistor P4 receiving the voltage VSS and a fifth node n5 connected between the third node n3 and the fifth node n5 and receiving the power supply voltage VDD at the bulk terminal and receiving the input signal IN A first NMOS transistor N1 receiving the power supply voltage VDD at the bulk terminal thereof and a second NMOS transistor N3 connected between the fourth node n4 and the sixth node n6, A second NMOS transistor N2 receiving the output signal, a fifth node n5 connected between the first voltage VBB and the first voltage VBB at the bulk terminal, and a fourth node n4 And a fifth node N6 receiving the output signal of the third node N6 and a first voltage VBB connected to the sixth node n6 and receiving a first voltage VBB at a bulk terminal thereof, and a fourth NMOS transistor N4 receiving the output signal of the third NMOS transistor n3.

In the embodiment of the present invention, the second voltage VSS is a ground voltage and the first voltage VBB is a voltage of -3 V or less, which is a low back gate bias (LVBB). Here, the first voltage VBB is a voltage supplied from the internal voltage generator.

The operation of the control signal generator 110 will be described with reference to FIG.

The control signal generator 110 outputs the control signal OUT in response to the input signal IN. The control signal generator 110 outputs a high level control signal OUT when the input signal IN is input at a logic high level and outputs a low level control signal OUT when the input signal IN is input at a logic low level. . In an embodiment of the present invention, the input signal IN may be a test mode signal.

When the input signal IN is input to the control signal generator 110 at a logic high level, the first inverter IV1 inverts the input signal IN and outputs a logic low signal. The second PMOS transistor P2 receiving the output signal of the first inverter IV1 of the low level is turned on and outputs the power supply voltage VDD to the second node n2. The second PMOS transistor P4 is turned on because the second voltage VSS is at the ground voltage level and the second NMOS transistor N2 receiving the output signal of the first inverter IV1 of the low level is turned off, do. At this time, the output signal of the fourth node n4 becomes the high level, and the control signal OUT which is the output signal of the fourth node n4 becomes the logic high.

The first PMOS transistor P1 receiving the high level input signal IN is turned off. A third PMOS transistor P3 receiving the second voltage VSS, a first NMOS transistor N1 receiving the high level input signal IN and a fourth node n4 receiving the high level output signal The third NMOS transistor N3 is turned on. The first NMOS transistor N1 and the third NMOS transistor N3 are turned on to pull down the current from the third node n3 to the first voltage VBB and output the output signal of the third node n3 to the logic low I make it.

The fourth NMOS transistor N4 is turned off when the output signal of the third node n3 of the logic low is input to block the output signal of the fourth node n4 from being pulled down toward the first voltage VBB.

Next, when the input signal IN is input to the control signal generator 110 at a logic low level, the first inverter IV1 inverts the input signal IN and outputs a logic high signal. The first PMOS transistor P1 receiving the low level input signal IN is turned on and outputs the power supply voltage VDD to the first node n1. The third PMOS transistor P3 receiving the second voltage VSS is turned on and the first NMOS transistor N1 receiving the input signal IN of the high level is turned off and the third node n3 is turned off Level signal.

The second PMOS transistor P2 receiving the output signal of the first inverter IV1 of high level is turned off. A fourth PMOS transistor P4 receiving the second voltage VSS, a second NMOS transistor N2 receiving the output signal of the first inverter IV1 of high level, and a second NMOS transistor N2 receiving the output signal of the third node n3 of high level, The fourth NMOS transistor N4 is turned on. The second NMOS transistor N2 and the fourth NMOS transistor N4 are turned on to pull down the current from the fourth node n4 to the first voltage VBB. At this time, the output signal of the fourth node n4 becomes a low level, and the control signal OUT which is an output signal of the fourth node n4 becomes a logic low.

The third NMOS transistor N3 is turned off when the output signal of the fourth node n4 of the logic low is input.

The switch control circuit unit 120 according to the embodiment of the present invention will be described with reference to FIG.

The switch control circuit unit 120 includes a voltage enable signal generation unit 121 and a switch unit 122. [

The voltage enable signal generation section 121 includes a second inverter IV2 for inverting the control signal OUT, a first delay section 1211 and a second delay section 1212. [

The first delay unit 1211 includes a third inverter IV3 for inverting the output signal of the second inverter IV2, a fourth inverter IV4 for inverting the output signal of the third inverter IV3, A fifth PMOS transistor P5 connected between the power supply voltage VDD and the seventh node n7 and receiving the output signal of the fifth inverter IV5, A fifth NMOS transistor N5 which is connected between the node n7 and the first voltage VBB and receives the first voltage VBB at the bulk terminal and receives the output signal of the fifth inverter IV5 at the gate terminal thereof, .

The second delay unit 1212 includes a first NOR gate NR1 for logically operating an output signal of the second inverter IV2 and an output signal of the seventh node n7, A sixth PMOS transistor P6 which is connected between the power supply voltage VDD and the eighth node n8 and receives the output signal of the sixth inverter IV6 and a sixth PMOS transistor P6 which receives the output signal of the sixth inverter IV6 and a power supply voltage VDD, And a sixth NMOS transistor N6 which is connected between the first voltage VBB and receives the first voltage VBB at the bulk terminal thereof and receives the sixth inverter IV6 at the gate terminal thereof.

In the embodiment of the present invention, the output signal of the seventh node n7 is the first voltage enable signal VBBEN and the output signal of the eighth node n8 is the second voltage enable signal VSSEN.

The switch unit 122 includes a first switch circuit 1221 for outputting the first voltage VBB in response to the first voltage enable signal VBBEN and a second switch circuit 1221 for outputting the second voltage VBB in response to the second voltage enable signal VSSEN. And a second switch circuit 1222 for outputting a voltage VSS.

The first switch circuit 1221 is connected between the first voltage VBB and the output node B and receives the first voltage VBB at the bulk terminal and the first voltage enable signal VBBEN at the gate terminal And a receiving seventh NMOS transistor N7.

The second switch circuit 1222 is connected between the second voltage VSS and the output node B and receives the first voltage VBB at the bulk terminal and the second voltage enable signal VSSEN at the gate terminal And a receiving eighth NMOS transistor N8.

4 is a timing diagram of voltage switching circuit 100 in accordance with an embodiment of the present invention.

The operation of the switch control circuit unit 120 according to the embodiment of the present invention will now be described with reference to FIGS. 3 to 4. FIG.

Referring to FIG. 3, the operation of the switch control circuit 120 when the control signal OUT transitions from a low level to a high level in the embodiment of the present invention is as follows.

When the voltage switching circuit 100 stops outputting the first voltage VBB and outputs the second voltage VSS, the control signal OUT transitions from a low level to a high level.

In the switch control circuit unit 120, the second inverter IV2 inverts when a high level control signal OUT is input and outputs a low level signal.

The output signal of the fifth inverter IV5 becomes a high level when the output signal of the second inverter IV2 of the low level in the first delay unit 1211 passes through the third to fifth inverters IV3 to IV5. At this time, the fifth PMOS transistor P5 receiving the output signal of the high-level fifth inverter IV5 is turned off, the fifth NMOS transistor N5 is turned on, and the seventh node n7 is turned on. 1 voltage enable signal VBBEN.

In the second delay unit 1212, the first NOR gate NR1 performs logic operation on the low-level second inverter IV2 output signal and the low-level first voltage enable signal VBBEN to output a high-level signal do. The sixth inverter IV6 inverts the output signal of the first NOR gate NR1 to output a low level signal. At this time, the sixth PMOS transistor P6 receiving the output signal of the low-level sixth inverter IV6 is turned on, the sixth NMOS transistor N6 is turned off, and the high- 2 voltage enable signal VSSEN.

The switch unit 122 outputs the second voltage VSS to the output node B in response to the first voltage enable signal VBBEN of the low level and the second voltage enable signal VSSEN of the high level.

Referring to FIG. 4, when the control signal OUT transitions from a low level to a high level, the first voltage enable signal VBBEN is input to the second to fifth inverter IV5 and the fifth NMOS transistor N5, And transitions from a high level to a low level. The second voltage enable signal VSSEN is supplied to the first NOR gate NR1, the sixth inverter IV6 and the sixth PMOS transistor P6 after the first voltage enable signal VBBEN transits to the low level. And is transited from the low level to the high level. That is, when the control signal OUT transitions from the low level to the high level, the first delay unit 1211 and the second delay unit 1212 change the logic level transition time of the second voltage enable signal VSSEN 1 voltage enable signal VBBEN.

Here, the signal delay amounts of the respective inverters and the first N0 gate NR1 are the same, and the amount of signal delay of the fifth to sixth PMOS transistors P5 and P6 and the fifth to sixth NMOS transistors N5 and N6 is same.

3, the operation of the switch control circuit 120 when the control signal OUT transitions from a high level to a low level in the embodiment of the present invention is as follows.

When the voltage switching circuit 100 interrupts the output of the second voltage VSS and outputs the first voltage VBB, the control signal OUT transitions from the high level to the low level.

In the voltage enable signal generating section 121, the second inverter IV2 inverts when a low level control signal OUT is input, and outputs a high level signal.

The output signal of the fifth inverter IV5 becomes low level when the output signal of the second inverter IV2 of high level in the first delay unit 1211 passes through the third to fifth inverters IV3 to IV5.

At this time, the fifth PMOS transistor P5 receiving the output signal of the low-level fifth inverter IV5 is turned on, the fifth NMOS transistor N5 is turned off, and the seventh node n7 is turned off, 1 voltage enable signal VBBEN.

In the second delay unit 1212, the first NOR gate NR1 outputs a low level signal in response to the high level second inverter IV2 output signal. The sixth inverter IV6 inverts the output signal of the first NOR gate NR1 to output a high level signal. At this time, the sixth PMOS transistor P6 receiving the output signal of the high-level sixth inverter IV6 is turned off, the sixth NMOS transistor N6 is turned on, and the eighth node n8 is turned on 2 voltage enable signal VSSEN.

When the control signal OUT transitions from a high level to a low level, the second delay unit 1212 responds to the output signal of the second inverter IV2 regardless of the output signal of the first voltage enable signal VBBEN And changes the logic level of the second voltage enable signal VSSEN.

That is, the switch circuit controller 120 adjusts the logic level transition time of the first voltage enable signal VBBEN and the second voltage enable signal VSSEN according to the control signal OUT logic level transition. The logic level transition time of the first voltage enable signal VBBEN and the second voltage enable signal VSSEN is adjusted to respond to the first voltage enable signal VBBEN and the second voltage enable signal VSSEN The switch unit 122 simultaneously applies the first voltage VBB and the second voltage VSS to the output node B to prevent the overcurrent from flowing.

The logic level transition time of the first voltage enable signal VBBEN is fixed to the signal delay amounts of the second to fifth inverters IV2 to IV5 and the fifth PMOS transistor P5 or the fifth NMOS transistor N5.

However, the logic level transition time of the second voltage enable signal VSSEN is longer than that of the first NOR gate NR1, the second to sixth inverters IV2 to IV6, the fifth PMOS transistor P5, The second and sixth inverters IV2 and IV6 and the sixth NMOS transistor N6 are either longer or shorter than the signal delay of the transistor N5 and the sixth PMOS transistor P6 or the sixth NMOS transistor N6, 6 PMOS transistor P6 or the sixth NMOS transistor N6.

Referring to FIG. 4, when the control signal OUT transitions from a high level to a low level, the first voltage enable signal VBBEN is input to the second to fifth inverter IV5 and the fifth PMOS transistor P5, Level to transition from the low level to the high level. The second voltage enable signal VSSEN is supplied to the first NOR gate NR1, the sixth inverter IV6 and the sixth NMOS transistor N6 before the first voltage enable signal VBBEN transitions to the high level. And is transited from the high level to the low level. That is, when the control signal OUT transitions from a high level to a low level, the first delay unit 1211 and the second delay unit 1212 change the logic level transition time of the second voltage enable signal VSSEN 1 voltage enable signal VBBEN.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10: voltage switching circuit 11: control signal generating unit
12: switch control circuit part 100: voltage switching circuit
110: control signal generator 120: switch control circuit
121: Voltage enable signal generator 1211: Voltage enable signal generator 1211:
1212: second delay unit 122: switch unit
1221: first switch circuit 1222: second switch circuit

Claims (12)

A voltage enable signal generator for outputting a first voltage enable signal having the control signal fixedly delayed and a second voltage enable signal varying the control signal; And
A switch control circuit for outputting a first voltage or a second voltage in response to the first and second voltage enable signals; And
And a control signal generating section for outputting the control signal in response to an input signal.
◈ Claim 2 is abandoned due to payment of registration fee. The method according to claim 1,
Wherein the first voltage is lower in voltage level than the second voltage.
◈ Claim 3 is abandoned due to the registration fee. The method according to claim 1,
The control signal generator
And said control circuit outputs said control signal by buffering said input signal.
◈ Claim 4 is abandoned due to the registration fee. The method of claim 3,
The input signal
And a test mode signal.
◈ Claim 5 is abandoned due to the registration fee. 3. The method of claim 2,
The switch control circuit section
A first switch circuit for outputting the first voltage in response to the first voltage enable signal; And
And a second switch circuit for outputting the second voltage in response to the second voltage enable signal.
◈ Claim 6 is abandoned due to the registration fee. 3. The method of claim 2,
The voltage enable signal generator
A first delay unit for delaying the control signal and outputting the first voltage enable signal; And
And a second delay unit delaying the control signal and the first voltage enable signal to output the second voltage enable signal.
◈ Claim 7 is abandoned due to registration fee. The method according to claim 6,
The second delay unit
When the switch control circuit part stops the output of the first voltage and outputs the second voltage in response to the control signal, after completing the delay of the first voltage enable signal in the first delay part, 2 < / RTI > voltage enable signal.
◈ Claim 8 is abandoned due to the registration fee. The method according to claim 6,
The second delay unit
Wherein when the switch control circuit stops the output of the second voltage in response to the control signal and outputs the first voltage, the first delay unit may delay the first voltage enable signal before starting the delay of the first voltage enable signal. And outputs a second voltage enable signal.
A voltage enable signal generator for generating a first voltage enable signal having a fixed logic level transition time and a second voltage enable signal having a logic level transition time varying in accordance with a logic level transition of the control signal; And
A switch control circuit for outputting a first voltage or a second voltage in response to the first and second voltage enable signals; And
And a control signal generating section for outputting the control signal in response to an input signal.
◈ Claim 10 is abandoned due to the registration fee. 10. The method of claim 9,
Wherein the first voltage is lower in voltage level than the second voltage.
◈ Claim 11 is abandoned due to registration fee. 11. The method of claim 10,
The voltage enable signal generator
Wherein when the switch control circuit stops outputting the first voltage and outputs the second voltage in response to the control signal, the logic level transition time of the second voltage enable signal is higher than the logic level transition time of the first voltage enable signal Wherein the logic level transition time is longer than the logic level transition time.
◈ Claim 12 is abandoned due to registration fee. 10. The method of claim 9,
The voltage enable signal generator
Wherein when the switch control circuit stops outputting the second voltage and outputs the first voltage in response to the control signal, the logic level transition time of the second voltage enable signal is higher than the logic level transition time of the first voltage enable signal Level transition time is shorter than a logic level transition time.

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