KR100272526B1 - Atd pulse grnerator - Google Patents

Abstract

An ATD pulse generator which minimizes the layout area, wherein the ATD pulse generator includes an input circuit unit, an address generator, and an ATD pulse generator, wherein the output of the input circuit unit is input to a gate. A first N-MOS transistor having Vcc input to the source, an output of the address generator being input to the gate, a drain of the first N-MOS transistor connected to the drain, and a second N-MOS transistor having Vss input to the source; A 3N-MOS transistor, an output of which is input to a gate and Vss is input to a source, a drain and a source of a 3N-MOS transistor are connected, a source of the 1N-MOS transistor is connected to a gate, and Vcc is input to a drain. A fifth N-MOS transistor, an output of the address generator is input to a gate, and a drain of the fifth N-MOS transistor The 4N-MOS transistor is connected to the source and Vss is input to the source, and the inverter is connected to the drain of the 5N-MOS transistor, so that the layout area can be minimized and the pulse width can be easily adjusted.

Description

HT pulse generator

The present invention relates to a pulse generator, and more particularly, to an address transition detection (ATD) pulse generator.

As shown in FIG. 1, the ATD pulse generator according to the related art includes an input circuit part 1, a first address generator 2 outputting an address according to a signal input through the input circuit part 1, The second address generator 3 outputs the inverted address, and the ATD pulse generator 4 detects a transition of the address and generates an ATD pulse, that is, an address transition detection pulse.

At this time, the input circuit unit 1 is composed of the P-MOS transistors PM1 and PM2 and the N-MOS transistor NM1 to operate as an inverter when the chip enable signal is 'high' and is inputted through the input pad AX. Invert the signal.

The ATD pulse generator 4 may include a delay unit 11 and a delay unit for delaying the output of the first to third inverters I1, I2, and I3, and the output of the first inverter I1 for a predetermined time. 11 and the first and second transmission gates TG1 and TG2 operating according to the output of 11) or the output of the second inverter I2.

Looking at the operation of the ATD pulse generator according to the prior art configured as described above are as follows.

First, when the chip select signal CE of the 'high' level is input, the input circuit unit 1 operates as an inverter as the P-MOS transistor PM2 is turned on to invert the signal input through the input pad AX. Output

Subsequently, the signal output from the input circuit unit 1 is inverted again through the three stage inverter and input to the first and second address generators 2 and 3.

The first address generator 2 outputs the input signal as an address signal via four inverters, and the second address generator 3 inverts the input signal through the five inverters. To the output.

On the other hand, the ATD pulse generator 4 is output from the input circuit unit 1 and receives a signal via the two-stage inverter and whenever a transition of the address signal occurs, that is, a transition of the output signal of the input circuit unit 1 occurs, 'high' It is configured to generate a 'level pulse, the detailed operation of which will be described with reference to FIG.

First, since the output of the input circuit unit 1 is inverted through the first inverter I1 to the original level through the two-stage inverter, the waveform of the node 'N1' is the state in which the output of the input circuit unit 1 is inverted.

Subsequently, the output of the first inverter I1 is delayed for a predetermined time by the delay unit 11 to represent an output waveform such as the node 'N2'.

The output of the retarder 11 is inverted through the second inverter I2 to represent an output waveform such as the node 'N3'.

On the other hand, the output waveforms of the nodes 'N2' and 'N3' are input to the control gates of the first and second transmission gates TG1 and TG2 to output the same waveforms as the node 'N4'.

At this time, the first transmission gate TG1 outputs a signal corresponding to the node 'N1' when the node 'N2' is 'high' and when the node 'N3' is 'low', and the second transmission gate TG2 is a node. The first input signal is output when 'N2' is 'low' and when node 'N3' is 'high'.

In other words, when the output of the input circuit unit 1 is 'high', the node 'N2' and the node 'N3' are 'low' and 'high', respectively, so that the second transmission gate TG2 is turned on, as shown in the node 'N4'. When outputting 'high' and the output of the input circuit section 1 transitions to 'low', the output 'low' of the input circuit section 1 is inverted by the first inverter I1 and delayed by the retarder 11. The second transmission gate TG2 remains turned on while the output waveform of the node 'N4' transitions to 'low' during the operation.

Subsequently, the 'high' signal delayed through the delay unit 11 turns on the first transmission gate TG1 and turns off the second transmission gate TG2, so the output waveform of the node 'N4' transitions back to 'high'. .

In addition, since the output waveform of the node 'N4' is inverted by the third inverter I3, the ATD pulse generator 4 finally has a 'high' level pulse of a period corresponding to the delay time of the delay unit 11, Output the address transition detection signal.

Subsequently, even when the output signal of the input circuit unit 1 transitions from 'low' to 'high', the address detection signal corresponding to the delay time of the delay unit 11 is output by the above-described operation.

The ATD pulse generator according to the prior art has a problem in that it uses a large number of inverters and transmission gates as delay elements and adds a delay unit to increase the pulse width, thus occupying a wide layout area.

Accordingly, an object of the present invention is to provide an ATD pulse generator capable of minimizing the layout area, which has been devised to solve the above-described problems.

1 is a circuit diagram showing the configuration of an ATD pulse generator according to the prior art

FIG. 2 is a waveform diagram illustrating each sub waveform of FIG. 1.

Figure 3 is a circuit diagram showing the configuration of the ATD pulse generator according to the present invention

FIG. 4 is a waveform diagram illustrating an angle waveform of FIG. 3.

Explanation of symbols for main parts of the drawings

1: input circuit part 2: first address generating part

3, 30: second address generator 4, 40: ATD pulse generator

The ATD pulse generator includes an input circuit unit, an address generator, and an ATD pulse generator, wherein the ATD pulse generator comprises: a first N-MOS transistor in which an output of the input circuit unit is input to a gate and Vcc is input to a source; The output of the address generator is input to the gate, the drain and the drain of the first N-MOS transistor is connected, the second N-MOS transistor, Vss is input to the source, the output of the input circuit is input to the gate and Vss is input to the source A fifth N-MOS transistor connected to a source of the third N-MOS transistor, a drain of the third N-MOS transistor, a source of the first N-MOS transistor connected to a gate, and a Vcc input to a drain; A fourth N-MOS transistor, in which a negative output is input, a drain thereof is connected to a source of the fifth N-MOS transistor, and a Vss is input to the source; And a second inverter connected to a drain and a 5N-MOS transistor characterized by a composed.

Hereinafter, an ATD pulse generator according to the present invention will be described with reference to the accompanying drawings.

3 is a circuit diagram showing the configuration of the ATD pulse generator according to the present invention, Figure 4 is a waveform diagram showing the angular waveform of FIG.

In the ATD pulse generator according to the present invention, as shown in FIG. 3, an input circuit unit 1, a first address generator 2 for outputting an address according to a signal input through the input circuit unit 1, and an inversion And a second address generator 30 for outputting the address, and an ATD pulse generator 40 for detecting an address transition and generating an address transition detection pulse.

At this time, the ATD pulse generator 40 has an output of the first N-MOS transistor NM30 and the output of the second address generator 30, in which the output of the input circuit unit 1 is input to the gate via two stage inverters. A second N-MOS transistor NM40 that is input to the first N-MOS transistor NM30 and a drain is connected to the gate, 'Vss' is input to a gate, 'Vcc' is input to a source, and a drain is input to the first N-MOS transistor NM30. A drain of the first P-MOS transistor PM30 connected to the source of the transistor NM30, the third N-MOS transistor NM50 at which the output of the input circuit unit 1 is input to the gate, and the drain of the third N-MOS transistor NM50. And a source are connected to a gate of the fifth N-MOS transistor NM70 connected to a drain of the first P-MOS transistor PM30, and an output of the second address generator 30 is input to a gate thereof, and a drain thereof is formed of the fifth N-MOS transistor NM70. 4th N-MOS transistor connected to the source of 5N-MOS transistor NM70 The inverter N4 is connected to the drain NM60 and the drain of the fifth N-MOS transistor NM70.

The operation of the ATD pulse generator configured as described above will be described with reference to FIG. 4.

First, the output of the input circuit unit 1 is input to the gate of the first N-MOS transistor NM30.

Since the output waveform of the node 'N1' is the output waveform of the second address generator 30, the output waveform of the node 'N1' is delayed for a predetermined time compared to the output waveform of the input circuit unit 1 by the delay time of the internal 5-stage inverter.

Meanwhile, since the first P-MOS transistor PM30 is always turned on, the output waveform of the node 'N2' is the first and second N-MOS transistors NM30 (NM40) simultaneously turned on, that is, the input circuit unit 1 It is 'low' only when the output of) and the output waveform of node 'N1' are 'high' at the same time.

Since the second P-MOS transistor PM40 is always turned on, the output waveform of the node 'N3' is that the fifth N-MOS transistor NM70 is turned on and the third or fourth N-MOS transistor NM50 or NM60 is turned on. In the turn-on state, that is, when the output waveform of the node 'N2' is 'high' and the output waveform of the input circuit unit 1 or the output waveform of the node 'N1' is 'high', it is 'low'.

Therefore, when the output of the input circuit unit 1 transitions from 'high' to 'low', the 'low' signal of the second address generator 30 is turned off and the delayed time is compared with the first N-MOS transistor NM30. The second N-MOS transistor NM40 and the fourth N-MOS transistor NM60 are turned off after a predetermined time.

In addition, since the first and second N-MOS transistors NM30 and NM40 are connected in series, the node 'N2 is turned on according to the turn-off of the first N-MOS transistor NM30 regardless of the turn-off of the second N-MOS transistor NM40. The output waveform of 'will transition from' low 'to' high '.

Subsequently, as the node 'N2' transitions to 'high', the node 'N3' transitions to 'low' because the fifth N-MOS transistor NM70 is turned on and the fourth N-MOS transistor NM60 is turned on.

At this time, the output of the input circuit unit 1 transitioned to 'low', but the second address generator 30 instead of the 'low' signal, which is the output of the input circuit unit 1 at the current stage, to the gate of the fourth N-MOS transistor NM60. The node 'N3' maintains the 'low' level during the delay time since the 'high' signal of the previous stage delayed is input.

When the 'low' signal of the input circuit unit 1 is input to the fourth N-MOS transistor NM60 via the second address generator 30, the output waveform of the node 'N3' transitions to 'high'.

Subsequently, the output of the node 'N3' is inverted by the inverter I4 so that an address transition detection signal having a 'high' level is finally output.

On the other hand, when the output of the input circuit unit 1 transitions from 'low' to 'high', the 'high' signal of the second address generator 30 is turned on and delayed for a predetermined time compared to the first N-MOS transistor NM30. The second N-MOS transistor NM40 and the fourth N-MOS transistor NM60 are turned on after a predetermined time.

Since the first and second N-MOS transistors NM30 and NM40 are connected in series, the output waveform of the node N2 is 'high' until both the first and second N-MOS transistors NM30 and NM40 are turned on. Keep it.

Therefore, even when the output of the input circuit unit 1 transitions to 'high', the node N2 remains 'high' during the delay time of the second address generator 30 so that the fifth N-MOS transistor NM70 is turned on. Since the third N-MOS transistor NM50 is turned on by receiving the output 'high' of the input circuit unit 1, the output waveform of the node 'N3' transitions to 'low'.

Subsequently, the second N-MOS transistor NM40 receives the output 'high' of the input circuit unit 1 delayed by the second address generator 30 and is turned on, and the node 'N2' transitions to 'low' and thus the fifth NN. Since the MOS transistor NM70 is turned off, the output waveform of the node 'N3' transitions back to 'high'.

Subsequently, the output of the node 'N3' is inverted by the inverter I4 so that an address transition detection signal having a 'high' level is finally output.

The ATD pulse generator according to the present invention has the following effects.

First, since the address transition is detected by linking transistors, the layout area can be minimized.

Second, since the address transition detection pulse width is determined using the inverter delay stage of the address generator, it is easy to adjust the pulse width.

Claims (3)

An ATD pulse generator comprising an input circuit portion, an address generator and an ATD pulse generator, The ATD pulse generator comprises: a first N-MOS transistor having an output of the input circuit unit input to a gate and a Vcc input to a source; A second N-MOS transistor having an output of the address generator input to a gate, a drain of the first N-MOS transistor connected to a drain, and a Vss input to a source; A third N-MOS transistor having an output of the input circuit unit input to a gate and a Vss input to a source; A fifth N-MOS transistor having a source and a drain connected to the third N-MOS transistor, a source of the first N-MOS transistor connected to a gate, and a Vcc input to the drain; A fourth N-MOS transistor having a gate of which an output of the address generator is input, a drain of which is connected to a source of the fifth N-MOS transistor, and a Vss of a source thereof; ATD pulse generating device comprising an inverter connected to the drain of the fifth N-MOS transistor. The method of claim 1, A first P-MOS transistor for inputting Vcc to the source of the first N-MOS transistor is connected to a drain of the source of the first N-MOS transistor, Vss is connected to the gate, Vcc is connected to the source and always turned on ATD pulse generator, characterized in that connected. The method of claim 1, A second P-MOS transistor for inputting Vcc to a source of the first N-MOS transistor is connected to a drain of the 5N-MOS transistor, a Vss is connected to a gate, a Vcc is connected to a source, and is always turned on. ATD pulse generator, characterized in that connected.