KR100365940B1 - Clock buffer circuit of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock buffer circuit of a semiconductor device. In particular, an intermediate driver does not use an inverter and uses a MOS transistor to reduce the area of a chip and appropriately configure logic to form a clock tree suitable for a dynamic circuit. A clock buffer circuit for configuring the apparatus, comprising: a trigger clock generator for outputting a trigger clock using a latch clock in which an external clock and an internal clock are latched; A driver configured to drive a ground voltage according to a trigger clock output from the trigger clock generator; An internal clock generator for generating an internal clock using a delay circuit for delaying a signal driven by the driver for a predetermined time; And a latch controller controlled by the external clock and the trigger clock to latch the internal clock and output the latch clock to the trigger clock generator.

Description

Clock Buffer Circuit of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock buffer circuit of a semiconductor device. In particular, an intermediate driver does not use an inverter and uses a MOS transistor to reduce the area of a chip and appropriately configure logic to form a clock tree suitable for a dynamic circuit. It relates to a clock buffer circuit for configuration.

1 is a conventional clock buffer circuit, and includes a first NAND gate ND1 and a second NAND gate ND2 for receiving an external clock-in EX-CLK and a power supply voltage Vcc, respectively, and the first NAND. First, second, and third inverters IV1, IV2, and IV3 connected in series between the gate ND1 output terminal and the first internal clock CLK1 output terminal, and the second NAND gate ND2 output terminal and the second terminal. Fourth, fifth, and sixth inverters IV4, IV5, and IV6 connected in series between the internal clock CLK2 output terminals.

In the conventional clock buffer circuit having the above-described structure, the size of the third and sixth inverters, which are the final stage inverters, is increased in order to increase the driving force, so that the first, second, fourth, and fifth inverters of the previous stages (IV1). , IV2, IV4, IV5) should be made larger.

Therefore, the area of the chip is increased, which is somewhat inconvenient for use in a dynamic circuit.

In addition, in the case of the One Zero Detector circuit, an operation error occurs when the battery is precharged in the "low" section of the clock and sufficient setup time is not obtained from the combinational circuit when it is active in the "high" section of the clock. There was a problem that occurred.

Accordingly, the present invention has been made to solve the above-mentioned problems. The clock buffer circuit is suitable for a dynamic circuit by configuring the driver as a MOS transistor, reducing the chip area, and adjusting the clock pulse width using a delay circuit. The purpose is to provide.

1 is a clock buffer circuit of a semiconductor device according to the prior art.

2 is a clock buffer circuit of a semiconductor device according to an embodiment of the present invention.

3 is an operation timing diagram of FIG. 2.

<Description of the symbols for the main parts of the drawings>

10: trigger clock generator 20: latch control

22: latch portion 30, 40: internal clock generator

32, 42: delay part EX_CLK: external clock

TCLK: Trigger clock CLK1, CLK2: Internal clock

N1, N2, N3, N4: Node

The clock buffer circuit of the present invention for achieving the above object includes a trigger clock generator for outputting a trigger clock using a latch clock of the external clock and the internal clock; A driving unit driving a ground voltage according to a trigger clock output from the trigger clock generator; An internal clock generator for generating the internal clock using a delay circuit for delaying a clock driven by the driver for a predetermined time; And a latch control unit controlled by the external clock and the trigger clock to latch the internal clock to output the latch clock to the trigger clock generator.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 2 illustrates a clock buffer circuit according to an embodiment of the present invention, and includes a trigger clock generator for outputting a trigger clock TCLK by using a latched signal on an external clock EX_CLK and a third node N3. 10 and the first and second drivers 34 and 44 which pull down the nodes N1 and N4 to ground voltages according to the trigger clock TCLK of the trigger clock generator 10, and the first and second drivers. First and second generating first and second internal clocks CLK1 and CLK2 using the first and second delay units 32 and 42 which delay a clock driven by the driving units 34 and 44 for a predetermined time. 2 is a latch control unit configured to latch the first internal clock CLK1 of the first internal clock generator 30 by being controlled according to the internal clock generators 30 and 40 and the external clock EX_CLK and the trigger clock TCLK. 20).

The trigger clock generator 10 inverts an NAND gate ND3 for logically combining an external clock EX_CLK and the latched signal N3 of the latch controller 20, and an output signal of the NAND gate ND3. Inverter IV7 outputs the trigger clock TCLK.

The first driver 34 includes an NMOS transistor MN1 driving the trigger clock TCLK by applying the trigger clock TCLK to a gate and a source connected to a ground voltage. Here, the second driver 44 also includes the NMOS transistor MN3 in the same manner as the first driver 34.

The first internal clock generator 30 is an inverter IN8 for inverting the potential of the node N1 driven by the first driver 34 to generate the first internal clock CLK1, and the inverter ( A first delay unit 32 for delaying the output signal of IV8) for a predetermined time, an inverter IV9 for inverting the output signal of the first delay unit 32, and an output signal of the inverter IV9 are connected to the gate. The power supply voltage Vcc is applied to the source, and the drain is configured of the PMOS transistor MP1 connected to the node N1.

Here, the second internal clock generator 40 also includes the inverters VI13 and IV14, the second delay unit 42, and the PMOS transistor MP3, similarly to the first internal clock generator 30. It is composed.

The latch control unit 20 is controlled by the trigger clock TCLK, and the NMOS transistor MN2 selectively transmits the signal N2 in which the first internal clock CLK1 is inverted by the inverter IV10. And latching a signal selectively transmitted by the NMOS transistor MN2. PMOS transistor for pulling up the output terminal N3 of the latch unit 22 to the power supply voltage Vcc according to the latch unit 22 including the inverters IV11 and IV12 and the external clock EX-CLK. It is comprised including (MP2).

Hereinafter, an operation relationship of the clock buffer circuit of the present invention having the above configuration will be described in detail with reference to the operation timing diagram of FIG. 3.

When the initial external clock EX_CLK is in the "low" state, the trigger clock TCLK of the trigger clock generator 10 is in the "low" state, and the node Nl of the first internal clock generator 30 is " High "state.

Accordingly, the first internal clock CLK1 is in the "low" state, the output node N2 of the inverter IV10 is in the "high" state, and since the trigger clock TCLK is "low", the latch control unit 20 NMOS transistor MN2 is turned off so that node N3 has an external clock EX_CLK in a low state, PMOS transistor MP2 is turned on and a power supply voltage Vcc is applied so that it is " high " It becomes a state.

In addition, since the trigger clock TCLK is in the "low" state, the NMOS transistor MN3, which is the second driver 44, is turned off so that the node N4 is in the "high" state, and thus the second internal clock CLK2. ) Is output as "low".

Subsequently, when the external clock EX_CLK transitions to "high," the third NAND gate ND3 of the trigger clock generator 10 may have a node "N3" in the "high" state, thus eventually triggering the clock clock generator 20. The trigger clock TCLK, which is the output of, is in a "high" state.

Therefore, the NMOS transistor MNl, which is the first driver 34, is turned on, so that the first node Nl drops to "low", and the trigger clock TCLK is in a "high" state. The NMOS transistor MN2 of the latch control unit 20 is turned on.

Subsequently, the "low" potential of the first node N1 is inverted by the eighth inverter IV8 to become a "high" potential, whereby the first internal clock CLK1 transitions to "high".

Meanwhile, since the first internal clock CLK1, which is the output of the eighth inverter IV8, is “high”, the first internal clock CLK1 is input to the tenth inverter IV10 and inverted to the “low” state.

Subsequently, since the trigger clock TCLK is in the "high" state, the NMOS transistor MN2 of the latch control unit 20 is turned on, and the output of the "low" state of the tenth inverter IV10 is latched. It is transmitted to 22 and latched. At this time, since the external clock EX-CLK is in a high state, the PMOS transistor MP2 is turned off.

Accordingly, the external clock EX_CLK in the "high" state and the signal in the "low" state latched in the latch unit 22 are input to the third NAND gate ND3 to transition the trigger clock TCLK back to "low". The NMOS transistor MN1 of the first internal clock generator 30 and the NMOS transistor MN2 of the latch controller 20 are turned off again.

On the other hand, when the potential of the first node Nl is in the "low" state, the first internal clock CLK1 in the "high" state is delayed by the first delay unit 32 for a predetermined time, and the inverter IV9 is applied to the inverter IV9. Inverted by the PMOS transistor MP1 to turn on, the first internal clock CLKl maintains a high state for a predetermined time.

3 shows such a signal flow relationship. When the trigger clock TCLK of (b) transitions from "low" to "high", the first internal clock CLKl of (f) transitions to "high" and triggers. Even when the clock TCLK falls back to "low", the first internal clock CLKl is maintained at the "high" state by the first delay unit 32. At this time, the clock at the second node N2 and the third node N3 is delayed by the same pulse width as that of the first internal clock CLKl as shown in (d) and (e). Maintain state.

Subsequently, when the external clock EX_CLK drops from "high" to "low", an input terminal of the third NAND gate ND3 has a "low" signal on the third node N3 and an "low" external clock EX_CLK. ), The trigger clock (TCLK) is still in the "low" state. Accordingly, the NMOS transistor MN1 of the first internal clock generator 30 and the NMOS transistor MN2 of the latch controller 20 are turned off.

On the other hand, when looking at the waveform on the first node (Nl), the trigger clock (TCLK) is a "high" state, the NMOS transistor (MN1) of the first driver 34 is turned on to turn on the first node (Nl). Make it "low".

Therefore, since the first internal clock CLKl is in the "high" state and the trigger clock TCLK is shifted to the "low" state through the latch control unit 20, the NMOS transistor which is the first driver 34 is a transistor. Turn off (MNl).

On the other hand, the first internal clock CLK1 in the "high" state is delayed by the first delay unit 32 for a predetermined time and the PMOS transistor MP1 is turned on so that the first node Nl is "high". To make the first internal clock CLK1 "low".

Here, the interval until the first internal clock CLK1 in the "high" state transitions to the "low" state is as long as the delay time ("delay" in FIG. 3) of the first delay unit 32.

On the other hand, since the second internal clock generating unit 40 generating the second internal clock CLK2 performs the same operation by the same configuration as the first internal clock generating unit 30, the second internal clock CLK2. ) Is the same as the waveform of the first internal clock CLK1.

Summarizing the operation of FIG. 2 described above, even if the first external clock EX_CLK transitions from "low" to "high", the internal clocks CLK1 and CLK2 are reset even if the pulse of the trigger clock TCLK rises and falls again. The first and second delay units 32 and 42 maintain a "high" state for a predetermined time and then transition to "low". At this time, the delay time is the magnitude of the pulse width of the external clock EX_CLK. In the present invention, the internal clocks CLKl and CLK2 are synchronized with the external clock EX_CLK to generate a clock pulse whose pulse width is appropriately determined by the delay value. This makes it possible to construct a clock tree suitable for dynamic circuits.

In addition, since the eighth inverter IV8, which is the final stage inverter, is driven by the first NMOS transistor MNl, the drive size of the seventh inverter IV7 is about 1 when driving an inverter composed of NMOS and PMOS. Since the size is about / 3, the clock tree can be configured with a smaller area, and sufficient setup time can be secured according to the delay value, so that the logic suitable for the dynamic circuit can be configured.

As described above, the present invention has a useful effect in the high-speed operation of the chip by making the clock tree suitable for the dynamic circuit by reducing the area of the chip and configuring the logic appropriately by using the MOS transistor instead of the inverter in the intermediate stage driver.

Preferred embodiments of the present invention are for the purpose of illustration and various modifications, changes, alternatives and additions will be possible to those skilled in the art through the spirit and scope of the present invention as set forth in the appended claims.

Claims (4)

A trigger clock generator configured to output a trigger clock using a latch clock in which an external clock and an internal clock are latched; A driving unit driving a ground voltage according to a trigger clock output from the trigger clock generator; An internal clock generator for generating an internal clock using a delay circuit for delaying a signal driven by the driver for a predetermined time; And And a latch control unit controlled by the external clock and the trigger clock to latch the internal clock to output the latch clock to the trigger clock generator. The method of claim 1, The driving unit, And an NMOS transistor having a gate applied to the gate from the trigger clock generator, a drain connected to an input terminal of the internal clock generator, and a source connected to a ground voltage. The method of claim 1, The internal clock generator, Inverting means for inverting the clock driven by the driving unit to generate the internal clock; Delay means for delaying the internal clock for a predetermined time; And And a PMOS transistor having a clock applied to the gate by the delay means, a source connected to a power supply voltage, and a drain connected to an input terminal of the inverting means. The method of claim 1, The latch control unit, An NMOS transistor for selectively transmitting the internal clock as the trigger clock is applied to and controlled by a gate; Latch means for latching an internal clock selectively transmitted by the NMOS transistor; And And a PMOS transistor having a gate connected to an external clock, a source connected to a power supply voltage, and a drain connected to an output terminal of the latching means.