KR100973720B1 - Latch circuit for semiconductor memory device - Google Patents

Abstract

The present invention relates to a latch circuit capable of performing a latch operation normally regardless of a state change of an input signal. The latch circuit of the present invention is characterized in that, in the cross-coupled latch, the current path is connected from the output node to the ground power supply, and the latch operation is continuously performed regardless of the state change of the input signal. . According to this configuration, the present invention always generates a certain level of output signal while the cross-couple latch operation is not stopped even when the hold time of the input signal is insufficient. Accordingly, the present invention solves the limitation of the hold time required in the latching operation, and has the effect of suppressing the occurrence of an uncertain level of output.

Semiconductors, Memory Devices, Latches, Hold Time, Cross-Coupled

Description

LATCH CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE

The present invention relates to a semiconductor memory device, and more particularly, to a latch circuit capable of performing a latch operation normally regardless of a state change of an input signal.

BACKGROUND ART A latch circuit commonly used in a semiconductor memory device uses a method of inputting and outputting data in synchronization with a rising or falling edge of a clock signal.

In the data latch that receives data using the clock signal, the data signal must be input before a certain period before the transition point of the clock signal for the stable data latch, and the data signal must be input for a certain period after the transition point of the clock signal. The input must continue. At this time, the time at which the data signal is input before a predetermined period before the clock signal transition point is referred to as a setup time of the data signal. The time at which the data signal is input for a certain period after the clock signal transition time is called a hold time of the data signal.

Therefore, in order to stably latch data to the data latch latched in synchronization with the clock signal, data must be input before the clock signal setup timing interval. Likewise, data input can be reliably latched in the data latch only if data input is maintained for at least the hold timing period.

1 shows a latch circuit of a semiconductor memory device according to the prior art.

Conventional latch circuits include NMOS transistors 17 and 18 that form an input stage for large data input, and a precharge unit that receives a clock signal and precharges the supply voltage VDD to the output nodes OUT and OUTB. The PMOS transistors 10, 14, and the PMOS transistors 11, 12, 13, and the NMOS transistors 15, which constitute a latch unit which cross-couples and latches signals of the output nodes OUT and OUTB. 16) and an NMOS transistor 19 which is a switching transistor for controlling a power source in response to a clock signal.

The conventional latch circuit configured as described above is a latch having a differential cross-coupled input of a general type, and operates the latch unit by varying the ratio of the transconductance of a transistor receiving data to a difference of an input signal. .

That is, the signal is activated by the clock signal CLOCK, and the input signal IN is latched and output in the activated state. When the clock signal transitions to a high state, the input signal IN is input to generate output signals OUT and OUTB.

For example, when both the clock signal CLOCK and the input signal IN remain low, the PMOS transistors 10 and 14 connected to the power supply have the turn-on state and the output nodes OUT and OUTB. Precharged to In this operation, the latch unit latches a logic high value. Since the NMOS transistor 19 forming the current path has a turn-off state, the output signal OUT maintains the latch value (logical high value) of the output node OUT regardless of the input signal.

As shown in FIG. 2, when the clock signal CLOCK is switched to the high state and the input signal IN continues to be low, the NMOS transistor 17 at the input terminal is turned off. In addition, the NMOS transistor 18 at the input stage has a turn-on operating state. Since the clock signal is high, the NMOS transistor 19 also has a turn-on operating state. At this time, the current path to the ground power supply is formed through the NMOS transistors 18 and 19, thereby making the latch value of the latch portion a logic low value. Therefore, the output signal OUT transitions to the low state.

In this state, the clock signal CLOCK continues to be in a high state, and when the input signal IN transitions to a high state, the NMOS transistor 17 of the input terminal is turned on. The NMOS transistor 18 at the input is turned off. At this time, the output signal OUT continues to be low.

When the clock signal CLOCK transitions from a high state to a low state and the input signal IN continues to be in a high state, the precharge operation is performed again as the PMOS transistors 10 and 14 are turned on. As a result, the output signal OUT is switched to the high state.

In this manner, the conventional latch circuit is activated by the clock signal CLOCK, and latches and outputs the input signal IN in the activated state. When the clock signal transitions to a high state, the input signal IN is input to generate output signals OUT and OUTB.

However, the conventional latch circuit has a problem that an error occurs in the output signal when the hold time is not sufficient, as shown in FIG.

That is, the NMOS transistors 17 and 18 constituting the input terminal sense a input signal or perform a current path function for a latch operation. For example, as shown in FIG. 2, when the hold time is sufficient, no error occurs in sensing and latching of the input signal.

However, as shown in FIG. 3, when the hold time is not sufficient, a malfunction occurs that causes an output data error or causes excessive power to flow. This occurs because the NMOS transistors 17 and 18 constituting the input stage do not perform the function of the current path for the latch operation in the specific portion during the operation function.

Accordingly, an object of the present invention is to provide a latch circuit of a semiconductor memory device in which a current path function for a latch operation can be normally performed regardless of a change in an input state in a cross-coupled latch. .

In the latch circuit of the semiconductor memory device according to the present invention for achieving the above object, in the latch of the cross-couple method, to form a current path from the output node to the ground power supply, the latch operation regardless of the state change of the input signal It characterized in that it comprises a latch circuit for controlling to be made continuously.

In addition, the latch circuit according to another embodiment of the present invention, the precharge unit for precharging the power supply voltage to the output node; An input unit for inputting a differential input signal; A latch unit configured to latch a value of the output node in response to a differential input of the input unit when a clock signal is enabled; It characterized in that it comprises a current path portion for forming a current path connected from the output node to the ground power source.

In the latch circuit of the present invention, in the cross-coupled latch, the current path is connected from the output node to the ground power source, and the latch operation is continuously performed regardless of the state change of the input signal. do. According to this configuration, the present invention always generates a certain level of output signal while the cross-couple latch operation is not stopped even when the hold time of the input signal is insufficient. Accordingly, the present invention solves the limitation of the hold time required in the latching operation, and has the effect of suppressing the occurrence of an uncertain level of output.

Hereinafter, a latch circuit of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

4 illustrates a latch circuit diagram of a semiconductor memory device according to an embodiment of the present invention.

The latch circuit of the present invention is precharged to the input unit 80 for inputting data, the precharge unit 50 for precharging the supply voltage VDD to the output nodes OUT and OUTB, and the output nodes OUT and OUTB. A latch unit 60 and 70 of a cross-coupling system in which one side of the signal transitions from the current potential to the other side in response to the differential input of the input unit 80, and the latch unit 60 NMOS transistor which is a switching transistor for controlling a power source in response to a clock signal, and a current path unit 90 for forming a current path so that 70 can always perform a latch operation regardless of a change in an input signal of the input unit 80. It comprises a 31.

The input unit 80 includes two NMOS transistors 27 and 30, inputs input signals IN and INB to gate terminals, a drain terminal is connected to the latch unit 70, and a source terminal is The common terminal is connected to the drain terminal of the NMOS transistor 31 at the same time. The input unit 80 differentially inputs signals IN and INB through the two transistors. In addition to the function of inputting a signal, the input unit 80 also serves as a current path for the latch operation of the latch units 60 and 70.

The NMOS transistor 31, which is the switching transistor, receives a clock signal CLOCK through a gate terminal, and a source terminal is connected to a ground power source. The switching transistor is configured to control the latch unit to perform a latch operation in synchronization with a clock signal.

The current path unit 90 is connected to the input unit 80 to assist the current path function of the input unit 80. To this end, the NMOS transistor 28 is commonly connected to the drain terminal and the source terminal of the NMOS transistor 27, and the gate terminal is connected to the latch unit, and the drain terminal and the source terminal of the NMOS transistor 30 are common to each other. And an NMOS transistor 29 having a gate end connected to the latch unit.

The NMOS transistor 28 is particularly suitable for performing the current path function for the latch operation of the latch parts 60 and 70 even when the transistor 27 of the input part 80 temporarily fails to perform the current path function. Element. Similarly, the NMOS transistor 29 performs a current path function for the latch operation of the latch parts 60 and 70, especially when the transistor 30 of the input part 80 temporarily does not perform the current path function. It is an element for doing this.

The precharge unit 50 is composed of two PMOS transistors 20 and 24 connected to a supply power source. The PMOS transistors 20 and 24 are configured to receive a clock signal through a gate terminal, and precharge the power supply voltage to the output nodes OUT and OUTB in synchronization with the clock signal.

The latch units 60 and 70 are connected in a cross-coupled manner. Although the latch units 60 and 70 are divided into two blocks in the drawing, this is for convenience of description, and the latch units 60 and 70 operate in conjunction with each other. The latch unit 60 includes three PMOS transistors 21, 22, and 23. One PMOS transistor 22 inputs a clock signal to the gate terminal, and connects the gate terminals of the PMOS transistors 21 and 23 to the source terminal and the drain terminal, respectively. The PMOS transistor 21 is connected between a supply power supply and an output node OUTB, and the other PMOS transistor 23 is connected between a supply power supply and an output node OUT. The gate terminals of the PMOS transistors 21 and 23 are connected to the output nodes OUT and OUTB in a cross-coupled manner. The latch unit 70 is composed of two NMOS transistors 25 and 26. The NMOS transistors 25 and 26 are connected in a cross-coupled manner between the output nodes OUTB and OUT and the input unit 80.

The following describes the operation of the latch circuit according to the present invention configured as described above.

The present invention is a latch having a differential input of a cross-couple method, and operates the latch unit by varying the ratio of the transconductance (TRANSCONDUCTANCE) of the transistor receiving data to the difference of the input signal.

That is, the signal is activated by the clock signal CLOCK, and the input signal IN is latched and output in the activated state. When the clock signal transitions to a high state, the input signal IN is input to generate output signals OUT and OUTB.

Therefore, when both the clock signal CLOCK and the input signal IN remain low, the PMOS transistors 20 and 24 connected to the supply power supply are turned on while the power supply to the output nodes OUT and OUTB is turned on. The voltage is precharged. In this operation, the latch sections 60 and 70 latch a logic high value. Since the NMOS transistor 31 forming the current path has a turn-off state, the output signal maintains the latch value (logical high value) of the output node OUT regardless of the input signal.

When the clock signal CLOCK transitions to a high state and the input signal IN continues to be in a low state, the NMOS transistor 27 of the input terminal has a turn-off operation state and the NMOS transistor 30 of the input terminal. Has a turn-on operating state. Since the clock signal is high, the NMOS transistor 31 also has a turn-on operating state. At this time, the current path to the ground power supply is formed through the NMOS transistors 30 and 31, thereby making the latch value of the output node OUT of the latch portion a logic low value. Therefore, the output signal OUT transitions to the low state.

In this state, the clock signal CLOCK continues to be in a high state, and when the input signal IN transitions to a high state, the NMOS transistor 27 at the input terminal is turned on. The NMOS transistor 30 at the input terminal is turned off. At this time, the output signal OUT continues to be low.

When the clock signal CLOCK transitions from the high state to the low state and the input signal IN continues to be in the high state, the PMOS transistors 20 and 24 are turned on and the precharge operation is performed again. As a result, the output signal OUT is switched to the high state.

On the other hand, the above operation is a case having a sufficient setup time and hold time. In this case, as in the prior art, the latch is normally operated normally. However, in the case where the hold time is not sufficient, a case of maintaining an output of an uncertain (UNCERTAIN) level as in FIG. 3 has conventionally occurred.

Even in such a case, the present invention performs the normal operation of the latch. That is, even when the clock signal is transitioned from the low state to the high state, and the input signal IN transitions from the low state to the high state in a state where sufficient hold time is not maintained, the present invention is shown in FIG. As shown, a complete low level output signal OUT is generated.

Looking at this operation in detail, when the clock signal is in a low state, the precharge unit 50 sufficiently precharges the power supply voltage to the output nodes OUT and OUTB. In this state, when the clock signal is enabled as the high signal, the high logic value latched to the latch units 60 and 70 is output.

However, the input signal IN has a low state and the other input signal INB has a high state opposite to the input signal. Therefore, while the high signal is applied to the gate terminal of the NMOS transistor 30, the NMOS transistor 30 is turned on.

In this operation, the current holding the high level latched to the output node OUT of the latch units 60 and 70 is already turned on by the NMOS transistor 30 in the turn-on state and the high logic clock signal. It flows to the ground power supply via the switching transistor 31 which has a state.

On the other hand, before the high level signal latched to the output node OUT flows sufficiently to the ground power supply through the NMOS transistor 30 and the switching transistor 31, the input signal IN transitions from the low state to the high state. A case of becoming occurs. At this time, the NMOS transistor 30 is turned off while the low signal corresponding to the input signal INB is provided to the gate terminal of the NMOS transistor 30.

However, the NMOS transistor 29 of the current path unit 80 which is connected in parallel with the NMOS transistor 30 and performs an auxiliary current path function remains turned on, thereby switching with the NMOS transistor 29. The current path through the transistor 31 is maintained. In this way, the high level signal latched to the output node OUT is sufficiently flowed to the ground power supply via the NMOS transistor 29 and the switching transistor 31, and the output signal of the latch units 60 and 70 is a low signal. Is converted to.

The operation state at this time is shown in FIG. Therefore, the present invention adds the current path unit 80, so that the latch operation is continuously performed regardless of the input signal change state of the input unit 80. Therefore, the output signal has no uncertainty. When the input signal is reversed, the NMOS transistor 28 of the current passage 80 serves as a secondary current passage.

The above-described preferred embodiment of the present invention is disclosed for the purpose of illustration, and may be applied to a case in which the cross-couple latch operation is always performed normally even when the hold time is not sufficient. Therefore, those skilled in the art will be able to improve, change, substitute or add other embodiments within the technical spirit and scope of the present invention disclosed in the appended claims.

1 is a configuration diagram of a latch circuit according to the prior art,

2 is an output waveform diagram of a latch according to the prior art,

3 is an output waveform diagram of a latch when a conventional hold time is not sufficient;

4 is a configuration diagram of a latch circuit according to an embodiment of the present invention;

5 is an output waveform diagram of a latch when the hold time is insufficient when the present invention is applied.

Explanation of symbols on the main parts of the drawings

50: precharge part 60, 70: latch part

80: input portion 90: current passage portion

Claims (12)

A latch circuit of a semiconductor memory device, comprising: forming a current path from an output node to a ground power source in a cross-coupled latch and controlling the latch operation to be continued regardless of a change in state of an input signal. A precharge unit for precharging the power supply voltage to the output node; An input unit for inputting a differential input signal; A latch unit configured to latch a value of the output node in response to a differential input of the input unit when a clock signal is enabled; And a current path portion forming a current path connected from the output node to a ground power source. The method of claim 2, And an enable part connected between the current path part and a ground power source. The method of claim 3, wherein And the enable part comprises a first NMOS transistor enabled by a clock signal. The method of claim 4, wherein And the input unit includes a second NMOS transistor connected between the output node and the first NMOS transistor and inputting an input signal to a gate terminal. The method of claim 5, And the current passage portion comprises a third NMOS transistor connected in parallel with the second NMOS transistor and connecting a gate end thereof to the latch portion. The method of claim 2, The precharge unit includes a PMOS transistor connected between a supply power supply and an output node. The method of claim 7, wherein And the PMOS transistor is configured to input a clock signal to a gate terminal. The method of claim 2, And the latch portion is of a cross-couple type. The method of claim 9, The latch unit includes a pair of PMOS transistors connected between a power supply and an output node; A pair of NMOS transistors connected between an output node and the current path unit; And a PMOS transistor connecting gate ends of the pair of PMOS transistors. The method of claim 10, And the gate terminal of the PMOS transistor connecting the gate terminals of the pair of PMOS transistors to input a clock signal. The method of claim 11, The current path unit is a semiconductor comprising a pair of NMOS transistors having a gate terminal connected to a gate terminal of the pair of PMOS transistors, and a source terminal and a drain terminal connected to a source terminal and a drain terminal of the NMOS transistor constituting the input unit. Latch circuit of the memory device.

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