KR20070109425A - Oscillator circuit - Google Patents

Abstract

An oscillator circuit is provided to implement a stable operation by a reference circuit for outputting a uniform period by varying the change of periods in a compensative direction by the external environment. An oscillator circuit(200) includes a first inverter(210) inverting a first input signal; a second inverter(220) inverting a second input signal; a reference circuit(230) generating a reference voltage varied according to power voltage(Vdd) and temperature change; a first comparator(CM1) comparing the output of the first inverter and the output of the reference circuit; a second comparator(CM2) comparing the output of the second inverter and the output of the reference circuit; and an SR(Set Reset) latch(240) generating a clock signal(clk) according to the output of the first and second comparators.

Description

Oscillator circuit

1 is a circuit diagram illustrating a conventional oscillator in detail.

2 is a circuit diagram showing in detail the oscillator of the present invention.

FIG. 3A is a graph comparing periodic changes according to changes in power supply voltages of the oscillator circuits of FIGS. 1 and 2.

FIG. 3B is a graph comparing period change according to temperature change of the oscillator circuit of FIGS. 1 and 2.

<Explanation of symbols for the main parts of the drawings>

210: first inverter 220: second inverter

230: reference circuit 240: SR latch

The present invention relates to an oscillator, and more particularly to an oscillator circuit with an SR-latch.

In general, an internal clock is used to operate internal devices in a memory or an IC chip. In flash memory, an internal clock is used in a microcontroller or a pump circuit, and the circuit for generating the internal clock is an oscillator circuit. The most basic circuit among oscillator circuits is a ring oscillator that connects an odd number of inverters in a ring structure to generate a clock. Although this structure is simple, the period may change significantly when PVT variations occur in the process, power supply voltage, and temperature. The period of the internal clock greatly affects the operation of the system. To improve this, many circuits are used that connect a constant current source to the inverter or include resistors, capacitors and a schmitt trigger or comparator to allow the RC delay effect to determine the period. However, even in this case, a change in the resistance value occurs due to a change in process, power supply voltage, temperature, and the like, and the period changes due to the change in the resistance value.

1 is a circuit diagram illustrating a conventional oscillator in detail. The oscillator 10 includes first and second inverters 11 and 12, first and second capacitors CP1 and CP2, a reference circuit 13, first and second comparators CR1 and CR2, and transistors ( P3 and N3) and SR latch 14. The first inverter 11 and the second inverter 12 receive the opposite signals INP and / INP, respectively, and apply signals to the first and second comparators CR1 and CR2 through the nodes K1 and K2. . The reference circuit 13 generates a reference voltage Vref and applies it to the first and second comparators CR1 and CR2. When the outputs of the first and second comparators CR1 and CR2 are changed, the signal input to the SR latch 14 is changed. As a result, the clock signal clk is changed. Therefore, the faster the cycle, the faster the discharge time of the inverters IN1 and IN2, that is, when the reference voltage Vref is high. In the reference circuit 13, when the power supply voltage Vdd is high, the voltage applied to the nodes K1 and K2 is also high. Then, the discharge time through the inverters IN1 and IN2 is increased. In addition, the clock signal clk period of the oscillator 10 decreases as the reference voltage Vref increases. Therefore, it can be seen that the clock signal clk period of the entire oscillator 10 according to the change of the power supply voltage Vdd is compensated for each other.

However, even when the temperature increases, the reference voltage Vref of the reference circuit 13 is output at a constant voltage, so that the period of the clock signal clk increases.

Therefore, the technical problem to be achieved by the present invention is to divide the period determining portion of the oscillator with the SR latch into two inputs of the comparator, the direction that the signals coming from the two inputs can compensate for the change in the period by the external environment The present invention provides an oscillator circuit having a reference circuit which is changed so that the overall period is constant.

The oscillator circuit according to the present invention for achieving the above technical problem, the first inverter for inverting the first input signal, the second inverter for inverting the second input signal, a reference variable that varies with power supply voltage and temperature change A reference circuit for generating a voltage, a first comparator for comparing an output of the first inverter and an output of the reference circuit, a second comparator for comparing an output of the second inverter and an output of the reference circuit, and the first comparator And an oscillator including an SR latch for generating a clock signal in accordance with the outputs of the first and second comparators.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2 is a circuit diagram showing in detail the oscillator of the present invention. The oscillator 200 includes first and second inverters 210 and 220, first and second capacitors C1 and C2, a reference circuit 230, first and second comparators CM1 and CM2, and transistors ( PT3 and NT5) and SR latch 240. The first inverter 210 includes a PMOS transistor PT1, an NMOS transistor NT1, and a resistor R1. The PMOS transistor PT1 is connected between the power supply voltage Vdd and the first node D1 to operate in response to the input signal INP. The NMOS transistor NT1 is connected between the first node D1 and the ground voltage Vss to operate in response to the input signal INP. The resistor R1 is connected between the first node D1 and the NMOS transistor NT1 to generate a delayed signal L1. The second inverter 220 includes a PMOS transistor PT2, an NMOS transistor NT2, and a resistor R2. The PMOS transistor PT2 is connected between the power supply voltage Vdd and the second node D2 to operate in response to the half input signal / INP. The NMOS transistor NT2 is connected between the second node D2 and the ground voltage Vss to operate in response to the half input signal / INP. The resistor R2 connects between the second node D2 and the NMOS transistor NT2 to generate a delayed signal L2. The first and second capacitors C1 and C2 delay the signals L1 and L2. The reference circuit 230 includes NMOS transistors NT3 and NT4 and resistors R3 to R5. The resistor R3 is connected between the power supply voltage Vdd and the node D6. The resistor R4 is connected between the node D6 and the node D5. The variable resistor R5 is connected between the node D5 and the ground voltage Vss. The NMOS transistor NT3 of the diode connection structure is connected between the power supply voltage Vdd and the node D4. The NMOS transistor NT3 transfers the power supply voltage Vdd through the node D4 in response to the power supply voltage Vdd. The NMOS transistor NT4 of the diode connection structure transfers the potential of the node D4 through the node D5 in response to the potential of the node D4. When the signal L1 having a level higher than the reference voltage Vref is applied, the first comparator CM1 inverts the applied signal L1 and outputs the inverted signal. When the signal L2 having a level higher than the reference voltage Vref is applied, the second comparator CM2 inverts the applied signal L2 and outputs the inverted signal. PMOS transistor PT3 and NMOS transistor NT5 are enable switches. The PMOS transistor PT3 is connected between the power supply voltage and the node D7 and operates in response to the enable signal EN. The NMOS transistor NT5 is connected between the ground voltage Vss and the node D8 to operate in response to the enable bar signal ENb. PMOS and NMOS transistors PT3 and NT5 are turned on when the latch is initialized. The inverters IV1 and IV2 invert and output the output signals BL1 and BL2 of the first and second comparators CM1 and CM2. The SR latch 240 is composed of NAND gates NG1 and NG2. The SR latch 240 outputs a clock signal clk in response to the output signals of the inverters IV1 and IV2.

The oscillator 200 operates as follows. The first and second interlocks 210 and 220 generate the first and second signals L1 and L2 in response to the input signals INP and / INP. The first and second capacitors C1 and C2 delay the first and second signals L1 and L2. When the power supply voltage Vdd is increased, the reference voltage Vref is applied with a voltage equal to the power supply voltage Vdd minus the voltage of the resistor R5. Therefore, since the increase width of the power supply voltage Vdd is greater than the increase width of the current flowing through the resistor R5, the reference voltage Vref increases. In addition, the reference voltage Vref increases as the temperature increases. This is because the threshold voltages of the NMOS transistors NT3 and NT4 decrease as the temperature increases, so that the potential of the node D5 becomes high and the current flowing between the resistors R3 and R4 decreases. Therefore, the current flowing through the resistor R5 decreases and the reference voltage Vref increases. As the reference voltage Vref increases, the clock period decreases accordingly, so that the clock signal of the entire circuit is uniformly compensated. The inverters IV1 and IV2 invert the output signals BL1 and BL2 of the first and second comparators CM1 and CM2. The SR latch unit 240 outputs a clock signal clk in response to the output signals of the inverters IV1 and IV2.

3 (a) and 3 (b) are graphs showing cycle changes of the oscillator 200 according to the related art and the present invention. 3 (a) is a graph showing a cycle change according to the power supply voltage, Figure 3 (b) is a graph showing a cycle change with the temperature. 1 and 2 are graphs comparing periodic changes according to changes in the power supply voltage Vdd of the oscillator circuit of FIGS. 1 and 2. As illustrated in FIG. 2, it can be seen from the graph that the period variation of the clock signal is not large even when the power supply voltage and temperature increase.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the oscillator circuit having the SR latch according to the present invention can be stably operated by a reference circuit which outputs a constant period by changing the period change in a direction that can compensate for each other by an external environment. can do.

Claims (7)

A first inverter for inverting the first input signal; A second inverter for inverting the second input signal; A reference circuit for generating a reference voltage that varies with power supply voltage and temperature change; A first comparator for comparing an output of the first inverter and an output of the reference circuit; A second comparator for comparing the output of the second inverter with the output of the reference circuit; And And an SR latch for generating a clock signal in response to the outputs of the first and second comparators. The method of claim 1, wherein the first inverter, A PMOS transistor connected between a power supply voltage and a first node to operate in response to the first input signal; An NMOS transistor connected between the first node and a ground voltage to operate in response to the first input signal; And And a first resistor connected between the first node and the NMOS transistor to delay an output signal. The method of claim 1, wherein the second inverter, A PMOS transistor connected between a power supply voltage and a second node to operate in response to the second input signal; An NMOS transistor connected between the second node and a ground voltage to operate in response to the second input signal; And And a second resistor connected between the second node and an NMOS transistor to delay an output signal. The method of claim 1, wherein the reference circuit, First and second resistors connected in series between the power supply voltage and the first node through an output node and outputting a reference voltage at the output node; First and second transistors connected in series between the power supply voltage and the first node and having a diode connection structure; And An oscillator comprising a variable resistor coupled between the first node and the ground. The method of claim 1, wherein the first comparator, And outputting the inverted output of the first inverter when the first inverter output having a level higher than the reference voltage is applied. The method of claim 1, wherein the second comparator, And outputting the inverted output of the second inverter when the second interlock output having a level higher than the reference voltage is applied. The method of claim 1, wherein the SR latch, And the level of the clock signal changes at the instant the output of the first and second comparators changes from a low state to a high state.

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