KR100266658B1 - Self calibrating circuit for semiconductor device - Google Patents

Abstract

PURPOSE: A self compensation circuit of a semiconductor device is provided to adapt positively to the variation of a manufacturing process, an operation voltage and an operation temperature to stabilize the operation characteristics. CONSTITUTION: The self compensation circuit of the semiconductor device includes an oscillator(201), a counter(202,204) and a decoder(206) and a controller(207). The oscillator generates frequency pulses(FREQ1-FREQ13) with response to a characteristic variation. The counter is initialized by a reset signal(CRCS) of predetermined period and counts the output pulses from the output frequencies. The decoder latches each counted result of a latch signal(DLT) to generate a signal(COUT/PN,COUT/N,COUT/P) for compensating the characteristic variation of each device of the semiconductor memory. The controller is controlled by a signal(CAL) of constant period and outputs the control signal(OSS,CRST) at the start position of oscillation and the latch signal(DLT) to the decoder at the end position of the oscillator.

Description

Self-calibration circuit of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a self-correction circuit.

1 is a block diagram of a prior art, as shown therein, when the power supply voltage Vcc is connected to the external pad 106, the external resistor R flowing a constant current to the ground side in response to a change in ambient temperature. A current source 101 for amplifying the current of the external resistor R to supply a current to the common node, a reference voltage generator 103 for generating a reference voltage Bref, a voltage CNV of the common node, A comparator 104 for comparing whether the reference voltage CNV coincides, a counter / decoder section 105 for outputting correction signals C0 to C4 according to the comparison result of the comparator 104, and this counter / decoder The voltage correction unit 102 corrects the voltage CNV of the common node in accordance with the output signals C0 to C4 of the unit 105.

The current source 101 is configured by connecting a gate and a drain of the PMOS transistors P1 and P2 to which a source is supplied with a power supply voltage Vcc, to an external pad 106, and to a common node. .

The voltage corrector 102 applies a power supply voltage Vcc to the gate of the NMOS transistor N1 by grounding a source of the NMOS transistors N1 to N6 having a common drain connected to a common node, and applying the NMOS to the gate of the NMOS transistor N1. The correction signals C0 to C4 from the counter / decoder section 105 are connected to the gates of the transistors N2 to N6, respectively.

Referring to the operation of the prior art as follows.

In general, the change of semiconductor manufacturing process, the change of device characteristics in the semiconductor device, the change of operating voltage at which the semiconductor device operates, or the change of the ambient temperature of the semiconductor device due to the operation of the semiconductor device are determined by the operation of the semiconductor device. This is the main reason for the difference by condition.

Therefore, there is a need for a means of eliminating these differences to ensure stable operation. Conventionally, an accurate resistor connected from the outside is used.

In FIG. 1, it is assumed that the resistor R connected to the external pad 106 has a constant value regardless of operating conditions or characteristics of the semiconductor device, unlike the semiconductor device.

First, when a power supply voltage Vcc is applied and a certain amount of current flows through the resistor R connected to the external pad 106, the current source 101 amplifies the current in the PMOS transistors P1 and P2 so as to provide a voltage compensation. The drains of the NMOS transistors N1 to N6 of the step 102 are supplied to a common node commonly connected.

In the NMOS transistors N1 to N6, only the NMOS transistor N1 is initially turned on by the power supply voltage Vcc and the level of the voltage CNV of the common node is turned on by the NMOS transistor N1. This is determined.

At this time, the reference voltage generator 103 generates a predetermined constant voltage Bref and supplies it to one input terminal of the comparator 104.

Accordingly, the comparator 104 compares the voltage CNV of the common node with the reference voltage Bref.

At this time, if the voltage CNV of the common node is higher than the reference voltage Bref, this means that the current driving capability of one NMOS transistor N1 is insufficient, so that the voltage CNV of the common terminal is not sufficiently discharged. The decoder section 105 turns on one of the correction signals C0 to C4.

In this case, it is assumed that the current driving capability is inadequately turned on in order of C0, C1, C2, C3, and C4.

Therefore, when the counter / decoder section 105 turns on the correction signal C0, the voltage correction section 102 causes the NMOS transistor N2 to turn on to flow a current flowing to the common node to the ground side.

The above process is repeatedly performed until the reference voltage Bref is equal to the voltage CNV of the common node.

If the reference voltage Bref and the common node voltage CNV are the same through the above process, the gate input signals C0 to C4 of each of the NMOS transistors N2 to N6 set by the counter / decoder section 105 are the same. ) Is a value that is corrected to ensure that the operation is matched to the designed value for a given process condition, operating voltage, and operating temperature of the semiconductor device.

Taking the application circuit as shown in Fig. 2 as an example, the driving capability of the NMOS transistors of the output buffers 111 to 117 is determined by using the comparator 104 and the counter / decoder section 105 to output buffer enable signals Vcc, C0 to C. It can be controlled by applying C4).

However, the related art requires an external resistor as a necessary material for correcting the operation of the semiconductor device, which requires an extra package for connecting the resistor, resulting in an increase in the number of parts and an increase in area during mounting.

In addition, the conventional technology requires a precise reference voltage generator in a semiconductor device, and generally has a problem that cannot be easily implemented in a MOS process by using the characteristics of a bipolar device.

Accordingly, an object of the present invention is to provide a self-correction circuit of a semiconductor device invented to have a constant operating characteristic despite these changes by actively reacting to changes in manufacturing processes, operating voltages and operating temperatures, etc., in order to improve the conventional problems. There is this.

In particular, the present invention utilizes the output frequency of an oscillator having characteristics that depend on the manufacturing process, operating voltage, and operating temperature. The purpose of the present invention is to ensure stable operation even when the operating conditions are changed by changing the size).

1 is a conventional self-correction circuit diagram.

2 is a block diagram showing the application of FIG.

Figure 3 is a block diagram showing an embodiment of the present invention.

4 is a circuit diagram of an inverter type oscillator in FIG.

FIG. 5 is a circuit diagram of a NAND gate type oscillator in FIG. 3. FIG.

FIG. 6 is a circuit diagram of a noah gate type oscillator in FIG. 3. FIG.

7 is an operation timing diagram in FIG. 3;

Explanation of symbols on the main parts of the drawings

201,203,205: Oscillator 202,204,206: Counter / Decoder

207: controller

The present invention provides an oscillation block for generating an output pulse of a frequency that depends on the manufacturing process, operating voltage, and operating temperature, a counter block for counting the output pulse of the oscillating block, and the coefficient of the counter block. A decoder block for outputting a correction signal for correcting a characteristic change of each MOS transistor by latching a value, and operating the oscillation block at regular intervals, resetting the counter block at the start of operation of the oscillation block, and oscillating the oscillation block And a controller for latching the decoder block at the end of the operation of the block.

The oscillation block includes an inverter type ring oscillator for generating pulses reflecting both the characteristics change of the PMOS transistor and the NMOS transistor, a NOR gate type ring oscillator for generating the pulse mainly reflecting the characteristic change of the PMOS transistor, It is characterized by including a NAND gate type ring oscillator mainly reflecting the change in the characteristics of the MOS transistor.

The oscillation block and the counter block are characterized by operating as a frequency counter.

Hereinafter, the present invention will be described in detail with reference to the drawings.

Figure 3 is a block diagram showing an embodiment of the present invention, as shown therein, the frequency depending on the manufacturing process (P), operating voltage (V), operating temperature (T) in accordance with the oscillation start / end signal (OSS) Oscillators 201, 203 and 205 for generating the output pulses FREQ1 to FREQ3 respectively, and initialized to preset values by the reset signal CRST to count and latch the respective output pulses FREQ1 to FREQ3 of the oscillators 201, 203 and 205. Counter / decoder sections 202, 204, 206 for outputting correction signals COUT / PN, COUT / N, COUT / P, respectively, by latching the count value by the signal DLT, and a pulse signal CAL of a predetermined period. The oscillator 201, 203, 205 controls the start / end operation of the oscillator 201, 203, 205, and outputs a reset signal CRST to the counter / decoder 202, 204, 206 at the start point of operation of the oscillator 201, 203, 205 and the oscillator 201, 203, 205. To the counter / decoder section 202, 204, 206 at the end of The controller 207 outputs the latch signal DLT.

The oscillator 201 is an inverter-type ring oscillator for reflecting changes in characteristics of both PMOS and NMOS transistors, as shown in the circuit diagram of FIG. 4, when the oscillation start / end signal OSS is active. A delay of sequentially outputting the NAND gate 211 for inverting (PREQ) and the output signals of the NAND gate 211 in a plurality of even-numbered inverters to output the oscillation pulse FREQ1 to the counter / decoder section 202. It consists of a circuit 212.

The oscillator 203 is a NAND gate type ring oscillator for reflecting changes in the characteristics of the NMOS transistor. As shown in the circuit diagram of FIG. 5, the oscillation pulse PREQ is generated when the oscillation start / end signal OSS is active. A delay circuit 222 which sequentially inverts the NAND gate 221 to be inverted and the output signal of the NAND gate 221 at a plurality of even NAND gates, and outputs the oscillation pulse FREQ2 to the counter / decoder section 204. ).

The oscillator 205 is a NOR gate type ring oscillator for reflecting changes in characteristics of a PMOS transistor. As shown in the circuit diagram of FIG. 6, the oscillator pulse PREQ is generated when the oscillation start / end signal OSS is active. A delay circuit 232 that sequentially inverts the NAND gate 231 to invert and the output signals of the NAND gate 231 at a plurality of even-numbered NOR gates, and outputs the oscillation pulse FREQ3 to the counter / decoder section 206. ).

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

The operation of the semiconductor device is performed according to the characteristics (P) of the semiconductor device under the given process conditions, that is, the performance of the NMOS transistor and the PMOS transistor, the operating voltage (V) of the semiconductor device, and the operating temperature (T) of the semiconductor device. (Operation speed, etc.) is determined.

For example, in the case of output circuits, if they are fabricated / operated at specified voltages and temperatures, and intermediate process conditions, the power supply noise of the output signal may be limited below the specification, but the transistors perform better and the operating voltage is higher than specified. At higher and very low operating temperatures, even the output circuit of the same semiconductor device can cause a lot of power supply noise.

Accordingly, it is required to ensure proper operation in various ranges by appropriately adjusting the performance of the semiconductor device expressed as a function of these various conditions, namely, process conditions, operating voltages, and operating temperatures.

The basic idea of the invention is that for a simple semiconductor circuit, for example a ring oscillator, the period of the output signal is a function of the above-mentioned process conditions (P), operating voltage (V) and operating temperature (T). By utilizing the oscillator embedded in a given semiconductor device, the operation of the semiconductor device is controlled within an appropriate range.

On the other hand, in the design of a semiconductor device, it may be influenced by the performance of the NMOS transistor or the performance of the PMOS transistor, or by both the NMOS transistor and the PMOS transistor.

That is, when the output circuit has a characteristic of transitioning from low to high, for example, the influence of the PMOS transistor is dominant. On the contrary, when the output circuit has a characteristic of transitioning from high to low, the characteristics of the NMOS transistor dominate. It's crazy.

In general logic, the delay time and the like are influenced by the NMOS transistor and the PMOS transistor alternately, so that both the NMOS transistor and the PMOS transistor change appear.

In the case of an output circuit in a semiconductor device, the characteristics of the PMOS transistor are excessively bad due to process changes, while the NMOS transistor has only one correction circuit if the characteristics of the NMOS transistor are too good. .

For example, in an inverter type ring oscillator, the characteristics of the NMOS transistors are interlocked with the characteristics change of the PMOS transistors, so that it is impossible to detect each characteristic change only by the output frequency thereof.

Therefore, a circuit for correcting such a characteristic change is required. To this end, in the present invention, the characteristic change of the NAND gate type ring oscillator 203 and the PMOS transistor mainly reflects the characteristic change of the NMOS transistor. An NOR gate type ring oscillator 205 that can reflect, and an inverter type ring oscillator 201 that can reflect all the characteristic changes of the NMOS and PMOS transistors are provided to cope actively with each change.

An embodiment of the present invention having the above characteristics will be described with reference to the block diagram of FIG. 3, the circuit diagram of FIGS. 4 to 6, and the timing diagram of FIG.

First, the controller 207 controlled to the periodic signal as shown in FIG. 7 (a) is embedded in the semiconductor device by the periodic oscillation start / end signal (OSS) as shown in FIG. 7 (b) generated at regular time intervals. Oscillators 201, 203, and 205 start operation, and at the same time as operation of the oscillators 201, 203, and 205, counter / decoder sections 202, 204, and 206 are reset to a predetermined state by a reset signal CRST as shown in FIG.

The periodic oscillation start / end signal OSS is determined according to the operating state of the semiconductor device, and the period is several tens of ms.

At this time, the oscillator 201 performs ring oscillation through the delay circuit 212 composed of the NAND gate 211 and an even number of inverters, and the oscillator 203 is an NAND gate 221 and an even number of NAND gates. Ring oscillation is performed through the delay circuit 222, and the oscillator 205 performs ring oscillation through the delay circuit 232 including the NAND gate 231 and an even number of NOR gates.

As a result, the ring oscillators 201, 203, and 205 convert the output pulses FREQ1, FREQ2, and FREQ3 of the frequency determined by the process condition P, the operating voltage V, and the operating temperature T in which the semiconductor device is manufactured. It is generated in response to the characteristic change of each MOS transistor in the device.

The output pulses FREQ1 to FREQ3 are as shown in Figs. 7 (e) (g) (i), respectively.

At this time, the counter / decoder section 202, 204, 206 increases or decreases the preset value by one bit each time the output pulses FREQ1, FREQ2, FREQ3 of the oscillators 201, 203, 205 toggle.

Here, the increase / decrease of the count value is set according to the characteristics of the counter.

Thereafter, when a predetermined time elapses, the controller 207 inactivates the oscillation start / stop signal OSS as shown in FIG. 7B and generates the latch signal DLT as shown in FIG. 7D. The operations of 201 to 203 are stopped, and at the same time, the counter / decoder sections 202, 204, and 206 latch and store the values in which the decoder counts pulse signals generated between the start and stop of the oscillators 201, 203, and 205, respectively.

The output values COUT / PN, COUT / N, and COUT / P shown in FIG. 7 (f) (h) (j) latched in the counter / decoder sections 202, 204, and 206, respectively, are the process information P of the semiconductor device. The value is determined according to the operating voltage V and the operating temperature T.

Therefore, the values COUT / PN, COUT / N, and COUT / P latched on the counter / decoder sections 202, 204 and 206 are held until the next corrective operation and used for the function of adjusting the operation of various elements in the semiconductor device.

In other words, each of the correction signals COUT / PN, COUY / N / COUT / P using the oscillators 201, 203, and 205 is connected to each circuit in the semiconductor device to be corrected, and thus the characteristics of each circuit are adjusted. Ensure correct calibration is made.

The oscillators 201, 203 and 205 can be operated by the self-correction operation when the operating voltage V of the semiconductor device exceeds the consideration range at the time of design under the process conditions given above.

If the operating voltage V is high, the frequencies of the output signals FREQ1 to FREQ3 of the oscillators 201, 203 and 205 will show higher values than when the operating voltage is low.

In addition, the controller 207 for controlling the start and stop of the self-correction operation is controlled by a signal CAL of a predetermined period as shown in FIG. 7 (a) input from the outside so that the oscillator 201, 203, 205 and the counter / decoder section The counters of 202, 204, and 206 act as a kind of frequency counter.

The constant period signal CAL is a stable clock signal mainly controlled by a crystal oscillator and a PLL circuit.

Accordingly, the output of the counter can distinguish between when the operating voltage V is high and low, and the count value at this time is converted by the decoder to fit the corresponding correction element and used to control the corresponding element.

For example, if the operating voltage of the output circuit is increased, even if the same output circuit is used, the power supply noise will increase at the output, thereby appropriately reducing the driving capability of the output circuit.

That is, the degree of reduction / expansion of the driving capability of the output circuit can be set by designing the voltage (V) / temperature (T) / process (P) conditions of the operating range at design time as boundary conditions.

As described in detail above, the present invention performs an operation of correcting an appropriate operation of a semiconductor device according to a change in process conditions P such as voltage V and temperature T, which are operating conditions, and characteristics of a transistor. Using a ring oscillator, a counter, a decoder, etc., there is an effect of stably maintaining the operation of the semiconductor device in a wide range.

In addition, the present invention can reflect the change in the characteristics of each element in the semiconductor device independently in the correction operation, thereby enabling effective correction.

Claims (5)

Oscillation means which is controlled by the oscillation start / end signal OSS at a constant period to generate output pulses FREQ1 to FRE13 corresponding to the characteristic change of each element in the semiconductor device, and by a predetermined period of the reset signal CRST in advance A counter means for counting the output pulses FREQ1 to FREQ3 of the oscillation means, respectively, and latching each count value of the counter means by a latch signal DLT at a predetermined period, thereby allowing each element in the semiconductor device to be latched. Decoder means for outputting signals (COUT / PN, COUT / N, COUT / P) for correcting a characteristic change of the control signal, and controlled by a signal CAL of a predetermined period, so that the control signal (OSS) at the start of the oscillation means starts. And a controller for outputting the CRST to the oscillation means and the counter means, respectively, and outputting a latch signal DLT to the decoder means at the end of oscillation of the oscillation means. The magnetic compensation circuit. The oscillating means of claim 1, wherein the oscillating means comprises an inverter-type ring oscillator for generating a pulse FREQ1 reflecting both the characteristic change of the PMOS transistor and the NMOS transistor in the semiconductor device, and the pulse reflecting the characteristic change of the NMOS transistor ( A NAND gate type ring oscillator for generating FREQ2) and a NOR gate type ring oscillator for generating a pulse FREQ3 reflecting a characteristic change of a PMOS transistor. 2. The self-correction circuit of a semiconductor device according to claim 1, wherein the oscillation means and the counter means operate as frequency counters. 2. The self-correction circuit of a semiconductor device according to claim 1, wherein the counter means comprises three counters which respectively count oscillation pulses FREQ1 to FREQ3. The semiconductor device according to claim 1, wherein the decoder means comprises three decoders for respectively latching three output signals of the counter means and outputting correction signals COUT / PN, COUT / N, and COUT / P, respectively. Self-correction circuit.