KR920001920B1 - Ring oscillator for temperature compensation - Google Patents

Abstract

The ring oscillator used in a logic circuit generates frequency insensitive to temperature variation. The oscillator comprises an oscillation circuit (1) composed of an odd number of logic gates connected in series and feedback loop to feed the output signal to an input terminal, a power supplying unit (2) comprising first type transistor tosupply Vcc voltage to the oscillation circuit (1), a ground path unit (3) to connect the oscillation circuit to Vss and a bias unit (4) comprising a resister (R) and two MOS transistor (D,S) whose gates are connected to the gates of the power supplying unit (2) and a ground path unit (3).

Description

Temperature Compensation Ring Oscillator

1 is a conventional ring oscillator circuit diagram.

2 is a ring oscillator circuit diagram of the present invention.

3 is a characteristic diagram comparing the cycle time of the ring oscillator with temperature changes.

4 is a characteristic diagram comparing the power consumption of the ring power supply of the ring oscillator according to the temperature change.

* Explanation of symbols for main parts of the drawings

1: oscillation circuit 2: power supply passage

3: Power path passage 4: Bias part

I1 ~ I5: Inverter

MP1, MP2,... , MN1, MN2,... , MD1, MD2,... MOS transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ring oscillator having a logic delay in a logic circuit, and more particularly, to a temperature compensating ring oscillator capable of preventing the propagation time from changing with temperature by using a MOS transistor. A circuit having a delay of the logic signal (propagation time) is usually formed in a closed circuit with an odd number of logic gates, a representative circuit of which is shown in FIG.

Conventional ring oscillators use an odd number of inverters by oscillating signals applied by forming a closed circuit connected in series using a plurality of inverters I1-I5 as logic gates. Here, the oscillation frequency is obtained by adjusting the delay time as the time constant of each inverter, but when the temperature changes, the electron movement is reduced, so the conductance of the P.NMOS transistor constituting the inverter circuit is reduced. This caused the oscillator's oscillation frequency to decrease. Therefore, the system is to cause a malfunction in a system that drives other circuits based on the oscillation frequency of the ring oscillator affected by the above temperature.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a temperature compensation ring oscillator that can greatly reduce the fluctuation of the frequency according to the temperature change. Another object is to provide a temperature compensating ring oscillator which can reduce power consumption according to temperature change.

Features of the present invention include an oscillation circuit sequentially connected to an odd number of logic gates; A power supply passage consisting of MOS transistors of a first type to supply power to the oscillation circuit; A power path passage consisting of MOS transistors of a second type to allow power applied to the oscillation circuit to flow; A bias unit for supplying a constant bias power to the power passage and the power passage; It is to provide a ring oscillator consisting of.

This feature can be achieved by maintaining a constant bias regardless of the temperature change in which the current-mirror constitutes the current supplied to the power supply passage and the power path passage in the bias portion that supplies a constant electrostatic source.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 shows a ring oscillator circuit diagram of the present invention. An oscillation circuit 1 is formed by connecting a plurality of inverters I1 to I5 in series to use an odd number of inverters. Here, other logic gates may be used instead of the inverter device. The inverters I1 to I5 are sequentially connected, and the output of the last stage inverter I5 is configured to output an oscillation signal to the output terminal out and to be fed back to the input of the first stage inverter I1. The power supply passage 2 for supplying the power supply VCC to the oscillation circuit 1 composed of the inverters I1 to I5 is connected to the power supply VCC by configuring the MOS transistors MP1 to MP5 of the first type. The nord side is connected to the source side of the MOS transistors MP1 to MP5 and each drain side is connected to each of the inverters I1 to I5 to supply power. The first type of MOS transistors MP1 to MP5 are composed of PMOS transistors.

The power path passage 3 connected to the oscillation circuit 1 to create a passage through which the power supply VCC flows is composed of MOS transistors MH1 to MH5 of the second type, and each drain side of the inverter I1 to I5. Each source side is connected to the ground (VCC) so that power can flow.

Here, the second type of MOS transistors MN to MN5 are composed of NMOS transistors. The bias unit 4 configured between the power supply VCC side and the ground side VSS side is configured such that the PMOS transistor MD1 and the NMOS transistor MD2 are connected through a resistor R, and each P.NMOS The gate side of the transistors MD1 and MD2 is connected to the source or drain side to operate as a diode.

The gate side of the first type MOS transistors MP1 to MP5 of the power supply passage 2 is configured to be connected to the drain side of the same type of MOS transistor MD1 of the bias unit 4, and the power path passage 3. The gate side of the second type MOS transistors MN to MN5 is configured to be connected to the drain side of the same type MOS transistor MD2 of the bias unit 4.

Here, the voltage applied to the gate side of the MOS transistor of the first type configured between the logic gates constituted by the inverter and the power supply VCC side is a threshold voltage VT1 of the MOS transistor MD1 of the bias portion and the empty time. The gate voltage of the MOS transistor of the second type connected between the logic gates composed of the inverter and the ground voltage VSS, which is maintained as VCC-VT1 by subtracting the value, is the same as that of the bias part of the MOS transistor MD2 of the same type. The gate voltage VT2 is maintained at VSS + VT2, which is the sum of the ground voltage VSS.

In the present invention configured as described above, when the power supply VCC is supplied, a bias voltage through the bias unit 4 is applied to the power supply passage 2 and the gates 3 of the transistors of the power path passage to oscillate the power supply VCC voltage. It is supplied to the circuit 1.

The power supply VCC applied to the bias unit 4 is applied to the gate side of the first type transistors MP1 to MP5 of the power supply passage 2 through the MOS transistor MD1 of the first type serving as a diode. The power dropped by the resistor R is applied to the gate side of the second type transistors MP1 to MP5 of the power supply passage 2.

Therefore, when the current supplied to each of the inverters I1 to I5 through the MOS transistors of the power supply passage 2 is formed by the same process as the MOS transistors MD1 of the first type of the MOS transistors of the bias portion, Each of the inverters I1 to I5 has the same characteristic, and the bias portion is supplied with the same amount of current as the current flowing in the first type MOS transistor MD1.

Here, the PMOS transistors MP1 to MP5 are pull-up transistors. In addition, a voltage dropped from the resistor R of the bias unit 4 is supplied to the gates of the NMOS transistors MN to MN5 connected to the respective inverters I1 to I5 to form the power passage 3. When the transistors MN to MN5 have the same characteristics through the same process as the second type MOS transistor MD2 of the bias part, the current flowing through the NMOS transistors MN to MN5 flows to the second type MOS transistor MD2 of the bias part. It is equal to the current.

Here, the NMOS transistors MN to MN5 are for pulldown. Accordingly, current flows through each of the inverters I1 to I5 through the MOS transistors of the first type and the second type of MOS transistors connected to each other. Will flow.

In particular, the bias unit 5 that controls the current flowing through each of the inverters I1 to I5 supplies current in a current mirror type to the MOS transistors of the first and second types, thereby greatly changing the frequency variation due to temperature change. Can be reduced.

In this case, the current change of the inverter stage due to the temperature change is not determined by the inverters I1 to I5 itself, but is limited by the current source of the bias unit 4 of the ring oscillator. Become insensitive. In addition, the bias unit 4 connects a resistor (R) element having a large resistance value between the P.NMOS transistors to supply power and form a direct current path, thereby greatly reducing power consumption.

FIG. 3 is a characteristic diagram comparing the cycle time of the ring oscillator according to the temperature change, comparing the conventional ring oscillator of FIG. 1 with the ring oscillator of FIG.

As can be seen from this characteristic diagram, it can be seen that the ring oscillator of the present invention has characteristics similar to a dotted line, and thus has a more stable characteristic with respect to temperature than a reference ring oscillator.

4 is a characteristic diagram showing the power consumption according to the temperature change, comparing the conventional ring oscillator and the ring oscillator of the present invention. In the present invention, the power consumption according to the temperature change is also conventional. It can be seen that it is improved over ring oscillator.

As described above, according to the present invention, the current consumption of each inverter constituting the ring oscillator circuit is driven by a constant power supplied from the bias unit using the current mirror characteristic, thereby greatly changing the frequency caused by the temperature change. In this case, when the ring oscillator is used in a semiconductor system, a desired frequency signal may not be generated, thereby eliminating the cause of the system malfunction. Therefore, by using the MOS technology, stable operating characteristics against temperature changes can be obtained in semiconductor integrated devices driven by the oscillation frequency of the ring oscillator.

Claims (4)

In a ring oscillator in which odd logic gates are sequentially connected to form a closed circuit in order to generate a constant oscillation frequency pulse, an oscillation circuit (1) in which odd logic gates are sequentially connected and a state signal of an output side is fed back to an input side (1) )Wow; One or more non-axial shafts are connected to the power supply (VCC) side and are connected to a power supply passage (2) composed of MOS transistors of the first type and ground (GND) side to supply power. A power path path 3 composed of MOS transistors of a type; The gate axis of the first type MOS transistors of the power path 2 and the gate side of the second type MOS transistors of the power path path 3 are connected to the gate-drain side axes of the same type of MOS transistors, respectively. A temperature compensating ring oscillator composed of a bias portion (4) so that the oscillation frequency does not change with temperature. 2. The gate voltage applied to the MOS transistors MP1 to MP5 of the first type constituting the power supply circuit 2 is set at the power supply voltage supplied from the power supply VCC side. The value obtained by subtracting the threshold voltage VT1 of the MOS transistor itself is supplied, and the power supply passage is provided with the gate voltage applied to the MOS transistors MN to MN5 of the second type constituting (3). A temperature compensation ring oscillator that supplies the threshold voltage (VT2) and ground voltage (VSS) of the MOS transistor itself. 2. The biasing device (4) according to claim 1, wherein the bias portion (4) is composed of first and second type MOS transistors connected in series with a logic gate and acts as a diode and between the first and second type MOS transistors. Temperature-compensated ring oscillator. The first type MOS transistors MP1 to MP5 constituting the power supply circuit 2 are constituted by P-channel elements having N wells as a substrate, and constitute the power passage circuit 3. Two types of MOS transistors (MN to MN5) are temperature compensation ring oscillators composed of N-channel elements.

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