KR100677842B1 - 반도체 장치 및 그 제조 방법 - Google Patents
반도체 장치 및 그 제조 방법 Download PDFInfo
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- KR100677842B1 KR100677842B1 KR1020050025397A KR20050025397A KR100677842B1 KR 100677842 B1 KR100677842 B1 KR 100677842B1 KR 1020050025397 A KR1020050025397 A KR 1020050025397A KR 20050025397 A KR20050025397 A KR 20050025397A KR 100677842 B1 KR100677842 B1 KR 100677842B1
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- insulating film
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- interlayer insulating
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- density plasma
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- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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Abstract
Description
Claims (10)
- 반도체 기판;상기 반도체 기판의 위쪽에 형성되어 있고, 하부(下部) 전극과 상부(上部) 전극의 사이에 강유전체를 재료로 하는 유전체막을 삽입하여 이루어지는 커패시터 구조;상기 커패시터 구조의 위쪽에 형성되어, 적어도 일부가 상기 커패시터 구조와 접속되어 이루어지는 복수의 배선을 갖는 배선층; 및상기 배선층을 덮는 고밀도 플라즈마 절연 재료로 이루어지는 상부 층간절연막을 포함하며,상기 상부 층간절연막은 인접하는 상기 배선 사이에서 상기 배선보다도 낮은 개소에 보이드(void)가 형성되어 이루어지며,상기 상부 층간절연막은 저(低)바이어스 또는 무(無)바이어스의 제 1 고밀도 플라즈마 절연막과, 상기 저바이어스보다도 높은 바이어스의 제 2 고밀도 플라즈마 절연막이 차례로 적층되어 이루어지는 것을 특징으로 하는 반도체 장치.
- 삭제
- 제 1 항에 있어서,상기 배선층과 상기 상부 층간절연막 사이에 형성되어 이루어지는 수소 확산 방지막을 더 포함하는 것을 특징으로 하는 반도체 장치.
- 제 1 항 또는 제 3 항에 있어서,상기 커패시터 구조를 덮는 고밀도 플라즈마 절연 재료로 이루어지는 하부 층간절연막을 더 포함하는 것을 특징으로 하는 반도체 장치.
- 반도체 기판의 위쪽에, 하부 전극과 상부 전극의 사이에 강유전체를 재료로 하는 유전체막을 삽입하여 이루어지는 커패시터 구조를 형성하는 공정과,상기 커패시터 구조의 위쪽에, 적어도 일부가 상기 커패시터 구조와 접속되도록 복수의 배선을 갖는 배선층을 형성하는 공정과,상기 배선층을 덮도록, 고밀도 플라즈마 절연 재료로 이루어지는 상부 층간절연막을 형성하는 공정을 포함하며,인접하는 상기 배선 사이에서, 상기 상부 층간절연막의 상기 배선보다도 낮은 개소에 보이드가 형성되도록 제어하여 상기 상부 층간절연막을 형성하며,상기 상부 층간절연막을 형성할 때에, 상기 반도체 기판을 탑재 고정시키는 기판 지지대를 챔버 내에서 상하 방향으로 움직일 수 있게 한 고밀도 플라즈마 CVD 장치를 사용하고,상기 반도체 기판이 상기 챔버 내에서 위쪽에 위치할수록 퇴적되는 고밀도 플라즈마 절연 재료의 밀도가 높아지는 것을 이용하여,상기 기판 지지대에 탑재 고정된 상기 반도체 기판의 상기 챔버 내에서의 위치를 상하 방향으로 조절하여, 상기 보이드의 형성을 제어하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 삭제
- 반도체 기판의 위쪽에, 하부 전극과 상부 전극의 사이에 강유전체를 재료로 하는 유전체막을 삽입하여 이루어지는 커패시터 구조를 형성하는 공정과,상기 커패시터 구조의 위쪽에, 적어도 일부가 상기 커패시터 구조와 접속되도록 복수의 배선을 갖는 배선층을 형성하는 공정과,상기 배선층을 덮도록, 고밀도 플라즈마 절연 재료로 이루어지는 상부 층간절연막을 형성하는 공정을 포함하며,인접하는 상기 배선 사이에서, 상기 상부 층간절연막의 상기 배선보다도 낮은 개소에 보이드가 형성되도록 제어하여 상기 상부 층간절연막을 형성하며,상기 상부 층간절연막을 저바이어스 또는 무바이어스에 의한 고밀도 플라즈마 CVD법을 이용한 제 1 고밀도 플라즈마 절연막과, 상기 저바이어스보다도 높은 바이어스에 의한 고밀도 플라즈마 CVD법을 이용한 제 2 고밀도 플라즈마 절연막을 차례로 적층하여 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제 5 항 또는 제 7 항에 있어서,상기 커패시터 구조를 덮도록 고밀도 플라즈마 절연 재료로 이루어지는 하부 층간절연막을 형성하는 공정을 더 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제 5 항 또는 제 7 항에 있어서,상기 유전체막을 PZT 또는 SBT를 재료로 하여 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제 5 항 또는 제 7 항에 있어서,상기 상부 층간절연막의 성막(成膜) 온도를 175℃∼400℃ 범위 내의 값으로 조절하는 것을 특징으로 하는 반도체 장치의 제조 방법.
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US7687394B2 (en) * | 2005-12-05 | 2010-03-30 | Dongbu Electronics Co., Ltd. | Method for forming inter-layer dielectric of low dielectric constant and method for forming copper wiring using the same |
US7485528B2 (en) | 2006-07-14 | 2009-02-03 | Micron Technology, Inc. | Method of forming memory devices by performing halogen ion implantation and diffusion processes |
JP5423056B2 (ja) * | 2009-03-02 | 2014-02-19 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
JP2011061085A (ja) * | 2009-09-11 | 2011-03-24 | Toshiba Corp | 強誘電体記憶装置 |
JP5635301B2 (ja) | 2010-05-12 | 2014-12-03 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置及びその製造方法 |
KR102345675B1 (ko) * | 2015-07-13 | 2021-12-31 | 에스케이하이닉스 주식회사 | 스위치드-커패시터 디시-디시 컨버터 및 그 제조방법 |
JP2017228599A (ja) * | 2016-06-21 | 2017-12-28 | ソニー株式会社 | 半導体装置、及び半導体装置の製造方法 |
US11133248B2 (en) * | 2019-11-11 | 2021-09-28 | Xia Tai Xin Semiconductor (Qing Dao) Ltd. | Semiconductor structure and method for fabricating the same |
WO2022019155A1 (ja) * | 2020-07-20 | 2022-01-27 | ソニーセミコンダクタソリューションズ株式会社 | 配線構造およびその製造方法、ならびに撮像装置 |
US20220406782A1 (en) * | 2021-06-18 | 2022-12-22 | Abhishek A. Sharma | Backend memory with air gaps in upper metal layers |
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JPH01108382A (ja) * | 1987-10-21 | 1989-04-25 | Nec Corp | プラズマ気相成長装置 |
JPH0897379A (ja) * | 1994-09-27 | 1996-04-12 | Sony Corp | 半導体集積回路とその製法 |
JP2853661B2 (ja) * | 1996-06-27 | 1999-02-03 | 日本電気株式会社 | 半導体集積回路装置の製造方法 |
JP2000022981A (ja) | 1998-07-03 | 2000-01-21 | Hitachi Ltd | ディスプレイ装置 |
JP2000100976A (ja) * | 1998-09-21 | 2000-04-07 | Matsushita Electronics Industry Corp | 半導体メモリアレイ装置およびその製造方法 |
JP2001135631A (ja) * | 1999-11-10 | 2001-05-18 | Matsushita Electronics Industry Corp | 半導体装置及びその製造方法 |
US20020175145A1 (en) * | 2001-05-25 | 2002-11-28 | Shyh-Dar Lee | Method of forming void-free intermetal dielectrics |
JP2003347218A (ja) * | 2002-05-28 | 2003-12-05 | Renesas Technology Corp | ガス処理装置および半導体装置の製造方法 |
JP2004087807A (ja) * | 2002-08-27 | 2004-03-18 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US7456116B2 (en) * | 2002-09-19 | 2008-11-25 | Applied Materials, Inc. | Gap-fill depositions in the formation of silicon containing dielectric materials |
WO2004095578A1 (ja) * | 2003-04-24 | 2004-11-04 | Fujitsu Limited | 半導体装置及びその製造方法 |
US6881668B2 (en) * | 2003-09-05 | 2005-04-19 | Mosel Vitel, Inc. | Control of air gap position in a dielectric layer |
JP2005183842A (ja) * | 2003-12-22 | 2005-07-07 | Fujitsu Ltd | 半導体装置の製造方法 |
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