KR100676788B1 - 메모리 회로 - Google Patents

메모리 회로 Download PDF

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Publication number
KR100676788B1
KR100676788B1 KR1020040030119A KR20040030119A KR100676788B1 KR 100676788 B1 KR100676788 B1 KR 100676788B1 KR 1020040030119 A KR1020040030119 A KR 1020040030119A KR 20040030119 A KR20040030119 A KR 20040030119A KR 100676788 B1 KR100676788 B1 KR 100676788B1
Authority
KR
South Korea
Prior art keywords
circuit
register
data
signal
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020040030119A
Other languages
English (en)
Korean (ko)
Other versions
KR20040094355A (ko
Inventor
나오또시 니시오까
Original Assignee
야마하 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 야마하 가부시키가이샤 filed Critical 야마하 가부시키가이샤
Publication of KR20040094355A publication Critical patent/KR20040094355A/ko
Application granted granted Critical
Publication of KR100676788B1 publication Critical patent/KR100676788B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H23/00—Tumbler or rocker switches, i.e. switches characterised by being operated by rocking an operating member in the form of a rocker button
    • H01H23/02—Details
    • H01H23/12—Movable parts; Contacts mounted thereon
    • H01H23/14—Tumblers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/065—Sense amplifier drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation

Landscapes

  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
KR1020040030119A 2003-04-30 2004-04-29 메모리 회로 Expired - Fee Related KR100676788B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003125362A JP2004334929A (ja) 2003-04-30 2003-04-30 メモリ回路
JPJP-P-2003-00125362 2003-04-30

Publications (2)

Publication Number Publication Date
KR20040094355A KR20040094355A (ko) 2004-11-09
KR100676788B1 true KR100676788B1 (ko) 2007-02-02

Family

ID=33308169

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020040030119A Expired - Fee Related KR100676788B1 (ko) 2003-04-30 2004-04-29 메모리 회로

Country Status (5)

Country Link
US (1) US7031207B2 (enExample)
JP (1) JP2004334929A (enExample)
KR (1) KR100676788B1 (enExample)
CN (1) CN1542841B (enExample)
TW (1) TWI244094B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
KR100655084B1 (ko) * 2006-01-17 2006-12-08 삼성전자주식회사 센스앰프 인에이블 회로 및 이를 갖는 반도체 메모리 장치
US8694812B2 (en) * 2010-03-29 2014-04-08 Dot Hill Systems Corporation Memory calibration method and apparatus for power reduction during flash operation
US8806245B2 (en) * 2010-11-04 2014-08-12 Apple Inc. Memory read timing margin adjustment for a plurality of memory arrays according to predefined delay tables
US9997232B2 (en) * 2016-03-10 2018-06-12 Micron Technology, Inc. Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations
US10475492B1 (en) * 2018-07-27 2019-11-12 Macronix International Co., Ltd. Circuit and method for read latency control

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08123838A (ja) 1994-10-21 1996-05-17 Hitachi Ltd Ａｓｉｃメモリおよびそれを用いたマイクロコンピュータ、ならびにメモリ設計方法
JP4707244B2 (ja) * 2000-03-30 2011-06-22 ルネサスエレクトロニクス株式会社 半導体記憶装置および半導体装置
JP4345204B2 (ja) * 2000-07-04 2009-10-14 エルピーダメモリ株式会社 半導体記憶装置
JP2002216481A (ja) * 2001-01-19 2002-08-02 Hitachi Ltd 半導体集積回路装置

Also Published As

Publication number Publication date
CN1542841B (zh) 2011-03-23
TW200428407A (en) 2004-12-16
CN1542841A (zh) 2004-11-03
KR20040094355A (ko) 2004-11-09
JP2004334929A (ja) 2004-11-25
US7031207B2 (en) 2006-04-18
TWI244094B (en) 2005-11-21
US20040218430A1 (en) 2004-11-04

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