KR100623801B1 - 반도체 메모리 비동기식 파이프라인 - Google Patents

반도체 메모리 비동기식 파이프라인 Download PDF

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KR100623801B1
KR100623801B1 KR1020007010865A KR20007010865A KR100623801B1 KR 100623801 B1 KR100623801 B1 KR 100623801B1 KR 1020007010865 A KR1020007010865 A KR 1020007010865A KR 20007010865 A KR20007010865 A KR 20007010865A KR 100623801 B1 KR100623801 B1 KR 100623801B1
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Prior art keywords
latch
pipeline
data
output
system clock
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Korean (ko)
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KR20010042316A (ko
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이안 메스
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모사이드 테크놀로지스 인코포레이티드
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

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KR1020007010865A 1998-04-01 1999-04-01 반도체 메모리 비동기식 파이프라인 Expired - Lifetime KR100623801B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
CA2,233,789 1998-01-04
CA2233789A CA2233789C (en) 1998-04-01 1998-04-01 Semiconductor memory asynchronous pipeline
US09/129,878 1998-08-06
US09/129,878 US6539454B2 (en) 1998-04-01 1998-08-06 Semiconductor memory asynchronous pipeline
US9/129,878 1998-08-06

Publications (2)

Publication Number Publication Date
KR20010042316A KR20010042316A (ko) 2001-05-25
KR100623801B1 true KR100623801B1 (ko) 2006-09-12

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KR1020007010865A Expired - Lifetime KR100623801B1 (ko) 1998-04-01 1999-04-01 반도체 메모리 비동기식 파이프라인

Country Status (4)

Country Link
US (1) US6539454B2 (https=)
JP (2) JP5266271B2 (https=)
KR (1) KR100623801B1 (https=)
CA (2) CA2233789C (https=)

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US8391039B2 (en) * 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
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US7484079B2 (en) * 2002-10-31 2009-01-27 Hewlett-Packard Development Company, L.P. Pipeline stage initialization via task frame accessed by a memory pointer propagated among the pipeline stages
KR100496817B1 (ko) * 2002-12-30 2005-06-23 주식회사 하이닉스반도체 데이터 정렬 시간을 최소화할 수 있는 반도체 기억 장치
KR100521759B1 (ko) * 2003-03-27 2005-10-17 학교법인 인하학원 모서리 감지 종료 회로 및 이를 이용한 고속의 비동기파이프라인 회로
US6963517B2 (en) * 2003-08-11 2005-11-08 Chao-Wu Chen Parallel asynchronous propagation pipeline structure to access multiple memory arrays
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
KR100753081B1 (ko) * 2005-09-29 2007-08-31 주식회사 하이닉스반도체 내부 어드레스 생성장치를 구비하는 반도체메모리소자
US7515482B2 (en) * 2005-09-29 2009-04-07 Hynix Semiconductor Inc. Pipe latch device of semiconductor memory device
US7391656B2 (en) * 2006-07-25 2008-06-24 Etron Technology, Inc. Self-feedback control pipeline architecture for memory read path applications
US8527802B1 (en) * 2012-08-24 2013-09-03 Cypress Semiconductor Corporation Memory device data latency circuits and methods
US8873264B1 (en) 2012-08-24 2014-10-28 Cypress Semiconductor Corporation Data forwarding circuits and methods for memory devices with write latency
US8933739B1 (en) 2013-07-05 2015-01-13 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
KR102101390B1 (ko) * 2013-10-08 2020-04-17 에스케이하이닉스 주식회사 반도체 장치 및 이를 포함하는 반도체 시스템
US10699053B1 (en) * 2018-01-17 2020-06-30 Xilinx, Inc. Timing optimization of memory blocks in a programmable IC
KR102811361B1 (ko) * 2021-04-28 2025-05-21 양쯔 메모리 테크놀로지스 씨오., 엘티디. 메모리 장치의 페이지 버퍼에서 판독된 데이터에 대한 클록 신호 반환 방식
US12189460B2 (en) * 2021-07-06 2025-01-07 UPBEAT TECHNOLOGY Co., Ltd Error detection and correction method and circuit

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Also Published As

Publication number Publication date
JP5266271B2 (ja) 2013-08-21
JP2011222117A (ja) 2011-11-04
JP2010176839A (ja) 2010-08-12
KR20010042316A (ko) 2001-05-25
JP5580254B2 (ja) 2014-08-27
US6539454B2 (en) 2003-03-25
US20010042162A1 (en) 2001-11-15
CA2233789A1 (en) 1999-10-01
CA2233789C (en) 2013-06-11
CA2805213A1 (en) 1999-10-01

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