KR100609133B1 - 금속 배선 형성 방법 - Google Patents
금속 배선 형성 방법 Download PDFInfo
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- KR100609133B1 KR100609133B1 KR1020040117083A KR20040117083A KR100609133B1 KR 100609133 B1 KR100609133 B1 KR 100609133B1 KR 1020040117083 A KR1020040117083 A KR 1020040117083A KR 20040117083 A KR20040117083 A KR 20040117083A KR 100609133 B1 KR100609133 B1 KR 100609133B1
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- high density
- depositing
- density material
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 title claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 47
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 238000001465 metallisation Methods 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 2
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 claims description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 claims 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052802 copper Inorganic materials 0.000 abstract description 18
- 239000010949 copper Substances 0.000 abstract description 18
- 238000005530 etching Methods 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000003361 porogen Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
그 다음, 상기 고밀도 물질층(13) 상에 반사방지막(14)를 형성하고, 그 위에 트렌치 형성영역을 정의하는 감광막 패턴(15)을 형성한다.
그런 다음, 도시하지는 않았지만, 상기 감광막 패턴(15)을 식각 마스크로 상기 반사방지막(14) 및 고밀도 물질층(13)을 선택적으로 식각하여 트렌치를 형성한다. 상기에서, 고밀도 물질층은 희생 물질로 사용되는 것으로서, 바람직하게는 TEOS (tetra ethyl ortho silicate) 또는 PECVD 방법으로 증착한 FSG 막을 사용할 수 있으며, 이러한 물질은 치밀한 구조를 하고 있기 때문에 트렌치 식각 또는 애싱 공정시 구리의 보우잉 현상이 전혀 생기지 않게 된다.
여기서, 미설명한 화살표는 건식 식각 또는 습식 식각 시 진행되는 식각 방향을 가리킨다.
Claims (9)
- 삭제
- 삭제
- 삭제
- 1) 산화막 상부에 식각 방지막 및 고밀도 물질층을 순차적으로 증착하는 단계;2) 상기 고밀도 물질층을 선택적으로 제거하여 제1 금속배선 트렌치를 형성하는 단계;3) 상기 트렌치 내에 제1 금속배선을 형성하는 단계;4) 상기 고밀도 물질층을 HF/DI 용액 또는 NH4HF/HF/DI을 사용하여 습식 식각하여 제거하는 단계;5) 전체 표면 상부에 확산 방지막을 증착하는 단계; 및6) 전체 표면 상부에 다공성 로우-케이(low-k) 물질층을 증착하는 단계를 포함하는 금속 배선 형성 방법.
- 1) 산화막 상부에 식각 방지막 및 고밀도 물질층을 순차적으로 증착하는 단계;2) 상기 고밀도 물질층을 선택적으로 제거하여 제1 금속배선 트렌치를 형성하는 단계;3) 상기 트렌치 내에 제1 금속배선을 형성하는 단계;4) 상기 고밀도 물질층을 NH3 및 N2/H2 플라즈마로 구성된 군으로부터 선택되는 환원 가스를 사용하여 건식 식각하여 제거하는 단계;5) 전체 표면 상부에 확산 방지막을 증착하는 단계; 및6) 전체 표면 상부에 다공성 로우-케이(low-k) 물질층을 증착하는 단계를 포함하는 금속 배선 형성 방법.
- 삭제
- 삭제
- 제 4항 또는 제5항에 있어서,상기 다공성 로우-케이 물질층은 HSQ (hydrogen silsesquioxane) 또는 MSQ (methyl silsesquioxane)인 것을 특징으로 하는 금속 배선 형성 방법.
- 삭제
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KR1020040117083A KR100609133B1 (ko) | 2004-12-30 | 2004-12-30 | 금속 배선 형성 방법 |
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KR1020040117083A KR100609133B1 (ko) | 2004-12-30 | 2004-12-30 | 금속 배선 형성 방법 |
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KR20060079317A KR20060079317A (ko) | 2006-07-06 |
KR100609133B1 true KR100609133B1 (ko) | 2006-08-08 |
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KR101998788B1 (ko) | 2013-04-22 | 2019-07-11 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US20030219968A1 (en) * | 2001-12-13 | 2003-11-27 | Ercan Adem | Sacrificial inlay process for improved integration of porous interlevel dielectrics |
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Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US20030219968A1 (en) * | 2001-12-13 | 2003-11-27 | Ercan Adem | Sacrificial inlay process for improved integration of porous interlevel dielectrics |
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