KR100604418B1 - 반도체 소자의 금속 배선층 형성방법 - Google Patents
반도체 소자의 금속 배선층 형성방법 Download PDFInfo
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- KR100604418B1 KR100604418B1 KR1020040117086A KR20040117086A KR100604418B1 KR 100604418 B1 KR100604418 B1 KR 100604418B1 KR 1020040117086 A KR1020040117086 A KR 1020040117086A KR 20040117086 A KR20040117086 A KR 20040117086A KR 100604418 B1 KR100604418 B1 KR 100604418B1
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- South Korea
- Prior art keywords
- metal wiring
- layer
- silicon oxynitride
- wiring layer
- film
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
Abstract
Description
Claims (5)
- (a) 소정의 하부 구조를 구비하는 반도체 기판 상부에 티타늄층, 알루미늄층 및 티타늄/티타늄나이트라이드층이 순차적으로 증착된 금속 배선층을 형성하는 단계;(b) 상기 금속 배선층의 상부에 실리콘산화질화막(SiON)을 형성하는 단계;(c) 상기 실리콘산화질화막의 상부에 난반사 방지막을 형성하는 단계; 및(d) 금속배선 마스크를 이용한 사진식각 공정으로 상기 난반사 방지막, 실리콘산화질화막 및 금속 배선층을 식각하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선층 형성방법.
- 제 1 항에 있어서,상기 실리콘산화질화막은 플라즈마 인핸스드 화학적기상 증착법에 의해 300∼5000Å 두께로 형성되고, 굴절률이 1.9∼2.3인 것을 특징으로 하는 반도체 소자의 금속 배선층 형성방법.
- 제 1 항에 있어서,상기 (d) 단계의 난반사 방지막 및 실리콘산화질화막 식각공정은 CHF3/CF4/Ar 가스의 조합으로 이루어진 활성화된 플라즈마를 이용하여 단일 단계의 건식각을 수행하는 공정인 것을 특징으로 하는 반도체 소자의 금속 배선층 형성방 법.
- 제 1 항에 있어서,상기 (d) 단계의 난반사 방지막 및 실리콘산화질화막 식각공정은 O2/N2/Ar 가스의 조합으로 이루어진 활성화된 플라즈마를 이용하여 상기 난반사 방지막을 먼저 식각한 후에 상기 실리콘산화질화막 식각 공정은 별도로 수행하는 것을 특징으로 하는 반도체 소자의 금속 배선층 형성방법.
- 제 1 항에 있어서,상기 (d) 단계의 금속 배선층 식각공정은 Cl2/BCl3/N2 가스의 조합으로 이루어진 활성화된 플라즈마를 이용하는 것을 특징으로 하는 반도체 소자의 금속 배선층 형성방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020040117086A KR100604418B1 (ko) | 2004-12-30 | 2004-12-30 | 반도체 소자의 금속 배선층 형성방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020040117086A KR100604418B1 (ko) | 2004-12-30 | 2004-12-30 | 반도체 소자의 금속 배선층 형성방법 |
Publications (2)
Publication Number | Publication Date |
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KR20060079320A KR20060079320A (ko) | 2006-07-06 |
KR100604418B1 true KR100604418B1 (ko) | 2006-07-25 |
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KR1020040117086A KR100604418B1 (ko) | 2004-12-30 | 2004-12-30 | 반도체 소자의 금속 배선층 형성방법 |
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