KR100588802B1 - 저 전력 클록 분배 방법 - Google Patents

저 전력 클록 분배 방법 Download PDF

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Publication number
KR100588802B1
KR100588802B1 KR1020037016361A KR20037016361A KR100588802B1 KR 100588802 B1 KR100588802 B1 KR 100588802B1 KR 1020037016361 A KR1020037016361 A KR 1020037016361A KR 20037016361 A KR20037016361 A KR 20037016361A KR 100588802 B1 KR100588802 B1 KR 100588802B1
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KR
South Korea
Prior art keywords
transmission line
clock
buffer
clock distribution
signal
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Expired - Lifetime
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KR1020037016361A
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English (en)
Korean (ko)
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KR20040010710A (ko
Inventor
마고시히데타카
Original Assignee
소니 컴퓨터 엔터테인먼트 인코포레이티드
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Publication of KR20040010710A publication Critical patent/KR20040010710A/ko
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Publication of KR100588802B1 publication Critical patent/KR100588802B1/ko
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
KR1020037016361A 2001-06-13 2002-06-12 저 전력 클록 분배 방법 Expired - Lifetime KR100588802B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US29794001P 2001-06-13 2001-06-13
US60/297,940 2001-06-13
US10/113,052 2002-04-01
US10/113,052 US6667647B2 (en) 2001-06-13 2002-04-01 Low power clock distribution methodology
PCT/US2002/018673 WO2002101527A1 (en) 2001-06-13 2002-06-12 Low power clock distribution methodology

Publications (2)

Publication Number Publication Date
KR20040010710A KR20040010710A (ko) 2004-01-31
KR100588802B1 true KR100588802B1 (ko) 2006-06-14

Family

ID=26810660

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020037016361A Expired - Lifetime KR100588802B1 (ko) 2001-06-13 2002-06-12 저 전력 클록 분배 방법

Country Status (6)

Country Link
US (1) US6667647B2 (enExample)
EP (1) EP1395894A4 (enExample)
JP (1) JP4886164B2 (enExample)
KR (1) KR100588802B1 (enExample)
CN (1) CN1267803C (enExample)
WO (1) WO2002101527A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909127B2 (en) * 2001-06-27 2005-06-21 Intel Corporation Low loss interconnect structure for use in microelectronic circuits
JP4457613B2 (ja) * 2003-09-04 2010-04-28 ソニー株式会社 固体撮像装置
US7446622B2 (en) * 2003-09-05 2008-11-04 Infinera Corporation Transmission line with low dispersive properties and its application in equalization
US7109902B2 (en) * 2004-06-30 2006-09-19 Texas Instruments Incorporated Method and system for sampling a signal
KR100808076B1 (ko) * 2005-09-16 2008-03-03 후지쯔 가부시끼가이샤 클록 분배 회로
US20070229115A1 (en) * 2006-01-25 2007-10-04 International Business Machines Corporation Method and apparatus for correcting duty cycle error in a clock distribution network
EP2932610A4 (en) 2012-09-07 2016-10-05 Univ Virginia Patent Found SMALL POWER TRIGGER SOURCE
US20150033050A1 (en) * 2013-07-25 2015-01-29 Samsung Electronics Co., Ltd Semiconductor integrated circuit and computing device including the same
US11579649B1 (en) 2021-12-30 2023-02-14 Analog Devices, Inc. Apparatus and methods for clock duty cycle correction and deskew

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5934032B2 (ja) * 1980-03-06 1984-08-20 日本原子力事業株式会社 信号伝送線路におけるリンギング防止回路
JP2665517B2 (ja) * 1989-09-29 1997-10-22 株式会社日立製作所 終端回路
JPH03186020A (ja) * 1989-12-15 1991-08-14 Mitsubishi Electric Corp 終端回路
DE69125816T2 (de) * 1991-02-21 1997-10-23 Ibm DÜE und Verfahren zur Bearbeitung von DÜE empfangener Daten zum Einsatz verschiedener Betriebsarten
EP0542321A3 (en) * 1991-09-23 1993-06-09 Schlumberger Technologies, Inc. Method and circuit for controlling voltage reflections on transmission lines
JPH05143535A (ja) * 1991-10-18 1993-06-11 Toshiba Corp 半導体集積回路
JPH06332569A (ja) * 1993-05-26 1994-12-02 Nippon Telegr & Teleph Corp <Ntt> 実時間タイマ一致化装置および一致方法
JP2735034B2 (ja) 1995-06-14 1998-04-02 日本電気株式会社 クロック信号分配回路
US5911063A (en) 1996-07-10 1999-06-08 International Business Machines Corporation Method and apparatus for single phase clock distribution with minimal clock skew
JP3441948B2 (ja) 1997-12-12 2003-09-02 富士通株式会社 半導体集積回路におけるクロック分配回路
JP2000200114A (ja) * 1999-01-07 2000-07-18 Nec Corp クロック分配回路
US6249193B1 (en) * 1999-02-23 2001-06-19 International Business Machines Corporation Termination impedance independent system for impedance matching in high speed input-output chip interfacing

Also Published As

Publication number Publication date
CN1267803C (zh) 2006-08-02
JP2005503004A (ja) 2005-01-27
US6667647B2 (en) 2003-12-23
WO2002101527A1 (en) 2002-12-19
CN1514966A (zh) 2004-07-21
EP1395894A4 (en) 2007-04-04
US20020190775A1 (en) 2002-12-19
JP4886164B2 (ja) 2012-02-29
KR20040010710A (ko) 2004-01-31
EP1395894A1 (en) 2004-03-10

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