JP4886164B2 - 低電力クロック分配方法 - Google Patents

低電力クロック分配方法 Download PDF

Info

Publication number
JP4886164B2
JP4886164B2 JP2003504222A JP2003504222A JP4886164B2 JP 4886164 B2 JP4886164 B2 JP 4886164B2 JP 2003504222 A JP2003504222 A JP 2003504222A JP 2003504222 A JP2003504222 A JP 2003504222A JP 4886164 B2 JP4886164 B2 JP 4886164B2
Authority
JP
Japan
Prior art keywords
transmission line
buffer
signal
clock distribution
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2003504222A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005503004A5 (enExample
JP2005503004A (ja
Inventor
英尚 馬越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Interactive Entertainment Inc
Original Assignee
Sony Interactive Entertainment Inc
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Interactive Entertainment Inc, Sony Computer Entertainment Inc filed Critical Sony Interactive Entertainment Inc
Publication of JP2005503004A publication Critical patent/JP2005503004A/ja
Publication of JP2005503004A5 publication Critical patent/JP2005503004A5/ja
Application granted granted Critical
Publication of JP4886164B2 publication Critical patent/JP4886164B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
JP2003504222A 2001-06-13 2002-06-12 低電力クロック分配方法 Expired - Lifetime JP4886164B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US29794001P 2001-06-13 2001-06-13
US60/297,940 2001-06-13
US10/113,052 2002-04-01
US10/113,052 US6667647B2 (en) 2001-06-13 2002-04-01 Low power clock distribution methodology
PCT/US2002/018673 WO2002101527A1 (en) 2001-06-13 2002-06-12 Low power clock distribution methodology

Publications (3)

Publication Number Publication Date
JP2005503004A JP2005503004A (ja) 2005-01-27
JP2005503004A5 JP2005503004A5 (enExample) 2005-08-04
JP4886164B2 true JP4886164B2 (ja) 2012-02-29

Family

ID=26810660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003504222A Expired - Lifetime JP4886164B2 (ja) 2001-06-13 2002-06-12 低電力クロック分配方法

Country Status (6)

Country Link
US (1) US6667647B2 (enExample)
EP (1) EP1395894A4 (enExample)
JP (1) JP4886164B2 (enExample)
KR (1) KR100588802B1 (enExample)
CN (1) CN1267803C (enExample)
WO (1) WO2002101527A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909127B2 (en) * 2001-06-27 2005-06-21 Intel Corporation Low loss interconnect structure for use in microelectronic circuits
JP4457613B2 (ja) * 2003-09-04 2010-04-28 ソニー株式会社 固体撮像装置
US7446622B2 (en) * 2003-09-05 2008-11-04 Infinera Corporation Transmission line with low dispersive properties and its application in equalization
US7109902B2 (en) * 2004-06-30 2006-09-19 Texas Instruments Incorporated Method and system for sampling a signal
KR100808076B1 (ko) * 2005-09-16 2008-03-03 후지쯔 가부시끼가이샤 클록 분배 회로
US20070229115A1 (en) * 2006-01-25 2007-10-04 International Business Machines Corporation Method and apparatus for correcting duty cycle error in a clock distribution network
EP2932610A4 (en) 2012-09-07 2016-10-05 Univ Virginia Patent Found SMALL POWER TRIGGER SOURCE
US20150033050A1 (en) * 2013-07-25 2015-01-29 Samsung Electronics Co., Ltd Semiconductor integrated circuit and computing device including the same
US11579649B1 (en) 2021-12-30 2023-02-14 Analog Devices, Inc. Apparatus and methods for clock duty cycle correction and deskew

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5934032B2 (ja) * 1980-03-06 1984-08-20 日本原子力事業株式会社 信号伝送線路におけるリンギング防止回路
JP2665517B2 (ja) * 1989-09-29 1997-10-22 株式会社日立製作所 終端回路
JPH03186020A (ja) * 1989-12-15 1991-08-14 Mitsubishi Electric Corp 終端回路
DE69125816T2 (de) * 1991-02-21 1997-10-23 Ibm DÜE und Verfahren zur Bearbeitung von DÜE empfangener Daten zum Einsatz verschiedener Betriebsarten
EP0542321A3 (en) * 1991-09-23 1993-06-09 Schlumberger Technologies, Inc. Method and circuit for controlling voltage reflections on transmission lines
JPH05143535A (ja) * 1991-10-18 1993-06-11 Toshiba Corp 半導体集積回路
JPH06332569A (ja) * 1993-05-26 1994-12-02 Nippon Telegr & Teleph Corp <Ntt> 実時間タイマ一致化装置および一致方法
JP2735034B2 (ja) 1995-06-14 1998-04-02 日本電気株式会社 クロック信号分配回路
US5911063A (en) 1996-07-10 1999-06-08 International Business Machines Corporation Method and apparatus for single phase clock distribution with minimal clock skew
JP3441948B2 (ja) 1997-12-12 2003-09-02 富士通株式会社 半導体集積回路におけるクロック分配回路
JP2000200114A (ja) * 1999-01-07 2000-07-18 Nec Corp クロック分配回路
US6249193B1 (en) * 1999-02-23 2001-06-19 International Business Machines Corporation Termination impedance independent system for impedance matching in high speed input-output chip interfacing

Also Published As

Publication number Publication date
KR100588802B1 (ko) 2006-06-14
CN1267803C (zh) 2006-08-02
JP2005503004A (ja) 2005-01-27
US6667647B2 (en) 2003-12-23
WO2002101527A1 (en) 2002-12-19
CN1514966A (zh) 2004-07-21
EP1395894A4 (en) 2007-04-04
US20020190775A1 (en) 2002-12-19
KR20040010710A (ko) 2004-01-31
EP1395894A1 (en) 2004-03-10

Similar Documents

Publication Publication Date Title
US6378080B1 (en) Clock distribution circuit
US6772362B2 (en) System for distributing clock signal with a rise rate such that signals appearing at first and second output terminals have substantially no signal skew
CN1523842B (zh) 信号传输装置与互连结构
JP3957237B2 (ja) 集積回路装置モジュール
JP4886164B2 (ja) 低電力クロック分配方法
US20050168956A1 (en) Printed wiring board for controlling signal transmission using paired inductance and capacitance
US20060092929A1 (en) Interwoven clock transmission lines and devices employing the same
US6873533B2 (en) Unbuffered memory system
Flynn et al. Global signaling over lossy transmission lines
US6208702B1 (en) High frequency clock signal distribution utilizing CMOS negative impedance terminations
US5994924A (en) Clock distribution network with dual wire routing
US6011441A (en) Clock distribution load buffer for an integrated circuit
JP5277700B2 (ja) クロック分配回路、半導体集積回路、およびクロック分配方法
US6919619B2 (en) Actively-shielded signal wires
JP2005503004A5 (enExample)
US6144224A (en) Clock distribution network with dual wire routing
JP2002094489A (ja) データ伝送回路
US5438297A (en) Electrical trace having a closed loop configuration
JP4272149B2 (ja) 方向性結合器を用いたデータ転送方式
JP4625798B2 (ja) 半導体装置
Balachandran et al. Constant impedance scaling paradigm for scaling LC transmission lines
JP2006526335A (ja) バッファ回路
US20070229115A1 (en) Method and apparatus for correcting duty cycle error in a clock distribution network
US6519747B2 (en) Method and apparatus for defining signal timing for an integrated circuit device
WO2008097309A1 (en) Method and apparatus for correcting duty cycle error in a clock distribution network

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070731

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071001

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090526

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090826

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20090907

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20091002

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20100714

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20100818

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20110108

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20110111

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111031

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20111209

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20141216

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4886164

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term