KR100566983B1 - Apparatus and method for providing synchronous clock in duplexing board - Google Patents

Abstract

The present invention provides a synchronization clock providing apparatus and method for a redundant board, comprising: a clock extracting unit for extracting a clock from a medium to be interfaced; A clock generator for generating a required clock from the clock extracted by the clock extractor; By including a clock synchronizing unit for analyzing the clock generated by the clock generator to reproduce the synchronized clock and provide it to other boards, switching between the boards occurs by synchronizing the clocks in accordance with the current state in both boards Even when the clock phase difference does not occur.

Description

Apparatus and method for providing synchronous clock of redundant boards {Apparatus and method for providing synchronous clock in duplexing board}

1 is a block diagram of a conventional clock providing apparatus of a redundant board;

2 is a flowchart illustrating a clock providing method of a conventional redundant board;

3 is a conceptual diagram showing a phase difference of a clock provided by the prior art;

4 is a block diagram of an apparatus for providing a synchronous clock of a redundant board according to the present invention;

5 is a flowchart illustrating a synchronization clock providing method of a redundant board according to the present invention;

6 is a conceptual diagram showing that a synchronization clock is generated by the present invention,

7 is a table showing an example of clock adjustment according to active / standby switching according to the present invention.

Explanation of symbols on the main parts of the drawings

10a: A side (active) 10b: B side (standby)

20: clock extractor 30: clock generator

40: clock synchronization unit 41: output buffer

42: input buffer 43: synchronization controller

44: memory section

The present invention relates to an apparatus and a method for providing a synchronous clock of a redundant board, in particular, to synchronize the clock according to the current state in both redundant boards, so that the phase difference of the clock does not occur even when switching between boards occurs. The present invention relates to a synchronization clock providing apparatus of a redundant board and a method thereof.

In general, redundancy is the use of two computers, peripherals, boards, or other circuitry within a system, so that one can continue to operate the system when one fails or fails or replaces the system.

Thus, when there is a board named 'I' which plays the role of 'A' in a system, the board is mounted in the form of A / B so that there is no problem in performing the role of 'A' even if a problem occurs in the board. In this chapter, only one of the two chapters plays the role of 'A', and when there is an error in one of the boards, the other board replaces the role.

This redundancy is implemented in a number of ways, depending on its importance, and so on.

On the other hand, in the case of communication systems, boards are often configured in a redundant structure to ensure stability. In other words, if one board fails to operate, the other board operates normally so that it does not interfere with the overall system operation.

1 is a block diagram of a conventional clock providing apparatus of a redundant board.

As shown therein, a clock extracting unit (2) which extracts a clock required by a current board by distinguishing a reference clock transmitted from an interfaced transmission medium; Based on the clock extracted from the clock extractor 2, a clock to be provided to the other board 4 is generated and provided to the other board 4, and a more effective clock is provided among the clocks provided to the other board 4. It consists of a clock generation section (3) informing what is.

Here, reference numeral 1a denotes an active side provided with a clock extractor 2 and a clock generator 3, and 1b denotes a standby side provided with a clock extractor 2 and a clock generator 3.

2 is a flowchart illustrating a clock providing method of a conventional redundant board.

As shown therein, steps of receiving a reference clock to extract a clock (ST11) (ST12); Based on the extracted clock, a required clock is generated and provided to the other board 4, and steps (ST13 to ST15) indicating which clock is more effective than the clock provided to the other board 4 is performed.

The operation of the prior art configured as described above will be described in detail with reference to the accompanying drawings.

First, both the active 1a and the standby 1b are provided with the clock extracting unit 2 and the clock generating unit 3 in the same manner.

Therefore, the clock extractor 2 extracts the clock required by the other board 4 which is the current system by distinguishing the reference clock received from the transmission medium to be interfaced.

Then, the clock generator 3 generates a clock to be provided to another board 4 which is another system based on the clock to be extracted by the clock extractor 2. The generated clock is then transmitted according to the promised interface format.

In addition, it performs a function of informing the other board 4 which is a more valid clock than two clocks provided.

This prior art is described in more detail.

Each redundant board receives a reference clock from the interface medium (STM (Synchronous Transport Module), E1, etc.) and extracts it for use.

Also, based on this signal, necessary clock is generated and transferred to other system.

However, in the case of redundancy, the clocks can be transmitted from the active board and the standby board, respectively. Therefore, it is necessary to inform the system receiving the clock which clock is more valid than the current state.

Therefore, in general, a clock valid signal is generated to recognize a clock of an active board as a valid clock.

However, this conventional technology has the following problems.

In other words, when a clock is provided by a redundant board as in the related art, even if the function of the active board is interrupted, the standby board may be converted to active and continue to perform the function.

3 is a conceptual diagram illustrating a phase difference of a clock provided by the prior art.

Therefore, as shown in FIG. 3, in the case of a clock, the phases of the clocks extracted from each board may not exactly match each other. Therefore, when switching between boards occurs, data loss may occur due to a slight phase difference in another system receiving the clock. There was a problem that could occur.

Accordingly, the present invention has been proposed to solve the above-mentioned general problems, and an object of the present invention is to generate a reference clock based on a clock received from an apparatus such as an STM framer of a communication system and to interwork it. Apparatus and method for providing a synchronous clock for a redundant board that can synchronize the clocks according to the current state in both redundant boards so that a phase difference of the clock does not occur even when switching between the boards occurs. To provide.

In order to achieve the above object, a synchronization clock providing apparatus of a redundant board according to an embodiment of the present invention,

A clock extractor for extracting a clock from an interfaced medium; A clock generator for generating a required clock from the clock extracted by the clock extractor; Technical features of the present invention include a clock synchronizing unit which analyzes the clock generated by the clock generating unit and reproduces the synchronized clock and provides it to another board.

In order to achieve the above object, a synchronization clock providing method of a redundant board according to an embodiment of the present invention,

Extracting a clock upon receiving a reference clock; A second step of generating a required clock after the first step; And a third step of analyzing a clock generated after the second step, reproducing a synchronized clock, and providing the same to another board.

Hereinafter, an embodiment of the present invention as described above, an apparatus for providing a synchronous clock of a redundant board and a method thereof will be described with reference to the accompanying drawings.

4 is a block diagram of an apparatus for providing a synchronous clock of a redundant board according to the present invention.

As shown therein, a clock extractor 20 for extracting a clock from a medium to be interfaced; A clock generator 30 for generating a required clock from the clock extracted by the clock extractor 20; The clock generator 30 includes a clock synchronizer 40 which analyzes the clock generated by the clock generator 30 and reproduces the synchronized clock and provides it to another board.

The clock synchronizer 40 includes: an output buffer 41 for distributing and transmitting a clock received from the clock generator 30 in two directions; An input buffer 42 for receiving an output of the output buffer 41 on its own side and a clock of the output buffer 41 on the other side; A synchronization controller 43 for analyzing the signal transmitted from the input buffer 42 and reproducing it with a synchronized clock and providing it to another board; And a memory unit 44 connected to the synchronization adjusting unit 43 to store the state of the current side.

In the above, the synchronization controller 43 bypasses the clock of its own side in the active mode, synchronizes the phase with the reference clock transmitted from the active side in the standby mode, and is stored in the standby mode in the converted active mode. Apply the phase adjustment value to provide the adjusted clock.

The synchronization controller 43 includes a delay buffer and compares the phases once again by passing the delay buffer when the phases are not the same as those of the reference clock in the standby state.

In the above-described memory unit 44, the phase adjustment value is stored when the phase of the clock is changed to the active state by storing the value of the phase of the clock of the magnetic side in comparison with the reference clock in the standby state.

5 is a flowchart illustrating a synchronization clock providing method of a redundant board according to the present invention.

As shown therein, a first step (ST21) (ST22) of extracting a clock upon receiving the reference clock; A second step ST23 for generating a required clock after the first step; And a third step ST24 of analyzing a clock generated after the second step, reproducing a synchronized clock, and providing the same to another board.

In the third step, the clock adjusted by applying an active mode for bypassing the clock of its own side, a standby mode for matching phase with a reference clock transmitted from the active side, and a phase adjustment value stored in the standby mode is applied. Provides conversion including active mode.

In the third step, the standby mode stores a value of adjusting a phase of a clock of a magnetic side in comparison with a reference clock so that a phase adjusting value is applied when it is changed to an active state.

Referring to the accompanying drawings, the operation of the synchronization clock providing apparatus and method of the redundant board according to the present invention configured as described above will be described in detail as follows.

First, the present invention generates a reference clock based on a clock received from a device such as a STM (Synchronous Transport Module) framer of a communication system and provides it to an interlocking block. According to this, the clock phase is synchronized so that the phase difference of the clock does not occur even when switching between boards occurs.

FIG. 6 is a conceptual diagram illustrating that a synchronous clock is generated by the present invention, and FIG. 7 is a table showing an example of clock adjustment according to active / standby switching according to the present invention.

Therefore, in the present invention, the output buffer 41 and the input buffer 42 are provided for clock synchronization with the partner board.

The output buffer 41 emits two signals, one of which is transmitted to the other side and the other of the signal to the input buffer 42 of its side.

In the input buffer 42, two signals from the output buffer 42 of the other side and two signals from the output buffer 42 of the magnetic side are inputted.

These two signals are transmitted to the synchronization controller 43. At this time, the clock generator 30 through the synchronization controller 43 passes both the output buffer 41 and the input buffer 42 once. Therefore, the ideal signal delay of each signal is the same.

The synchronization controller 43 synchronizes the signal with two input signals. At this time, the state of the current side is divided into initial active mode / standby mode / converted active mode as follows.

1) Initial active mode

Initially active is an initial active state in which no initial transfer has occurred.

In this state, the synchronization controller 43 sends the clock transmitted from the clock generator 30 of the magnetic side to the other board without phase adjustment.

However, instead of sending the clock from the clock generator 30 directly to the outside, the synchronization controller 43 bypasses the on-signal through the output buffer 41 and the input buffer 42. .

Therefore, the signal delay along the buffer becomes the same as the standby side.

2) standby mode

In the standby mode, the clock of the magnetic side is adjusted to the same phase based on the clock transmitted from the active side.

As shown in FIG. 6, when the phases are not the same while comparing the phase difference between the input reference clock and the clock of the current magnetic side, the phases are compared again by passing through the memory unit 44.

This operation is repeated, and it remembers how many delay buffers it passed when the phases became the same, and sends the signal out.

Therefore, in the standby mode, the current phase adjustment range is memorized in preparation for the transfer.

3) converted active mode

The converted active mode is a mode converted from the standby mode to the active mode, and unlike the initial active, it uses the phase adjusted clock used in the standby mode.

In other words, when the board used as standby becomes active, the input of the reference clock will be lost. If it is active but sends the clock of its own side, the phase difference from the previous clock will occur.

Therefore, by using the phase adjustment range stored in the standby mode as it is, the clock generated on the magnetic side is adjusted using the synchronization controller 43 and then exported to the outside.

Meanwhile, referring to the table of FIG. 7, an example of a clock control method according to active / standby switching between the A side and the B side is shown. Here, the delay buffer refers to the example of FIG. 6.

So in case of # 1, if A side is active and B side is in standby state, A side generates and outputs its own clock and B side performs 2 buffer delays.

In case of # 2, when A side is open and B side becomes active (B side becomes active due to the failure of A side), A side does not generate clock and B side 2 buffer delay Do this.

In case of # 3, when the A side is in the standby state and the B side is active (transformed active), the A side performs 3 buffer delays and the B side performs 2 buffer delays.

In the case of # 4, when the A side becomes active again (transitioned active) and the B side becomes standby, the A side performs 3 buffer delays and the B side performs 1 buffer delay.

As such, the present invention synchronizes the clocks according to the current state in both redundant boards so that the phase difference of the clocks does not occur even when switching between boards occurs.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the apparatus for providing a synchronous clock of a redundant board according to the present invention and a method thereof provide synchronization between clocks according to a current state of both redundant boards so that a phase difference of a clock does not occur even when switching between boards occurs. It will work.

In addition, the present invention eliminates the interruption of clock provision due to redundancy, and generates and provides a synchronized clock, thereby minimizing data loss during redundancy switching, thereby improving the reliability of the system.

Claims (8)

delete A clock extractor for extracting a clock from an interfaced medium; A clock generator for generating a required clock from the clock extracted by the clock extractor; An output buffer configured to transmit the clock received by the clock generator in two directions; An input buffer for receiving an output of the output buffer on its own side and a clock of the output buffer on the other side; A synchronization controller which analyzes the signal transmitted from the input buffer and reproduces the synchronized clock to provide to another board; The memory unit is connected to the synchronization control unit and stores a current side state. The clock generation unit analyzes the clock generated by a synchronized clock and comprises a clock synchronization unit configured to provide to another board. Synchronous clock providing device of redundancy board. The method of claim 2, wherein the synchronization control unit, In the active mode, the clock on the magnetic side is bypassed. In the standby mode, the clock is phased with the reference clock transmitted from the active side. In the active mode, the clock is adjusted by applying the phase adjustment value stored in the standby mode. Apparatus for providing a synchronous clock of a redundant board, characterized in that provided. The method of claim 3, wherein the synchronization control unit, And a delay buffer to compare the phases again by passing the delay buffer when the phases are not the same as those of the reference clock in the standby state. The memory unit of claim 2, wherein the memory unit includes: The apparatus for providing a synchronous clock of a redundant board according to claim 1, wherein the phase adjustment value is stored when the phase of the clock of the magnetic side is adjusted in comparison with the reference clock in the standby state. delete Extracting a clock upon receiving a reference clock; A second step of generating a required clock after the first step; Analyzing the clock generated after the second step and reproducing the synchronized clock to provide to another board, an active mode for bypassing a clock of its own side, and a standby mode for matching phase with a reference clock transmitted from the active side; And a conversion active mode providing a clock adjusted by applying a phase adjustment value stored in the standby mode. The method of claim 7, wherein the standby mode in the third step, A method of providing a synchronous clock of a redundant board comprising: storing a phase adjusted value of a clock of a magnetic side in comparison with a reference clock so that a phase adjusted value is applied when it is changed to an active state.

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