JP2001007792A - Method and device for generating extract reference clock signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the phase variation of the output of an extract reference signal generation circuit by self-traveling a first phase synchronous oscillator (PLO) and supplying the output of m-th PLO to the extracted reference signal generation circuit when a selected extract clock signal becomes abnormal. SOLUTION: When an extract clock switch circuit 19 detects that a selected extract clock signal is cut, a transmission clock signal that PLO 7 outputs is inputted to an extract reference 8k generation circuit 20, a switch 21 is controlled and the contact point is opened. Thus, PLO 5 becomes a self-traveling state. The extract clock switch circuit 19 selects a next normal extract clock signal and inputs the extract clock signal to the extract reference 8k generation circuit 20. The extract clock switch circuit 19 controls the switch 21, closes the contact point, inputs the output of the extract reference 8k generation circuit 20 to PLO 5 and restores PLO 5 from the self-traveling state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for generating an extracted reference clock signal, and more particularly to a method and apparatus for distributing an extracted reference clock signal in a transmission apparatus based on a clock signal extracted from a transmission line when a synchronization method of the transmission apparatus or the like is in a slave mode. The present invention relates to a method and an apparatus for generating an extracted reference clock signal for obtaining a clock signal.

[0002]

2. Description of the Related Art FIG. 2 is a diagram showing a configuration of an apparatus for explaining a conventional method of generating an extracted reference clock signal.
This is an example in which the extracted reference clock signal is set to 8 kHz. In FIG. 1, reference numeral 1 denotes a transmission line interface board, which comprises a clock extraction circuit 1a and an extraction reference 8k generation circuit 1b. The clock extraction circuit 1a extracts a clock signal included in the received signal transmitted from the transmission line (# 1), and extracts the extraction reference 8k generation circuit 1.
b has a function of dividing the frequency of the clock signal extracted by the clock extraction circuit 1a to 8 kHz, which is the extracted reference clock signal. Transmission line interface boards 2 and 3 having the same configuration are provided corresponding to the transmission paths (# 2) to (#n), respectively, and the output of each transmission path interface board is supplied to a clock board 8. The clock board 8 has a plurality of extraction standards 8k input from the transmission line interface boards 1 to 3.
Based on an extraction reference 8k switching circuit 4 for selecting a desired signal from a clock signal and an output of the extraction reference 8k switching circuit 4,
A phase-locked oscillator (hereinafter, referred to as PLO) 5, 6, and 7 for generating a plurality of clock signals necessary for the transmission device is provided.

The operation of FIG. 2 will be described. The clock extraction circuit 1 provided in the transmission line interface boards 1, 2 and 3 will be described.
a, 2a and 3a extract a pulse repetition component from the transmitted received signal, and the extracted clock signal is used as an extraction reference 8k generation circuit 1b, 2b and 3b to generate an 8 kHz internal reference clock signal in the apparatus. In order to perform the frequency division, the signal is input to the extraction reference 8k switching circuit 4. The extraction reference 8k switching circuit 4 monitors the reception state of the extraction reference 8k clock signal output from the plurality of transmission line interface boards 1, 2, and 3, and selects a normal extraction reference clock signal in a predetermined order. Output. The selected extraction reference 8k clock signal is input to the PLO 5, and a stable clock signal without jitter is generated. PLO5
As the clock signal output by the device, in addition to various clock signals required in the device, a device 8k clock signal to be supplied to the PLOs 6 and 7 is output. The PLOs 6 and 7 use the device 8k clock signal output from the PLO 5 as an input signal.
The output clock signals O6 and O7 are phase-synchronized with the PLO5. Therefore, all the outputs of the PLOs 5, 6, and 7 are phase-synchronized with the extraction reference 8k clock signal generated based on the clock signal extracted from any of the transmission lines (# 1 to #n). The PLOs 6 and 7 output a stable clock signal and are used for various purposes. Next, when the output of the selected extraction reference 8k clock signal becomes abnormal, the extraction reference 8k switching circuit 4 switches to the extraction reference 8k clock signal supplied from another transmission line interface board. When all the extraction reference 8k clock signals become abnormal, the PLO 5 supplies the clock signal as a self-running state.

[0004]

Since a plurality of extraction reference 8k clock signals generated in each transmission line interface board are asynchronous with each other, when the extraction reference 8k clock signal is switched and when the PLO recovers from self-running, P
There is a possibility that the phase fluctuation between the extraction reference 8k clock signal input to the LO and the output clock signal of the PLO becomes large, and this may affect the transmission of the transmission / reception signal in the process of pulling in the PLO at this time. Therefore, in order to avoid the influence on the transmission of the transmission / reception signal described above, a phase control circuit is added to the conventional method of generating the extracted reference clock signal, and the extraction reference signal generated based on the clock signal extracted from each transmission path is added. The phase of the output of the 8k generation circuit is matched. FIG. 3 is an example of an apparatus for implementing a conventional method of generating an extracted reference clock signal to which a phase control function is added. In FIG. 1, reference numeral 9 denotes a transmission line interface board, which comprises a clock extraction circuit 9a, an extraction reference 8k generation circuit 9b, and an extraction reference 8k phase control circuit 9c. The clock extraction circuit 9a extracts a clock signal from the received signal transmitted from the transmission line (# 1), and the extraction reference 8k generation circuit 9b converts the clock signal extracted by the clock extraction circuit 9a into an extraction reference clock signal of 8 kHz. It has a function of dividing so that The extraction reference 8k phase control circuit 9c controls the phase of the output of the transmission line interface board 9 supplied to the clock board 15. The transmission line interface boards 10 and 11 having the same configuration are each a transmission line (# 2)
The output of each transmission line interface board is supplied to the clock board 15. The clock board 15 includes a clock control circuit 14 including an extraction reference 8k switching section 12 and a transmission line interface board control section 13.
And PLO5-7, each transmission line interface panel 9
To the extraction reference 8k generation circuit, and a desired signal is selected by the extraction reference 8k switching circuit 12, and the extraction reference 8k clock signal of the transmission line interface board not selected by the clock control circuit 14 is output. By transmitting a control signal from the transmission path interface board control unit 13 to the extraction reference 8k phase control circuit of each transmission path interface board so as to synchronize the phase with the extraction reference 8k clock signal of the selected transmission path interface board, all extractions are performed. The reference 8k clock signal is phase-synchronized with the currently selected extraction reference 8k clock signal. However, the conventional method for generating an extracted reference clock signal to which a phase control circuit is added requires control circuits 9a to 11c for all transmission path interface boards, and further requires the clock board 15 to control each transmission path interface board. Wiring is also required, and there has been a problem that the circuit scale increases and the device cost increases. SUMMARY OF THE INVENTION The present invention has been made to solve the problem of the above-described conventional method of generating an extracted reference clock signal, and has an object to output a clock signal at the time of switching the subordinate destination of the extracted clock signal and at the time of recovery from PLO free running. An object of the present invention is to provide a low-cost method for generating an extracted reference clock signal in which a signal does not cause a phase change.

[0005]

According to a first aspect of the present invention, there is provided a method for generating an extracted reference clock signal, comprising selecting one clock signal having a frequency f1 extracted from a plurality of transmission paths. A frequency f2, which is obtained by dividing the selected extracted clock signal and serving as a reference input of the phase locked oscillator.
Is generated, where the frequency f1
>> f2, the extracted reference clock signal is input to a first phase-locked oscillator to generate a clock signal of a desired frequency, and the output of the first phase-locked oscillator is input to an m-th phase-locked oscillator to perform the extraction. A transmission clock signal having the same frequency as the reference clock signal is generated, and when the output of the extracted clock signal extracted from the transmission line is cut off, the first phase-locked oscillator is free-running and the transmission output by the m-th phase-locked oscillator is output. A clock signal is input to the extracted reference clock signal generating means, and at the time of recovery of the extracted clock signal, an extracted clock signal extracted from a transmission line is input to the extracted reference clock signal generating means, and the first phase locked oscillator is free-running. , The phase fluctuation of the extracted reference clock signal is suppressed when the extracted clock signal fails. According to a second aspect of the present invention, there is provided an extracted reference clock signal generating apparatus, comprising: an extracted clock switching circuit for inputting an extracted clock signal having a frequency f1 from a plurality of transmission paths; An extraction reference signal generation circuit that generates a clock signal (f1 >>f2); a first phase-locked oscillator that generates a signal of frequency f2 synchronized with the output of the extraction reference signal generation circuit; An m-th phase-locked oscillator that generates a signal having the same frequency f1 as the extracted clock signal, and outputs the m-th phase-locked oscillator when the extracted clock signal selected in the extracted clock switching circuit is cut off. Drives the extraction reference signal generation circuit based on the above, and allows the first phase locked oscillator to run by itself, and then outputs the extraction clock signal from another transmission line. -Option and drives the extracted reference signal generation circuit based on the extraction clock signal, and driving the first phase locked oscillator based on the extraction reference signal generating circuit output,
When the extracted clock signals from all the transmission lines are cut off, the extraction reference signal generation circuit is driven based on the m-th phase-locked oscillator output, and the first phase-locked oscillator is allowed to run by itself, By selecting the extracted clock signal from the transmission line, driving the extracted reference signal generation circuit based on the extracted clock signal, and driving the first phase locked oscillator based on the output of the extracted reference signal generation circuit, The phase fluctuation of the output of the first phase-locked oscillator due to the switching of the extracted clock signal is suppressed. 4. The extracted reference clock signal generation device according to claim 3, wherein the extracted clock signal is a 1.544 MHz signal, and the output of the reference signal generation circuit is an 8 kHz signal.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on illustrated embodiments. FIG. 1 is a diagram showing an embodiment of a device configuration for carrying out a method for generating an extracted reference clock signal according to the present invention.
z. As shown in the figure, a plurality of transmission line interface boards 16, 17 and 18 each including a clock extraction circuit 16a, 17a and 18a for extracting a clock signal from a reception signal sent from each transmission line,
A clock board 22 for inputting an extracted clock signal from each transmission path interface board. The clock board 22 includes an extraction clock switching circuit 19 for selecting a plurality of input clock signals, and an extraction reference 8k generation circuit 20 for dividing the selected extraction clock signal to generate an extraction reference 8k clock signal (extraction reference clock signal). (Extraction reference signal generation circuit), a switch 21 serving as a switching means for performing a circuit disconnection operation in the event of a clock extraction operation failure, and a stable phase synchronized with the extraction reference 8k clock signal based on the generated extraction reference 8k clock signal. PLO5 for generating various clock signals and distributing them in the transmission device, PLO6 for generating various clock signals necessary for the transmission device in phase synchronization with the output signal of PLO5 and distributing them in the transmission device, and output signals of PLO5 Clock signal of the same frequency as the clock signal extracted from each transmission line interface board in phase with And a PLO7 to generate.

The operation of FIG. 1 will be described. First, the transmission speed on the transmission line side is set to the same transmission speed for all of the plurality of transmission lines, and the clock extraction circuits 16a, 17a, and 18a provided in the transmission line interface boards 16, 17, and 18 A pulse repetition component is extracted from the transmitted received signal and is used as a clock signal. At this time, the extracted clock signals extracted from the plurality of transmission paths are each asynchronous. The clock signal extracted by the clock extraction circuit (16a, 17a, 18a) of each transmission path interface board (16, 17, 18) is input to the extraction clock switching circuit 19, and is determined from the plurality of extraction clock signals. One extracted clock signal is selected according to the procedure. The selected extracted clock signal is input to an extraction reference 8k generation circuit 20 including a frequency dividing circuit, and the extraction reference 8k serving as a reference clock signal of the PLO 5 is extracted.
Generate a clock signal. The extracted clock signal to be extracted from the signal received from the transmission line is an extraction reference signal which becomes the reference clock signal of the PLO 5 such as 1.544 Mb / s.
The frequency is higher than that of the k clock signal. Extraction criteria 8
The output of the k generation circuit 20 is output to the PLO5 through the switch 21.
To enter. The switch 21 is connected to the extraction clock switching circuit 19
The switch 2 is used to disconnect the circuit when the output of the extracted clock signal selected in step 2 is cut off.
The control of 1 is performed by the extraction clock switching circuit 19.
The PLO 5 receiving the extraction reference 8k clock signal generates various clock signals that are phase-synchronized with the extraction reference 8k clock signal. The device 8k clock signal output from PLO5 is used as a reference clock signal for PLO6 and PLO7, and various clock signals output from PLO6 and PLO7 are phase-synchronized with the output clock signal from PLO5. Therefore, the various stable clock signals output from the PLOs 5, 6, and 7 are all phase-synchronized with the output signal of the extraction reference 8k generation circuit 20. PLO7 is an extracted clock signal extracted from the transmission line interface board, for example, 1.544.
The transmission clock signal of Mb / s is output and used in the transmission unit of the transmission device, and is extracted when the output of the extraction clock signal from the transmission line interface board selected via the extraction clock switching circuit 19 is cut off. It has a function of supplying a transmission clock signal to the reference 8k generation circuit 20.

PL for generating various stable clock signals
O5, 6 and 7 are constituted by phase synchronization circuits. The operation of the phase locked loop circuit will be described. The phase of the output signal of the phase locked loop circuit is compared with the phase of the input signal, and a voltage corresponding to the phase difference between the two signals is generated. To synchronize the phases of the output signal and the input signal of the phase synchronization circuit. When the input signal of the phase locked loop circuit serving as the reference clock signal is interrupted, the phase locked loop circuit runs at a predetermined frequency. Also, various clock signals can be generated by changing the output frequency and the frequency division ratio of the voltage controlled oscillator provided in the phase locked loop.

Next, when the extracted clock switching circuit 19 detects that the extracted clock signal output from the selected transmission line interface board has been cut off, the extracted clock switching circuit 19 first outputs the PLO 7 The input transmission clock signal is input to the extraction reference 8k generation circuit 20, and the switch 21 is controlled to open its contact. Therefore, PLO5 is in a self-running state. In this state, since the extraction reference 8k generation circuit 20 operates by the transmission clock signal output from the PLO 7, the output is in phase synchronization with the clock signal output from the self-running PLO 5, and the standby state is maintained. And In the meantime, the extracted clock switching circuit 19 searches for the next normal subordinate, and when a corresponding transmission line interface board is detected, selects the extracted clock signal and inputs the extracted clock signal to the extraction reference 8k generation circuit 20. Further, the extraction clock switching circuit 19 controls the switch 21 to close its contact, inputs the output of the extraction reference 8k generation circuit 20 to the PLO 5,
5 is restored from the self-propelled state. By the above procedure, the selection switching of the extracted clock signal by the extracted clock switching circuit 19 is completed. However, compared with the extraction reference 8k clock signal input to the PLO 5, each transmission line interface board and P
Since the extracted clock signal supplied from the LO 7 has a much higher frequency, even if the extracted clock signal is switched in the extracted clock switching circuit 19, the phase fluctuation of the extracted reference 8k clock signal generated by the extraction reference 8k generation circuit occurs. Therefore, phase fluctuations of various clocks output from the PLOs 5, 6, and 7 do not occur, and transmission of transmission / reception signals is not affected.

On the other hand, when all the extracted clock signals output from the transmission line interface board are cut off, the extracted clock switching circuit 19 selects the transmission clock signal output from the PLO 7 and outputs it to the extraction reference 8k generation circuit 20,
By controlling the switch 21, the contact is opened to bring the PLO 5 into a self-running state. In this state, the extraction reference 8k generation circuit 2
Since 0 is phase-synchronized with the transmission clock output from the PLO 7, it is also phase-synchronized with the PLO 5, and in this state, it stands by until an extracted clock signal is detected. Next, when the extracted clock switching circuit 19 detects an extracted clock signal from any of the transmission line interface boards, it enters a clock signal selection state, inputs the selected extracted clock signal to the extraction reference 8k generation circuit 20, and then controls the switch 21. Then, the contact is closed, an extraction reference 8k clock signal is input to the PLO 5, and the PLO 5 is restored from the self-running state. Therefore, the input signal of the extraction criterion 8k generation circuit 20 is P
Even if the output is switched from the LO7 output to any of the transmission line interface board outputs, the output of the extraction reference 8k generation circuit 20 does not cause a phase change, and the extraction reference 8k generated based on the extracted clock signal supplied from the transmission line interface board. All output clock signals output from the PLOs 5, 6, and 7 are synchronized in phase with the clock signal. In the selection operation of the extracted clock signal, the transmission of the transmission / reception signal is not affected as described above.

[0011]

According to the first, second and third aspects of the present invention, the extracted clock signal of the frequency f1 inputted from the transmission line is provided.
When the selected signal becomes abnormal, the frequency f2 (f1
>> The self-running first phase-locked oscillator driven based on the output of the extracted reference signal generation circuit of f2), and the frequency of the m-th phase-locked oscillator driven in synchronization with the first phase-locked oscillator The output of f1 is supplied to the extraction reference signal generation circuit, and after selecting another extraction clock signal, the extraction clock signal is supplied to the extraction reference signal generation circuit, and the extracted clock signal is supplied to the extraction reference signal generation circuit based on the output of the extraction reference signal generation circuit. By driving one phase-locked oscillator, even if the extracted clock signal from the transmission line becomes abnormal, the phase fluctuation of the output of the extracted reference signal generation circuit can be prevented without adding a special phase control circuit, and the transmission device can operate at a low speed. Significant effect on cost reduction and performance improvement.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of an apparatus for realizing a method of generating an extracted reference clock signal according to the present invention.

FIG. 2 is a diagram showing a configuration of a device for realizing a conventional method for generating an extracted reference clock signal.

FIG. 3 is a diagram showing a configuration of an apparatus for realizing a conventional method for generating an extracted reference clock signal to which a phase control function is added.

[Explanation of symbols]

 5, 6, 7,... PLO, 16, 17, 18,..., Transmission line interface board, 16a, 17a, 18a. ..Switches, 22..Clock boards

Claims (3)

[Claims] 1. A method for generating an extracted reference clock signal for obtaining a clock signal to be distributed in a transmission device based on clock signals extracted from a plurality of transmission lines, comprising: a clock signal having a frequency f1 extracted from the plurality of transmission lines; Is selected, and the selected extracted clock signal is frequency-divided to generate an extracted reference clock signal having a frequency f2.
Inputting the extracted reference clock signal having a frequency f1 >> f2 to a first phase-locked oscillator to generate a clock signal of a desired frequency; inputting the output of the first phase-locked oscillator to an m-th phase-locked oscillator; A transmission clock signal having the same frequency f1 as the extracted reference clock signal is generated, and when the output of the extracted clock signal extracted from the transmission line is cut off, the first phase-locked oscillator is free-running and the m-th phase-locked oscillator is The transmission clock signal to be output is input to the extraction reference clock signal generation means, and the transmission clock signal is frequency-divided to generate an extraction reference clock signal having a frequency f2. A clock signal is input to the extracted reference clock signal generating means, and the first phase is output based on the output of the extracted reference clock signal generating means. A method for generating an extracted reference clock signal, characterized in that a phase fluctuation of the extracted reference clock signal is suppressed when a failure occurs in the extracted clock signal by driving a synchronous oscillator. 2. An extraction reference clock signal generation device for obtaining a clock signal to be distributed in a transmission device based on clock signals extracted from a plurality of transmission lines, wherein an extracted clock signal having a frequency f1 is extracted from the plurality of transmission lines. An extracted clock switching circuit to be input; and dividing the output of the extracted clock switching circuit to obtain a frequency f2.
An extraction reference signal generation circuit for generating a clock signal of (f1 >>f2); a first phase-locked oscillator for generating a desired signal synchronized with the output of the extraction reference signal generation circuit; An m-th phase-locked oscillator that generates a signal having the same frequency f1 as the extracted clock signal, and automatically turns off the first phase-locked oscillator when the extracted clock signal selected in the extracted clock switching circuit is cut off. Running, and driving an extraction reference signal generation circuit based on the output of the m-th phase-locked oscillator to generate a clock signal of frequency f2, and then select an extraction clock signal from another transmission line, And drives the first phase-locked oscillator based on the output of the extracted reference signal generation circuit. When the extracted clock signal from the CPU is cut off, the first phase-locked oscillator self-runs, and drives the extraction reference signal generation circuit based on the output of the m-th phase-locked oscillator. Switching the extracted clock signal by selecting a clock signal, driving the extracted reference signal generation circuit based on the extracted clock signal, and driving the first phase locked oscillator based on the output of the extracted reference signal generation circuit Wherein the phase fluctuation of the output of the first phase-locked oscillator is suppressed. 3. The extracted clock signal is 1.544 MHz.
3. The extracted reference clock signal generation device according to claim 2, wherein the output of the reference signal generation circuit is an 8 kHz signal.