JPH0435133A - Clock changeover circuit - Google Patents

Abstract

PURPOSE:To suppress the fluctuation of a phase of an output clock by providing n-sets of phase synchronization section each outputting a clock with a prescribed frequency higher than the frequency of an input lock while the phase is matched with the input clock. CONSTITUTION:A clock whose phase is in matching with an input clock and whose frequency is a constant frequency of 75MHz sufficiently higher than the frequency of 1.5MHz of the input clock is given to phase synchronization sections 150-1 - 150-n provided to an input of a selection section 380. As a result, even when one set of input clock selected and outputted by a selection section 380 is interrupted and other one set of input clock is selected, the frequency of the output clock of the phase synchronization sections 150-1 - 150-n is sufficiently higher than the frequency of the input clock (multiple of 50). Thus, the frequency fluctuation of the output clock is suppressed even during the interrupt detection time of the selection section 380 and an interrupt detection input is given, and even when the clock from the selection section 380 is selected, the phase fluctuation of the output clock is reduced.

Description

[Detailed Description of the Invention] [Summary] Regarding a clock switching circuit that has multiple clocks for synchronizing its own device and switches between the clocks, when the currently selected synchronizing clock is disconnected and a disconnection detection input is given to the clock selection circuit. A clock switching circuit that can suppress frequency fluctuations of the output clock even during the time period until the output clock is input, and can reduce fluctuations in the phase of the output clock even when the clock selection circuit switches the synchronization clock in response to a disconnection detection input. a selection unit that inputs n sets of clocks, selects and outputs one set of clocks, and selects and outputs another set of clocks when the selected input clock is disconnected; A clock switching circuit having a phase-locked loop that inputs the output clock of the selection section, adjusts its phase to the phase of the input clock, and outputs a clock of a constant frequency. The configuration includes n phase synchronization units that output a clock having a constant frequency higher than the frequency of the input clock in accordance with the phase of the input clock.

[Industrial application field]

The present invention relates to an improvement in a clock switching circuit that has a plurality of clocks for synchronizing its own device and switches between the clocks.

With the recent demand for stable synchronization in PCM data communication systems, etc., it is required to have multiple sets of clocks for synchronization. For this reason, a master clock from the station, an internal clock of the device itself, a loop timing clock timingd from the line, etc. are provided, and any one of the clocks is selected to generate a synchronized clock.

When the selected clock is turned off, the selection circuit switches to another clock. However, there is a condition that during this switching operation, sudden phase fluctuations in the output synchronized clock must not occur and line errors must not occur.

Therefore, the frequency fluctuation of the output clock can be suppressed even during the period when the currently selected synchronization clock is disconnected and the disconnection detection input is applied to the clock selection circuit (hereinafter referred to as SEL), and the disconnection detection input is applied. There is a need for a clock switching circuit that can reduce fluctuations in the phase of the output clock even when the synchronization clock is switched using the SEL.

[Conventional technology]

FIG. 4 is a block diagram showing the configuration of a conventional clock switching circuit.

FIG. 5 is a time chart explaining the operation of the conventional example.

In Fig. 4, the current and standby input clocks (their frequencies are, for example, 1.5 MI+z) ■ and ■ are input to frequency dividers 1 and 2, respectively, and the output frequencies of frequency dividers 1 and 2 are The frequencies are divided so that they are the same (for example, 1/10) and output to 5EL3. 5EL3
In response to the control signal indicated by the clock interruption detection signal (■) or (■), the input that is not disconnected (usually the current input) is selected and output to the phase-locked loop (hereinafter referred to as PLL) 5. P i, L5 outputs a clock with a constant frequency (for example, the frequency is 75 MHz) that matches the phase of the input clock.

Also, in order to match the phase of each input clock,
The output of 5EL3 (selected clock) is branched and added to the differentiating circuit 4, and differentiated by the differentiating circuit 4, and the differentiated output is used as a reset pulse to the frequency dividing circuit 1 or 2 that is not currently selected (usually the spare frequency dividing circuit 2). ) was entered.

[Problem to be solved by the invention]

However, in the above circuit configuration, when the selected synchronization clock is disconnected, if the disconnection detection time is set within the standard range (for example, several ms) as shown in Figure 5, the disconnection detection input While the PLL 5 is being input, only a constant input of "[I" or "L#" is given as a value for phase comparison, and the output clock of the PLL 5 may cause sudden phase fluctuations and cause line errors. There was a problem with gender.

Therefore, an object of the present invention is to suppress the frequency fluctuation of the output clock even during the period from when the currently selected synchronization clock is disconnected to when the disconnection detection input is applied to the SEL, and to suppress the frequency fluctuation of the output clock even during the period from when the selected synchronization clock is disconnected to when the disconnection detection input is applied to the SEL. An object of the present invention is to provide a clock switching circuit that can reduce fluctuations in the phase of an output clock even when switching the clocks.

[Means to solve the problem]

The above problem is solved by the circuit configuration shown in FIG.

That is, in FIG. 1, there is a selection section 3 which inputs n sets of clocks, selects and outputs one set of clocks, and selects and outputs another set of clocks when the selected input clock is disconnected.
80 and a phase-locked loop 500 that inputs the output clock of the selection section 380 and outputs a clock with a constant frequency by adjusting its phase to the phase of the input clock. These are n phase synchronization sections that are provided at the input of the selection section 380 and output a clock having a constant frequency higher than the frequency of the input clock by matching its phase with the phase of the input clock.

[For production]

In FIG. 1, the phase synchronization units 150-1 to 150-n provided at the input of the selection unit 380 match the phase of the input clock to the frequency of the input clock (for example, 150-n).
．． A clock with a constant frequency (for example, 75 MHz) that is sufficiently higher than 5 Ml (referred to as z) is output.

As a result, even when one set of input clocks selected and output by the selection unit 380 is cut off and switched to another set of input clocks, the frequency of the output clocks of the phase synchronization units 150-1 to 150-n is sufficiently higher (for example, 50 times) than the frequency of the input clock, it is possible to suppress fluctuations in the frequency of the output clock even during the time until the disconnection detection input is applied to the selection section 380.

In addition, even if the selection unit 380 switches the clock in response to a disconnection detection input, it is possible to reduce the variation in the phase of the output clock.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a clock switching circuit according to an embodiment of the present invention.

FIG. 3 is a time chart explaining the operation of the embodiment.

The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, the working and standby master clocks (their frequency is, for example, 1°5 MHz) given from the station are connected to bipolar/unipolar conversion circuits (hereinafter referred to as B/U) 111 and 11, respectively. -2 and converts the bipolar signals in B/Ull-1 and 11-2 into unipolar signals and outputs the unipolar signals. This output is branched and one is added to the synchronous circuits 13-1 and 13-2 for synchronization with the synchronous circuits 3-1 and 3-2, and the other is added to the disconnection detection circuits 12-1 and 12-2. The disconnection detection circuits 12-1 and 12-2 detect disconnection of the input clock.

The outputs of the disconnection detection circuits 12-1 and 12-2 are applied to the 5EL38, and when the current input master clock is disconnected in SF and L3B, the output is switched to the spare input master clock. When both the active and standby input master clocks are disconnected, the output clock of the internal clock generation circuit 21 of the own device, which will be described later, is transferred to the frequency dividing circuit 23 and the PLL.
The clock input via 24 is selected and output.

When the output of the internal clock generation circuit 21 is also cut off, a loop timing clock extracted from an opposing line, which will be described later, is input via the frequency divider circuit 32 and the PLL 33, and the clock is output.

The output of the above-mentioned synchronous circuit 13-1 (the spare circuit is the same as the current circuit, so only the current circuit will be explained) is added to the frequency divider circuit 14-1, and the frequency is divided by, for example, l/10 (currently In the case of , the frequency is 0.15MHz) PLL15
Output to -1. In P L Li 2-1, the output of the frequency dividing circuit 14-1 is applied to one input terminal of a phase comparison circuit (hereinafter referred to as PC) 16-1. PCl3-1
The other input terminal of the voltage controlled oscillator (hereinafter referred to as VCO)
In this case, the output frequency is, for example, 75 M.
Hz) The output of 18-1 is converted into a clock pulse by a slice amplifier (not shown), and then the frequency dividing circuit 1
In addition to 9-1, the output frequency-divided to 11500 by the frequency divider circuit 19-1 is added.

PCl3-1 compares the phases of the two to determine the difference, outputs a voltage proportional to the phase difference, and uses a low-pass filter (hereinafter referred to as LPF).
) Add to 17-1. The LPF171 passes only the DC component of the input voltage, and the output is the VC018-
Add to 1. Then, VC018-1 changes the output frequency in accordance with the DC voltage component.

This output is applied to the aforementioned frequency dividing circuit 19-1 and also to 5EL38.

A similar operation is performed for the spare input master clock using the spare circuit shown in FIG.

Further, the internal clock output (its frequency is, for example, 1.5 MHz) generated by the internal clock generating circuit 21 of the own device is also branched, one is applied to the frequency dividing circuit 23, and the other is applied to the disconnection detecting section 22. The output of the disconnection detection circuit 22 is applied to 5EL3B. On the other hand, the frequency dividing circuit 23 divides the frequency of the input clock by, for example, 1/10 and applies it to the PLL 24, and the same operation as described for the current master clocker input is performed. Then, the output of PLL24 is applied to 5EL38.

Also, the loop timing clock extracted from the opposing line (its frequency is, for example, 1.5 MHz) is similarly branched, one is added to the frequency dividing circuit 32, and the other is sent to the disconnection detection port i!! )Add to 31. Then, the output of the disconnection detection circuit 31 is applied to 5EL38. Further, the frequency of the input clock is divided by, for example, 1/10 in the frequency dividing circuit 32, and the output is outputted to the PLL.
Add to 33. In PLL33, the same operation as in the case of the current master clock mentioned above is performed, and the output is set to 5E.
Add to L38.

As described above, in the 5EL 70, when the current master clock is normal, a manually inputted clock is selected and output from the current master clock input via the PLL 15-1. When the current disconnection detection circuit 12-1 detects disconnection of the current master clock, it selects and outputs the spare input master clock input via the PLL 15-2.

Also, when both the active and standby input master clocks are disconnected, the internal clock generation circuit 21 in 5BL38
The clock input through the PLL 24 is selected and outputted. Moreover, when the output of the internal clock generation circuit 21 is also cut off, the loop timing clock extracted from the opposite line is inputted via the PLL 33.
5EL38 to select and output.

The output selected by the above-mentioned 5EL38 (its frequency is, for example, 75M1lz) is input to the frequency divider circuit 39, and the output is set to 1/1, for example.
The clock frequency is divided by 10 and the frequency of 7.5 MHz is P.
Output to LL50. The VC○50 also performs the same operation as the PLL Li2-1 used as the current master clock described above, and outputs a clock from the PLL50 at a frequency (75 MHz in this case) matching the phase of the input clock.

Next, the operation of the circuit when, for example, the current input master clock is disconnected will be explained.

In this case, as shown in Figure 3, compared to the frequency of the input master clock (1.5 MHz in this case), the PLL15
Since the output frequency of VCO 18-1 in -1 is extremely high (75 MHz in this case), even when the input clock is cut off and switched to the spare master clock by 5EL38, as shown in Figure 3, the current VCO18-1
Since the output of PLL 15-2 is a high-frequency clock even when switching to the spare master clock, the output of PLL 50 has a very large phase difference with the current one, as shown in Figure 3. small.

As a result, the selected synchronization clock is cut off, and the 5EL
Even during the time period until the disconnection detection input is applied to 38, the frequency fluctuation of the output clock can be suppressed.

Furthermore, even if the 5EL38 switches the synchronization clock upon receiving the disconnection detection input, the fluctuation in the phase of the output clock can be reduced.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a clock whose frequency is almost the same as before the clock disconnection and with almost no fluctuation during the disconnection detection time.

Furthermore, even if the clock switching circuit switches the clocks in response to the disconnection detection input, the fluctuation in the phase of the output clock can be reduced.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram showing the configuration of a clock switching circuit according to an embodiment of the present invention, Fig. 3 is a time chart explaining the operation of the embodiment, and Fig. 4 is a conventional example. FIG. 5 is a block diagram showing the configuration of the clock switching circuit of FIG. 5, and a time chart illustrating the operation of the conventional example. In the figure, 150-1 to 150-n indicate phase synchronization units. JX buried prisoner of the present invention

Claims (1)

[Claims] a selection unit (380) which inputs n sets of clocks, selects and outputs one set of clocks, and selects and outputs another set of clocks when the selected input clock is disconnected; In a clock switching circuit having a phase-locked loop (500) that inputs an output clock of 380), adjusts its phase to the phase of the input clock, and outputs a clock of a constant frequency, the input of the selection section (380) n phase synchronization units (150-1 to 150-n) are connected to each other and output a clock having a constant frequency higher than the frequency of the input clock by adjusting the phase thereof to the phase of the input clock. clock switching circuit.