JP2006277693A - Clock switching device and clock switching method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock switching device and clock switching method capable of automatically switching to a clock distribution system for backup without interrupting processing of a device. <P>SOLUTION: The device is provided with a first phase adjusting means 1 for detection for matching phases of a certain clock pulse T0 of a first clock distribution system CIN0 and a clock pulse T0' one cycle before, a first abnormality detecting means 2 for checking whether logical levels (HIGH/LOW) of the clock pulses T0, T0' correspond or not, and making an ALM0 high when the logical levels do not correspond, a second phase adjusting means 3 for detection for matching phases of a certain clock pulse T1 of a second clock distribution system CIN1 and a clock pulse T1' one cycle before, a switching signal generating means 6, and a switching means 7. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to clock switching, and more particularly, to a clock switching device and a clock switching method capable of switching a clock by detecting a waveform abnormality.

  Conventionally, when a failure occurs in the clock distribution system, the device is restarted after replacing the suspicious component, and therefore it has been necessary to interrupt the processing of the device when the failure is recovered.

  An example of a conventional clock switching device is described in Japanese Patent Application Laid-Open No. 9-510338. The clock switching device described in Patent Document 1 proposes a circuit that switches the phases of two input clocks in synchronization. However, since the clocks of the same oscillation source (synchronization) are assumed, the oscillation source has failed. In this case, it is necessary to interrupt the processing of the device and replace the suspected part, so it is necessary to interrupt the processing of the device and restart the device.

  Further, since this clock switching device does not have a waveform abnormality detection function, it is necessary to separately provide some means for detecting a failure of the clock distribution system and instructing switching of the input clock.

As an example of a conventional clock switching apparatus for such a problem, Patent Document 2 (United States Patent 5,903,748) discloses an asynchronous clock switching that does not interrupt a clock pulse when a failure of the apparatus is recovered. A circuit is described.
Japanese National Patent Publication No. 9-510338 United States Patent 5,903,748

  However, since the conventional clock switching device described above uses a VCO (Voltage Control Oscillator), there is a problem that jitter is larger than a clock generated by a high-precision crystal oscillator.

  An object of the present invention is to automatically switch to a backup clock distribution system without interrupting the processing of the apparatus when one of two high-precision, low-jitter clock distribution systems with different oscillation sources fails. A clock switching device and a clock switching method that can be used.

  To achieve the above object, according to the present invention, a clock switching device that switches a clock supplied to an information processing device detects a waveform abnormality of an output clock pulse among a plurality of input clock pulses. , And means for switching to another clock pulse whose phase is matched with that of the clock pulse being output.

  In a preferred aspect of the present invention, in addition to the above aspect, an abnormality detecting means for detecting a mismatch in logic level between the current clock pulse and the clock pulse one cycle before is provided for each of a plurality of clock pulses, and the phase of other clock pulses is provided. Is switched to another clock pulse whose phase is matched by the switching phase adjusting means based on the detection of the logic level mismatch by the abnormality detecting means and the phase adjusting means for switching to match the phase of the clock pulse being output. And a switching means.

  In a further preferred aspect of the present invention, in addition to the above aspect, for each of a plurality of clock pulses, a detection phase adjustment unit that matches the phase of the current clock pulse and the clock pulse of the previous cycle is provided, and from the detection phase adjustment unit, The clock pulse being output and other clock pulses are output to the switching phase adjustment means.

  In a further preferred aspect of the present invention, in addition to the above aspect, when the abnormality detection unit detects a mismatch, the switching unit includes a switching signal generation unit that generates a switching signal to another clock pulse, and the switching unit includes the switching signal generation unit. The clock pulse is switched on the basis of the switching signal from.

  According to the present invention, it is possible to realize a clock switching device that can automatically switch to a backup clock distribution system without interrupting the processing of the device.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

(Description of clock switching circuit configuration)
FIG. 1 is a block diagram showing a configuration of a clock switching circuit according to an embodiment of the present invention.

  According to FIG. 1, the clock switching circuit according to the embodiment of the present invention includes a first detection phase adjustment unit 1, a first abnormality detection unit 2, a second detection phase adjustment unit 3, and a first detection phase adjustment unit 3. 2 abnormality detecting means 4, switching phase adjusting means 5, switching signal generating means 6, and switching means 7.

  The first detection phase adjusting unit 1 has a function of comparing the phases of a clock pulse T0 in the first clock distribution system CIN0 and the clock pulse T0 'of the previous cycle and matching the phases.

  The first abnormality detection means 2 has a function of determining the logic levels (HIGH / LOW) of the clock pulses T0 and T0 'and outputting them as ALM0 information.

  The second detection phase adjusting means 3 has a function of comparing the phases of a clock pulse T1 in the second clock distribution system CIN1 and the clock pulse T1 'of the previous cycle and matching the phases.

  The second abnormality detection means 4 has a function of discriminating the logic levels (HIGH / LOW) of the clock pulses T1 and T1 'and outputting them as ALM1 information.

  The switching phase adjusting means 5 has a function of comparing the phases of the clock pulse D0 in the first clock distribution system CIN0 and the clock pulse D1 in the second clock distribution system CIN1, and matching the phases.

  The switching signal generating means 6 has a function of switching the switching signal SEL based on ALM0 information and ALM1 information.

  The switching means 7 has a function of selecting the first clock distribution system CIN0 or the second clock distribution system CIN1 based on the switching signal SEL and outputting it as COUT.

  FIG. 2 shows a first detection phase adjustment unit 1, a first abnormality detection unit 2, a second detection phase adjustment unit 3, and a second detection unit that constitute a part of the clock switching circuit in FIG. It is a block diagram which shows a detailed structure with the abnormality detection means 4.

  1 and 2, the phase comparison circuit 12 in the first detection phase adjusting means 1 compares the phase of a clock pulse T0 in the first clock distribution system CIN0 with the clock pulse T0 ′ of the previous cycle. When the phase of T0 is before, the counter 13 is instructed to count up, and when the phase of T0 is later, it instructs to count down.

  The variable delay circuit 11 increases or decreases the delay amount according to the value of the counter 13.

  As a result, the count value of the counter 13 is adjusted so that the variable delay circuit 11 has a delay amount corresponding to one cycle of the clock CIN0, and the phase of T0 'matches the phase of T0.

  The ExOR circuit 21 in the first abnormality detection means 2 outputs an exclusive OR operation result T0 ″ of the clock pulses T0 and T0 ′.

  The fixed delay circuit 24 and the gate 25 give a specific delay to the clock pulse T0 ', and output both positive logic T0 "" and negative logic / T0 "".

  The selector 22-1 and the F / F (flip-flop circuit) 23-1 take in the logic 1 (HIGH level) of T0 ″ at the rising edge of T0 ″ and output DT0.

  The selector 22-2 and the F / F 23-2 take in the logic 1 (HIGH level) of T0 "at the falling edge of T0" "and output DC0.

  The OR circuit 26 outputs the logical sum result of DT0 and DC0 as ALM0.

  As a result, when the logic levels (HIGH / LOW) of the clock pulses T0 and T0 'do not match, ALM0 becomes HIGH.

  FIG. 3 is a block diagram showing a detailed configuration of the switching phase adjusting means 5, the switching signal generating means 6, and the switching means 7 constituting a part of the clock switching circuit in FIG.

  As shown in FIG. 3, the phase comparison circuit 52 in the switching phase adjusting means 5 compares the phase of the clock pulse D0 with the first clock distribution system CIN0 with the phase of the clock pulse D1 with the second clock distribution system CIN1. When the phase of D0 is earlier, the counter 53-0 is counted up, and when the phase of D0 is later, the counter 53-0 is counted. The DOWN and the counter 53-1 are instructed to count up.

  The variable delay circuit 51-0 increases or decreases the delay amount according to the value of the counter 53-0, and the variable delay circuit 51-1 increases or decreases the delay amount according to the value of the counter 53-1.

  At this time, since CIN0 and CIN1 have different oscillation sources, the counters 53-0 and 53-1 always count up or down to match the phases of D0 and D1, and the variable delay circuits 51-0 and 51-1 Is attached to the MAX side or the MIN side, the counter values of the counters 13 and 33 in the detection phase adjusting means 1 and 2 are subtracted or added.

  As a result, the state in which the phase of the clock pulse D0 in the first clock distribution system CIN0 and the phase of the clock pulse D1 in the second clock distribution system CIN1 match is kept.

  The switching signal generator 6 switches SEL from HIGH when ALM0 changes from LOW to HIGH when the switching signal SEL is LOW, and remains HIGH when ALM0 changes from LOW to HIGH when SEL is HIGH.

  Further, when ALM1 changes from LOW to HIGH when the switching signal SEL is HIGH, SEL is switched to LOW, and when ALM1 changes from LOW to HIGH when SEL is LOW, it remains LOW.

The switching means 7 selects the first clock distribution system CIN0 when SEL is LOW, and selects the second clock distribution system CIN1 when SEL is HIGH, and outputs it as COUT.
(Description of operation of clock switching circuit)
Next, the operation of each component of the clock switching device in FIGS. 1 to 3 will be described using the time charts shown in FIGS.

  In FIG. 1, normally, clocks CIN0 and CIN1 having substantially the same frequency generated by different oscillation sources are supplied, and the switching means 7 selects one of the clocks and outputs it as COUT. ing.

  First, as an example, a description will be given of an operation of switching to CIN1 when an abnormality occurs in which the upper pulse of the CIN0 clock pulse is missed while the switching unit 7 is selecting CIN0.

  In FIG. 2, the phase of the first clock pulse T0 and the clock pulse T0 ′ of the previous cycle is compared. If the phase of T0 is earlier, the counter 13 is instructed to count up, and the phase of T0 is later. In the case of, the count down is instructed.

  The variable delay circuit 11 increases or decreases the delay amount according to the value of the counter 13.

  As a result, the count value of the counter 13 is adjusted so that the variable delay circuit 11 has a delay amount corresponding to one cycle of the clock CIN0, and the phase of T0 ′ matches the phase of T0 (4-1, FIG. 4). 4-2).

  The ExOR circuit 21 in the first abnormality detection means 2 outputs an exclusive OR operation result T0 ″ of T0 and T0 ′. For example, if an abnormality occurs in which one upper pulse of the CIN0 clock pulse is missing at the time point F in FIG. 4, a waveform such as 4-3 in FIG. 4 is output.

  The fixed delay circuit 24 and the gate 25 give a specific delay to the phase T0 ′, and output both the positive logic T0 ′ ″ and the negative logic / T0 ′ ″ (4-4 and 4-6 in FIG. 4). .

  The selector 22-1 and the F / F 23-1 take in and hold the logic 1 (HIGH level) of T0 ″ at the rising edge of T0 ′ ″ and output DT0, and output DT0 at the edge of A of T0 ′ ″. The HIGH level is set (4-5 in FIG. 4).

  At this time, the selector 22-2 and the F / F 23-2 capture the value of T0 ″ at the falling edge of T0 ′ ″ (rising edge of / T0 ′ ″), but 4-3 and 4 in FIG. As shown in −6, since T0 ″ is logic 0 (LOW level) at the falling edge of T0 ′ ″ (rising edge of / T0 ′ ″), DC0 remains LOW (FIG. 4). 4-7).

  Since the OR circuit 26 outputs the logical sum of DT0 and DC0 as ALM0, ALM0 becomes HIGH after the point A in FIG. 4 (4-8 in FIG. 4).

  In FIG. 3, the phase comparison circuit 52 in the switching phase adjusting means 5 compares the phase of the clock pulse D0 with the first clock distribution system CIN0 with the phase of the clock pulse D1 with the second clock distribution system CIN1, When the phase of D0 is before, the counter 53-0 is counted up and the counter 53-1 is instructed to count down. When the phase of D0 is later, the counter 53-0 is counted down, Instruct 53-1 to count up.

  The variable delay circuit 51-0 increases or decreases the delay amount according to the value of the counter 53-0, and the variable delay circuit 51-1 increases or decreases the delay amount according to the value of the counter 53-1.

  At this time, since CIN0 and CIN1 have different oscillation sources, counters 53-0 and 53-1 always count up or down to match the phase of D0 and D1, and variable delay circuits 51-0 and 51-1 Before sticking to the MAX side or the MIN side, the counter values of the counters 13 and 33 in the detection phase adjusting means 1 and 2 are subtracted or added.

  This keeps the state in which the phase of the clock pulse D0 with the first clock distribution system CIN0 and the phase of the clock pulse D1 with the second clock distribution system CIN1 match (5-4 and 5-4 in FIG. 5). .

  Since the switching signal SEL is LOW, the switching signal generating means 6 generates the signals AP0 and AP ″ differentiated at the falling edge of the clock pulse D1 when ALM0 changes from LOW to HIGH at the time A, and F / Invert the value of F61 (SEL) from LOW to HIGH (5-5, 5-6, 5-7 in Fig. 5).

  The switching means 7 switches the output clock COUT from the first clock distribution system CIN0 to the second clock distribution system CIN1 by inverting the value (SEL) of F / F61 from LOW to HIGH at time S (FIG. 5). 5-8).

  At this time, since the phase of the clock pulse D0 with CIN0 and the phase of the clock pulse D1 with CIN1 are matched at the input part of the switching means 7, the output clock COUT is apparently continuous, without interrupting the processing of the device. It is possible to automatically switch to a backup clock distribution system.

  As an example, an operation for switching to CIN1 when an abnormality occurs in which the lower pulse of CIN0's clock pulse is missed while the switching means 7 is selecting CIN0 will be described.

  In FIG. 2, the phase comparison circuit 12 in the first detection phase adjustment means 1 compares the phase of a clock pulse T0 in the first clock distribution system CIN0 with the clock pulse T0 ′ of the previous period T0. If the phase is earlier, the counter 13 is instructed to count up, and if the phase of T0 is later, the counter 13 is instructed to count down.

  The variable delay circuit 11 increases or decreases the delay amount according to the value of the counter 13.

  As a result, the count value of the counter 13 is adjusted so that the variable delay circuit 11 has a delay amount corresponding to one cycle of the clock CIN0, and the phase of T0 ′ matches the phase of T0 (6-1, FIG. 6). 6-2).

  The ExOR circuit 21 in the first abnormality detection means 2 outputs the exclusive OR operation result T0 ″ of T0 and T0 ′. For example, the lower pulse of the CIN0 clock pulse is generated at the time point F in FIG. If an abnormality that passes one shot occurs, a waveform like 6-3 in FIG. 6 is output.

  The fixed delay circuit 24 and the gate 25 give a specific delay to the phase T0 ′ and output both positive logic T0 ′ ″ and negative logic / T0 ″ ′ (6-4 and 6-6 in FIG. 6). .

  Selector 22-2 and F / F23-2 take in and hold logic 1 (HIGH level) of T0 ″ at the falling edge of T0 ′ ″, output DC0, and fall A of T0 ′ ″ DC0 is set to HIGH level at the rising edge of / T0 ″ ′ (6-7 in FIG. 6).

  At this time, the selectors 22-1 and F / F 23-1 capture the value of T 0 ″ at the rising edge of T 0 ″ ″, but as shown by 6-3 and 6-4 in FIG. At the rising edge of ', T0' 'is logic 0 (LOW level), so DT0 remains LOW (6-5 in Fig. 6).

  Since the OR circuit 26 outputs the logical sum of DT0 and DC0 as ALM0, ALM0 becomes HIGH after the point A in FIG. 6 (6-8 in FIG. 6).

  The operations of the switching phase adjusting means 5, the switching signal generating means 6 and the switching means 7 in FIG. 3 are the same as those in the case where the upper pulse of the CIN0 clock pulse becomes abnormal. At the time S, the output clock COUT is switched from the first clock distribution system CIN0 to the second clock distribution system CIN1 (7-8 in FIG. 7).

  The operation of switching to CIN1 when the switching means 7 selects the first clock distribution system CIN0 and an abnormality occurs in the clock pulse of the first clock distribution system CIN0 has been described above. In the third embodiment, when an abnormality occurs in the clock pulse of the second clock distribution system CIN1 in a state where the switching means 7 selects the second clock distribution system CIN1, CIN0 is operated by the same operation. It is possible to switch to.

  When an abnormality occurs in the clock pulse of CIN1 while the switching means 7 is selecting CIN0, the second abnormality detecting means 4 sets ALM1 to HIGH, but the FIN in the switching signal generating means 6 Since the value (SEL) of / F61 is LOW, AP ″ remains unchanged and the value (SEL) of F / F61 does not invert.

  Similarly, when an abnormality occurs in the clock pulse of CIN0 with the switching means 7 selecting CIN1, the first abnormality detection means 2 sets ALM0 to HIGH, but the switching signal generation means 6 Since the F / F61 value (SEL) is high, AP ″ remains low and the F / F61 value (SEL) is not inverted.

  As described above, the present invention has the following effects.

  The first effect is that the phases of the first clock distribution system and the second clock distribution system of the two clock distribution systems having different oscillation sources are matched at the input unit of the switching means. It is possible to automatically switch to a backup clock distribution system without interruption.

  The second effect is that the phase is adjusted by the delay circuit without using the VCO (voltage control oscillator), and therefore the jitter can be reduced by using a high-precision crystal oscillator as the clock oscillation source. is there.

  Although the present invention has been described above with a plurality of preferred embodiments, the present invention is not necessarily limited to the above-described embodiments, and various modifications may be made within the scope of the technical idea. Can do.

It is a block diagram which shows the structure of the clock switching apparatus by embodiment of this invention. It is a block diagram which shows the structure of the component of the clock switching apparatus by embodiment of this invention. It is a block diagram which shows the structure of the component of the clock switching apparatus by embodiment of this invention. It is a time chart which shows operation | movement of the component of the clock switching apparatus by embodiment of this invention. It is a time chart which shows operation | movement of the component of the clock switching apparatus by embodiment of this invention. It is a time chart which shows operation | movement of the component of the clock switching apparatus by embodiment of this invention. It is a time chart which shows operation | movement of the component of the clock switching apparatus by embodiment of this invention.

Explanation of symbols

1, 3: Detection phase adjustment means 11, 31: Variable delay circuit 12, 32: Phase comparison circuit 13, 33: Counter 2, 4: Abnormality detection means 21, 41: EX. OR circuit 22-1, 22-2, 42-1, 42-2: selector 23-1, 23-2, 43-1, 43-2: F / F
24, 44: fixed delay circuit 25, 45: gate 26, 46: OR circuit 5: switching phase adjustment means 51-0, 51-1: variable delay circuit 52: phase comparison circuit 53-0, 53-1: counter 6: Switching signal generating means 61: F / F
7: Switching means 71: Selector

Claims (8)

A clock switching device that switches a clock supplied to an information processing device,
When a waveform abnormality of the output clock pulse is detected among a plurality of input clock pulses, a means for switching to another clock pulse whose phase is matched with the clock pulse being output is provided. A clock switching device. For each of the plurality of clock pulses, an abnormality detecting means for detecting a mismatch in logic level between a current clock pulse and a clock pulse one cycle before,
Switching phase adjusting means for adjusting the phase of the other clock pulse to the phase of the clock pulse being output;
2. A switching means for switching to and outputting the other clock pulse whose phase is matched by the switching phase adjusting means based on detection of a logic level mismatch by the abnormality detecting means. The clock switching device described. For each of the plurality of clock pulses, a detection phase adjusting means for adjusting the phase of the current clock pulse and the clock pulse of the previous cycle is provided.
3. The clock switching device according to claim 2, wherein a clock pulse being output and another clock pulse are output from the detection phase adjusting means to the switching phase adjusting means. A switching signal generating means for generating a switching signal to another clock pulse when the abnormality detecting means detects a mismatch;
4. The clock switching device according to claim 2, wherein the switching unit switches clock pulses based on a switching signal from the switching signal generation unit. A clock switching method for switching a clock supplied to an information processing device,
A clock characterized in that, when a waveform abnormality of the output clock pulse is detected among a plurality of input clock pulses, the output is switched to another clock pulse whose phase is matched to the clock pulse being output. Switching method. Detecting a logic level discrepancy between the current clock pulse and the previous clock pulse for each of the plurality of clock pulses;
Matching the phase of the other clock pulse to the phase of the clock pulse in the output;
6. The clock switching method according to claim 5, further comprising the step of switching to the other clock pulse whose phase is matched by the switching phase adjusting means based on the detection of the logic level mismatch.   7. The clock switching method according to claim 6, further comprising the step of matching the phase of the current clock pulse and the previous clock pulse for each of the plurality of clock pulses. Generating a switching signal to another clock pulse when detecting a mismatch in the logic level;
The clock switching method according to claim 6 or 7, wherein clock pulses are switched based on the switching signal.

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