JP4940726B2 - Clock delay correction circuit - Google Patents

Description

  The present invention relates to a clock delay correction circuit, and more particularly to a clock delay correction circuit suitable for correcting a clock phase of a clock distribution circuit in an LSI.

  In an LSI, a clock generated by a PLL circuit is distributed and supplied to each circuit portion by a clock distribution circuit. In the clock distribution circuit, variation in clock delay occurs on the clock distribution path mainly due to the difference in the length of the clock wiring and the difference in the driving characteristics of the circuit elements. Conventionally, the delay variation correction on the clock distribution path is corrected by supplying a reference clock as a reference for delay correction separately from the distribution clock or when the distribution clock itself is used as a reference clock. Thus, the distribution clock is regenerated using the voltage controlled oscillation circuit (VCO). However, when the distribution clock is regenerated by the VCO, there is a problem that the amount of jitter is larger than that of a clock generated by a high-precision crystal oscillator or the like.

  Patent Document 1 describes a phase-locked loop that corrects the phase of a distributed clock with a reference clock. This is shown in FIG. The phase lock loop is provided for the purpose of matching the phase of the first clock signal (distributed clock) CLK1 having the frequency f1 with the phase of the second clock signal (reference clock) CLK2 having the frequency f2. The local phase comparator 51 compares the phase of the clock CLK2 with the phase of the corrected output clock CLK1C, and generates a delay control signal based on the comparison result. The selector 52 that receives the output of the local phase comparator 51 generates a plurality of delay signals in response to a series of delay control signals.

The variable delay line circuit 53 receiving the output of the selector 52 receives the clock CLK1, delays CLK1 by an amount of time determined by the series of delay signals, and generates an output clock CLK1C. The reset phase comparator 54 compares the phase of the output CLK1C with the reference phase of the reference clock CLK2, and generates a reset signal when these phases match. In response to the reset signal from the reset phase comparator 54, the selector 52 generates a delay signal for adjusting the delay time amount of CLK1 to a predetermined amount.
Japanese Patent Publication No. 7-79236 (FIG. 1)

  The clock delay correction circuit described in Patent Document 1 has a complicated circuit configuration. For this reason, a clock delay correction circuit with a simplified circuit configuration is desired.

  The clock delay correction circuit of the above-mentioned patent document has two phase comparison circuits 51 and 54, and a signal delayed by a variable delay element is input to one input of each phase comparison circuit. In a signal propagation circuit including both variable delay elements, if the signal has a propagation time in a circuit portion other than the variable delay element, the propagation time appears in the phase error of the output clock that is finally output. In this clock delay correction circuit, three fixed time delay elements (fixed delay elements) 42, 43, and 46 are used to eliminate such a phase error. When setting the delay times of these fixed delay elements 42, 43, and 46, it is necessary to perform delay verification. For this reason, high-level delay verification is essential in design.

  Further, even if the delay times of the fixed delay elements 42, 43, and 46 can be matched in the design, each clock in the circuit has a different circuit configuration of the propagation path. The influence of delay variations caused by variations in ambient temperature, power supply voltage, etc. is large. For this reason, there is also a problem that it is difficult to obtain good phase accuracy when the shift register is reset.

  In view of the above, an object of the present invention is to improve a conventional clock delay circuit and provide a clock delay correction circuit having a simplified configuration.

  Furthermore, the present invention can be easily designed by suppressing the phase error caused by the signal propagation time other than the variable delay element and removing the fixed delay element necessary for adjusting the phase error, and can be used in an LSI. Another object of the present invention is to provide a clock delay circuit in which the phase accuracy of the output clock can be obtained by reducing delay variations caused by variations in the manufacturing process, LSI ambient temperature, power supply voltage, etc. .

In order to achieve the above object, a clock delay correction circuit according to a first aspect of the present invention includes an input clock signal , a frequency lower than the frequency of the input clock signal , and 1/2 of the frequency of the input clock signal. A clock delay correction circuit that receives a reference clock signal having a higher frequency and synchronizes the phase of the output clock signal generated from the input clock signal with the phase of the reference clock signal;
Period data generating means for detecting a period of the input clock signal and generating period data indicating the period;
A first variable delay circuit that has a variable delay time and generates an output clock signal delayed from the input clock signal by at least the variable delay time, and compares the phase of the output clock signal with the phase of the reference clock signal When the comparison result that the phase of the output clock signal is advanced from the phase of the reference clock signal is obtained by the first phase comparison circuit and the first phase comparison circuit, the count is increased, and the count value is the period. A first counter that resets the count value when the value corresponds to the period indicated by the data, and the variable delay time of the first variable delay circuit is proportional to the count value of the first counter Phase correction means controlled at the time to
It is characterized by providing.

The clock delay compensation circuit according to the second aspect of the present invention, the input clock signal, lower than the frequency of the input clock signal, and a reference with a frequency higher than half the frequency of the input clock signal A clock delay correction circuit that receives a clock signal and synchronizes the phase of the output clock signal generated from the input clock signal with the phase of the reference clock signal;
Period data generating means for detecting a period of the input clock signal and generating period data indicating the period;
A first variable delay circuit having a variable delay time and generating a first clock signal delayed from the input clock signal by at least the variable delay time; and having a variable delay time and at least the variable delay from the input clock signal A second variable delay circuit that generates a second clock signal delayed by time, a selection circuit that selects the first or second clock signal based on a selection signal, and outputs the first clock signal as an output clock signal; A first phase comparison circuit that compares the phase of the output clock signal with the phase of the reference clock signal, and the phase of the output clock signal is advanced from the phase of the reference clock signal by the first phase comparison circuit When the comparison result is obtained by counting UP, when the count value matches the value corresponding to the period indicated by the period data, the count value Lise And a switching signal generating means for switching the selection signal in response to reset of the first counter, and the variable delay time of the first variable delay circuit is the first counter And phase correction means controlled at a time proportional to the count value of the counter.

  In the clock delay correction circuit according to the present invention, the circuit configuration can be simplified by including the cycle data generating means for detecting the cycle of the input clock and determining the reset of the counter based on the cycle data.

  In a preferred aspect of the clock delay correction circuit according to the first aspect of the present invention, the period data generation means has a variable delay time, and generates a first clock signal by delaying the input clock signal. A variable delay circuit, a second phase comparison circuit that compares the phase of the input clock signal with the phase of the first clock signal, and count UP or count DOWN based on the comparison result of the second phase comparison circuit And a second counter that outputs a count value as the periodic data, and the variable delay time of the second variable delay circuit is controlled according to the count value of the second counter.

  When the above configuration is adopted, since the periodic data generation means and other circuits have the same circuit configuration, it is easy to match the propagation delay time between the two circuits, and propagation without using a fixed delay circuit is possible. Matching delay time is easy. In this case, it is also preferable to configure the first counter as an UP / DOWN counter. When this configuration is employed, the first variable delay circuit may directly delay the input clock signal, or further delay the input clock signal delayed by the second variable delay circuit. May be.

  In a preferred aspect of the clock delay correction circuit according to the second aspect of the present invention, the phase correction means has a variable delay time of the first or second variable delay circuit that generates a clock signal not selected by the selection circuit. Is further reset to 0 regardless of the count value.

  In the above preferred embodiment, the output of the variable delay circuit not selected by the switching means is held at the delay amount 0, and the delay adjustment is started after being selected by the switching means. For this reason, when the counter resets the count value, a beard-like waveform is not output from the selected variable delay circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a clock delay correction circuit according to the first embodiment of the present invention. The clock delay correction circuit 10 includes period data generation means 11 and phase correction means 12. The period data generation unit 11 includes a variable delay circuit 111, a phase comparison circuit 112, and a counter 113. The phase correction unit 12 includes a variable delay circuit 121, a phase comparison circuit 122, and a counter 123. A large number of clock delay correction circuits 10 of this configuration are arranged, for example, along a clock distribution circuit in an LSI, and each clock delay correction circuit generates an output clock from a clock distributed in the distribution circuit portion, Match the phase of the output clock with the phase of the reference clock.

  The reference clock CREF1 is a reference clock serving as a reference for delay correction that is generated by a high-precision crystal oscillator or the like and then supplied to each clock delay correction circuit 10 in the LSI. The oscillation source 101 includes a high-precision crystal oscillator that generates a distribution clock CLK1 having a frequency that is the same as or slightly higher than that of the reference clock CREF1, and a distribution circuit that distributes the output thereof.

  The period data generation unit 11 generates delay data for one period of the distribution clock CLK1 generated by the oscillation source 101. The phase correction unit 12 matches the phase of the distribution clock CLK1 generated by the oscillation source 101 with the phase of the reference clock CREF1, and outputs it as COUT1. A plurality of clock delay correction circuits 10 are provided in the LSI, and the phase of the distribution clock generated by a high-precision crystal oscillator or the like is matched with the phase of the reference clock. As a result, the LSI accurately corrects delay variations occurring on the clock distribution path while minimizing an increase in hardware and jitter added to the clock distribution circuit.

  Although the oscillation source 101 of the distribution clock CLK1 is composed of a high-accuracy crystal oscillator or the like, it is an oscillation source different from the reference clock CREF1, so that the distribution clock and the reference clock have substantially the same frequency. This is impossible, and there is always a slight frequency difference between the two. Therefore, an oscillation source that oscillates at a slightly higher frequency than the frequency of the reference clock CREF1 is selected as the oscillation source 101.

  The phase comparison circuit 112 in the period data generation means 11 is delayed by the variable delay circuit 111, which is the phase of a certain clock pulse C1 in the distribution clock supplied from the oscillation source 101 and the clock pulse one period before that. The phase of the clock pulse C1 ′ is compared. When the phase of the delayed previous clock pulse C1 ′ is ahead of the phase of the subsequent clock pulse C1, the phase comparison circuit 112 instructs the counter 113 to count up, and the delayed previous clock pulse C1 ′. When the phase of the clock pulse C1 ′ is delayed from the phase of the subsequent clock pulse C1, the count DOWN is indicated. The variable delay circuit 111 increases or decreases the delay amount according to the count value T1 of the counter 113. That is, the delay time is increased when the count value T1 is increased, and the delay time is decreased when the count value is decreased.

  As a result, the count value T1 of the counter 113 is adjusted by the variable delay circuit 111 to a value that is exactly the amount of delay for one period of the distributed clock, and the phase of the delayed previous clock pulse C1 ′ is changed to the subsequent clock pulse. It coincides with the phase of C1.

  The phase comparison circuit 122 in the phase correction means 12 is a certain clock of the output clock COUT1 in which the phase of a certain clock pulse CR1 in the reference clock CREF1 and the distributed clock supplied from the oscillation source 101 have passed through the variable delay circuit 121. The phase of the pulse CR1 ′ is compared. When the phase of the clock pulse CR1 ′ is ahead of the phase of the clock pulse CR1, the phase comparison circuit 122 instructs the counter 123 to count up, and the phase of the clock pulse CR1 ′ is higher than that of the clock pulse CR1. If it is delayed, the counter 123 is instructed to count down. The variable delay circuit 121 increases or decreases the delay amount according to the count value P <b> 1 of the counter 123. That is, the delay time is increased when the count value P1 is increased, and the delay time is decreased when the count value is decreased.

  Since the distribution clock has a slightly higher frequency than the reference clock CREF1, the counter 123 always counts up to match the phase of the clock CR1 'with the phase of the clock CR1. When the count value P1 of the counter 123 matches the count value T1 of the counter 113 in the cycle data generation means 11, the count value P1 is reset to 0, and the phase of the distribution clock CR1 ′ is adjusted to the phase just one cycle before. To do. As a result, the state in which the phase of a certain clock pulse CR1 'of the output clock COUT1 and the phase of a certain clock pulse CR1 of the reference clock CREF1 coincide with each other is kept.

  The above situation is shown in the timing chart of FIG. The phase of the clock pulse C1 is delayed by a delay time corresponding to the count value T1 to become the phase of the clock pulse C1 '. The predetermined count value T1 is maintained in a state where the phase of the delayed previous clock pulse C1 'and the phase of the subsequent clock pulse C1 match. For this reason, the delay time corresponding to the count value T1 coincides with one period of the distribution clock.

  The clock pulse CR1 'is a clock pulse delayed from the clock pulse C1 by a delay time corresponding to the count value P1. Since the distribution clock has a slightly higher frequency than the reference clock CREF1, the counter 123 always counts up to match the phase of the delayed clock pulse CR1 ′ with the phase of the reference clock pulse CR1, and the count value P1 is elapsed. It grows with. For this reason, the delay amount of the clock pulse CR1 'increases with time. When the count value P1 coincides with the count value T1 of the counter 113 in the period data generation means 11, the count value P1 is reset to 0, and the phase of the distribution clock CR1 'is matched with the phase of the reference clock. As a result, the state in which the phase of a certain clock pulse CR1 'of the output clock COUT1 and the phase of a certain clock pulse CR1 of the reference clock CREF1 coincide with each other is kept.

  In the above embodiment, the phase of the distribution clock C1 generated by a high-accuracy crystal oscillator or the like is matched with the phase of the reference clock CREF1, so that an increase in jitter is minimized and distribution that occurs on the clock distribution path is performed. The delay variation of the clock C1 is corrected. The clock delay correction circuit 10 of the present embodiment has only two variable delay circuits 111 and 121, and the circuit configuration of the period data generation means 11 and the phase correction means 12 is substantially the same. Becomes easier. In addition, since the circuit configurations of both means 11 and 12 are the same, delay variation due to variations in the LSI manufacturing process, LSI operation, ambient temperature, power supply voltage, and the like can be suppressed, and the clock when the counter is reset Phase accuracy is improved.

  FIG. 2 shows a clock delay correction circuit 20 according to the second embodiment of the present invention, and FIG. 6 is a time chart showing its operation. The clock delay correction circuit 20 of the embodiment of FIG. 2 is the same as that of FIG. 1 except that the input of the variable delay circuit 221 of the phase correction unit 22 is connected to the output of the variable delay circuit 211 of the period data generation unit 21. This is the same as the embodiment.

  The reference clock CREF2 is a reference clock for delay correction that is generated by a high-precision crystal oscillator or the like and then supplied to each clock delay correction circuit in the LSI. The oscillation source 201 is an oscillation source that generates a distribution clock CLK2 having a frequency that is the same as or slightly higher than that of the reference clock CREF2, and includes a high-precision crystal oscillator or the like.

  The period data generation means 21 generates delay data for one period of the distribution clock CLK2 generated by the oscillation source 201. The phase correction unit 22 matches the phase of the distribution clock CLK2 generated by the oscillation source 201 with the phase of the reference clock CREF2, and outputs it as COUT2. A plurality of clock delay correction circuits 20 are arranged in the LSI, and the phase of the distribution clock CLK2 generated by a high-precision crystal oscillator or the like is matched with the phase of the reference clock CREF2. As a result, the LSI corrects delay variations occurring on the clock distribution path while minimizing an increase in hardware and jitter added to the clock distribution circuit.

  The oscillation source 201 of the distribution clock CLK2 is composed of a high-accuracy crystal oscillator or the like, but is an oscillation source different from the reference clock CREF2, so that the distribution clock CLK2 and the reference clock CREF2 have completely the same frequency. Is practically impossible, and there is always a slight frequency difference between the two. Therefore, an oscillation source that oscillates at a slightly higher frequency than the reference clock CREF2 is selected as the oscillation source 201.

  With reference to FIG. 6, the operation of the delay correction circuit 20 of the present embodiment will be described. The variable delay circuit 211 increases or decreases the delay amount according to the value of the counter 213. As a result, the count value T2 of the counter 213 is adjusted to a value by which the variable delay circuit 211 is exactly the amount of delay for one cycle of the distribution clock CLK2, and the phase of C2 'matches the phase of C2. The phase comparison circuit 222 in the phase correction means 22 includes the phase of a certain clock pulse CR2 of the reference clock CREF2 and the output clock from which the distributed clock CLK2 supplied from the oscillation source 201 has passed through the variable delay circuit 211 and the variable delay circuit 221. The phase of a certain clock pulse CR2 ′ of COUT2 is compared. In the comparison, when the phase of the clock pulse CR2 ′ is ahead of the phase of the clock pulse CR2, the counter 223 is instructed to count up, and the phase of the clock pulse CR2 ′ is the phase of the clock pulse CR2. If it is later than this, the counter 223 is instructed to count down.

  The variable delay circuit 221 increases or decreases the delay amount according to the count value P2 of the counter 223. At this time, since the distribution clock CLK2 has a slightly higher frequency than the reference clock CREF2, the counter 223 always counts up to match the phase of the clock pulse CR2 'with the phase of the clock pulse CR2. When the count value P2 matches the count value T2 of the counter 213 in the period data generation means 21, the count value P2 is reset to 0, and the phase of the distribution clock CR2 'is matched with the phase of the reference clock CREF2. As a result, a state in which the phase of a certain clock pulse CR2 'of the output clock COUT2 and the phase of a certain clock pulse CR2 of the reference clock CREF2 coincide with each other is kept.

  In the first embodiment, compared with the case where the output of the oscillation source 101 needs to be supplied to both the period data generation unit 11 and the phase correction unit 12, the output of the oscillation source 201 is used in the second embodiment. Need only be supplied to the periodic data generating means 21. This makes the physical configuration somewhat simpler.

  In both the first and second embodiments, if the variable delay circuits 211 and 221 are configured as one delay circuit and divided and used at the time of use, it is more preferable than configuring them as separate delay circuits. Variations in delay amount can be suppressed. In the second embodiment, since the output of the oscillation source 201 is supplied only to the periodic data generation means 21, such a circuit configuration can be adopted more easily than in the first embodiment.

  In the second embodiment, since the output clock COUT2 passes through both the variable delay circuits 211 and 221 between the oscillation source 201 and the output terminal, as compared with the first embodiment, The number of stages of gates passing through increases. For this reason, there is a drawback that jitter tends to increase although it depends on the amount of noise generated.

  FIG. 3 shows the configuration of the clock delay correction circuit 30 according to the third embodiment of the present invention, and FIG. 4 shows the details of the phase correction means 32 shown in FIG. FIG. 7 is a time chart showing the operation of the clock delay correction circuit 30.

  Referring to FIG. 3, the clock delay correction circuit 30 includes a period data generation unit 31 and a phase correction unit 32. The phase correction unit 32 includes a first phase adjustment unit 320, a second phase adjustment unit 321, a phase difference detection unit 322, a switching signal generation unit 323, a switching unit 324, and fixed delay units 325 and 326. Referring to FIG. 4, the first phase adjusting unit 320 includes an inverter (NOT circuit) 331, an AND circuit 332, and a variable delay circuit 333. The second phase adjusting unit 321 includes an AND circuit 341 and a variable delay circuit 342.

  3 and 4, the reference clock CREF3 of the LSI is generated by a high-accuracy crystal oscillator or the like as in the first and second embodiments, and then supplied to each delay correction circuit in the LSI. This is a reference clock for correction. The distribution clock oscillation source 301 is selected to oscillate at a slightly higher frequency than the reference clock CREF3. The cycle data generation unit 31 has the same configuration as the cycle data generation unit 11 of FIG. 1, and outputs a count value T3 that is a delay amount for one cycle of the distribution clock CLK3.

  The phase comparison circuit 351 in the phase difference detection unit 322 is configured such that the phase of a certain clock pulse CR3 of the reference clock CREF3 and the distribution clock supplied from the oscillation source 301 are the first phase adjustment unit 320 or the second phase adjustment unit. The phase of a certain clock pulse CR3 ′ of the output clock COUT3 that has passed through 321 and the switching means 324 is compared. In this comparison, if the phase of CR3 'is ahead of the phase of CR3, the counter 352 is instructed to count up. Here, since the distribution clock has a slightly higher frequency than the reference clock CREF3, the counter 352 always counts up to match the phase of the clock pulse CR3 ′ with the phase of the clock pulse CR3 of the reference clock CREF3. To do.

  The switching signal generation unit 323 is configured to select the value “0/0” of the selection signal SEL every time the count value P3 of the counter 352 matches the count value T3 that is a delay amount for one period of the distribution clock output from the period data generation unit 31. Switch 1 ”. The switching unit 324 selects the clock C30 from the second variable delay circuit 342 as the output clock COUT3 when the selection signal SEL is “1”, and the first variable delay circuit when the SEL is “0”. The clock C30 from 333 is selected as the output clock COUT3.

  When the selection signal SEL of the switching signal generation unit 323 is “0”, the AND circuit 332 in the first phase adjustment unit 320 sends the count value P3 of the counter 352 to the variable delay circuit 333 as it is, and the SEL is “1”. When "", the output of the count value P3 to the variable delay circuit 333 is blocked. The AND circuit 341 of the second phase adjustment unit 321 sends the count value P3 of the counter 352 to the variable delay circuit 333 when the selection signal SEL of the switching signal generation unit 323 is “1”, and the SEL is “0”. When "", the output of the count value P3 to the variable delay circuit 342 is blocked.

  The operation of the clock delay correction circuit 30 will be described with reference to FIG. When the selection signal SEL, which is the output of the switching signal generation unit 323, is “0”, the switching unit 324 selects the clock C30 from the first variable delay circuit 333. The count value P3 of the counter 352 input to the variable delay circuit 342 is suppressed by the AND circuit 341, and the state of the delay amount 0 of the clock C31 from the second variable delay circuit 342 is held. When the counter 352 is reset from this state, the signal is input to the switching signal generation unit 323, the selection signal is switched from “0” to “1”, and the switching unit 324 replaces the clock C30 with the second signal. The clock C31 from the variable delay circuit 342 is selected as the output clock COUT3. Next, the count value P3 input to the AND circuit 332 through the fixed delay means 325 changes to zero. For this reason, the delay amount of the clock C30 becomes zero. Thereafter, the selection signal SEL input to the AND circuit 341 via the fixed delay means 326 is switched from “0” to “1”. Therefore, the count value P3 of the counter 352 is input to the second variable delay circuit 342, and the delay amount of the second variable delay circuit 342 is controlled by the count value P3.

  After that, as long as the selection signal from the switching signal generation means 323 continues “1”, the first variable delay circuit 333 is in a state where the delay amount is 0 because the input count value P3 is suppressed by the AND circuit 332. To maintain. Next, when the counter 352 is reset, the selection signal SEL changes to “0”, and the switching unit 324 selects the clock C30 from the first variable delay circuit 333 as the output clock COUT3 instead of the clock C31. Next, the count value P3 input to the AND circuit 341 via the fixed delay means 325 changes to 0, and the delay amount of the clock C31 from the second variable delay circuit 342 is set to 0. Thereafter, the selection signal / SEL input to the AND circuit 332 via the fixed delay means 326 is switched from “0” to “1”. Therefore, the count value P3 of the counter 352 is input to the first variable delay circuit 333, and the delay amount of the first variable delay circuit 333 is controlled by the count value P3.

  As described above, when the selection signal SEL from the switching signal generation unit 323 is “0”, the switching unit 324 selects the clock C30 (solid line portion) that has passed through the first phase adjustment unit 320 and outputs it as COUT3. To do. When the selection signal SEL from the switching signal generation unit 323 is “1”, the clock C31 (solid line portion) that has passed through the second phase adjustment unit 321 is selected and output as COUT3. As a result, a state in which the phase of a certain clock pulse CR3 'of the output clock COUT3 and the phase of a certain clock pulse CR3 of the reference clock CREF3 coincide with each other is kept.

  In the third embodiment, the output of the variable delay circuit 333 or 342 not selected by the switching unit 324 is held at the delay amount 0, and delay adjustment is started simultaneously with the selection by the switching unit 324. In the previous embodiment, when the counter 123 or 223 is reset, the clock waveform passing through the variable delay circuit 121 or 221 may be erroneously output from the output clock COUT1 or COUT2 in a beard shape. A means to guard is needed. However, in this embodiment, since the delay adjustment is started after the output clock is first switched by the switching unit 324, a beard-like waveform is not output, and such a guard unit is unnecessary.

  Also in this embodiment, the variable delay circuits 333 and 342 may delay the output of the variable delay circuit of the periodic data generation means 31 instead of directly delaying the input clock CLK3. Further, the delay times of the variable delay circuits 333 and 342 having outputs not selected as the output clock COUT3 are not limited to 0, and may be set to arbitrary values.

  Although the present invention has been described based on the preferred embodiment, the clock delay correction circuit of the present invention is not limited to the configuration of the above embodiment, and various modifications and changes can be made to the configuration of the above embodiment. Changes are also included in the scope of the present invention.

1 is a block diagram of a clock delay correction circuit according to a first embodiment of the present invention. The block diagram of the clock delay correction circuit which concerns on the 2nd Embodiment of this invention. The block diagram of the clock delay correction circuit which concerns on the 3rd Embodiment of this invention. FIG. 4 is a block diagram showing details of phase correction means in the clock delay correction circuit of FIG. 3. FIG. 2 is a timing chart showing the operation of the clock delay correction circuit of FIG. 1. FIG. 3 is a timing chart showing the operation of the clock delay correction circuit of FIG. 2. FIG. 4 is a timing chart showing the operation of the clock delay correction circuit of FIG. 3. The block diagram of the conventional clock delay correction circuit.

Explanation of symbols

10: Clock delay correction circuit 11: Period data generation means 111: Variable delay circuit 112: Phase comparison circuit 113: Counter 12: Phase correction means 121: Variable delay circuit 122: Phase comparison circuit 123: Counter 20: Clock delay correction circuit 21 : Period data generation means 211: Variable delay circuit 212: Phase comparison circuit 213: Counter 22: Phase correction means 221: Variable delay circuit 222: Phase comparison circuit 223: Counter 30: Clock delay correction circuit 31: Period data generation means 32: Phase correction means 320, 321: Phase adjustment means 322: Phase difference detection means 323: Switching signal generation means 324: Switching means 325, 326: Fixed delay means 331: Inverter 332, 341: AND circuits 333, 342: Variable delay circuit 351 : Phase comparison circuit 352: Counter

Claims (9)

The input clock signal, lower than the frequency of the input clock signal, and an output clock signal for receiving a reference clock signal having a frequency higher than half the frequency of the input clock signal, generated from the input clock signal In the clock delay correction circuit for synchronizing the phase of the reference clock signal with the phase of the reference clock signal,
Period data generating means for detecting a period of the input clock signal and generating period data indicating the period;
A first variable delay circuit that has a variable delay time and generates an output clock signal delayed from the input clock signal by at least the variable delay time, and compares the phase of the output clock signal with the phase of the reference clock signal When the comparison result that the phase of the output clock signal is advanced from the phase of the reference clock signal is obtained by the first phase comparison circuit and the first phase comparison circuit, the count is increased, and the count value is the period. A first counter that resets the count value when the value corresponds to the period indicated by the data, and the variable delay time of the first variable delay circuit is proportional to the count value of the first counter Phase correction means controlled at the time to
A clock delay correction circuit comprising:   The periodic data generation means has a variable delay time, delays the input clock signal to generate a first clock signal, a phase of the input clock signal, and the first clock signal And a second counter that counts up or down based on the comparison result of the second phase comparison circuit and outputs the count value as the period data. The clock delay correction circuit according to claim 1, wherein a variable delay time of the second variable delay circuit is controlled according to a count value of the second counter.   The clock delay correction circuit according to claim 2, wherein the first variable delay circuit directly delays the input clock signal.   The clock delay correction circuit according to claim 2, wherein the first variable delay circuit further delays the input clock signal delayed by the second variable delay circuit. The input clock signal, lower than the frequency of the input clock signal, and an output clock signal for receiving a reference clock signal having a frequency higher than half the frequency of the input clock signal, generated from the input clock signal In the clock delay correction circuit for synchronizing the phase of the reference clock signal with the phase of the reference clock signal,
Period data generating means for detecting a period of the input clock signal and generating period data indicating the period;
A first variable delay circuit having a variable delay time and generating a first clock signal delayed from the input clock signal by at least the variable delay time; and having a variable delay time and at least the variable delay from the input clock signal A second variable delay circuit that generates a second clock signal delayed by time, a selection circuit that selects the first or second clock signal based on a selection signal, and outputs the first clock signal as an output clock signal; A first phase comparison circuit that compares the phase of the output clock signal with the phase of the reference clock signal, and the phase of the output clock signal is advanced from the phase of the reference clock signal by the first phase comparison circuit When the comparison result is obtained by counting UP, when the count value matches the value corresponding to the period indicated by the period data, the count value Lise And a switching signal generating means for switching the selection signal in response to reset of the first counter, and the variable delay time of the first variable delay circuit is the first counter Phase correction means controlled at a time proportional to the count value of the counter;
A clock delay correction circuit comprising:   The phase correction unit further includes a reset unit that resets the variable delay time of the first or second variable delay circuit that generates a clock signal not selected by the selection circuit to 0 regardless of the count value. The clock delay correction circuit according to claim 5. The periodic data generating means has a variable delay time, delays the input clock signal to generate a third clock signal, a phase of the input clock signal, and the third clock signal And a second counter that counts up or down based on the comparison result of the second phase comparison circuit and outputs the count value as the period data. ,
The clock delay correction circuit according to claim 5 or 6, wherein a variable delay time of the third variable delay circuit is controlled according to a count value of the second counter.   The clock delay correction circuit according to claim 5, wherein the first and second variable delay circuits directly delay the input clock signal.   The clock delay correction circuit according to claim 5, wherein the first and second variable delay circuits further delay the input clock signal delayed by the third variable delay circuit.

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