JPH04291533A - Clock selection system for clock supply circuit - Google Patents

Abstract

PURPOSE:To reduce cost and power consumption by providing a 2nd clock source from which a standby clock is outputted to the clock supply circuit. CONSTITUTION:When the clock supply circuit is used for a repeater, a clock extracted from a reception signal is used for an active clock and it is inputted to a clock interrupt detection/switch section 140, from which the active clock is normally outputted. When the active clock is interrupted, the switch section 140 detects it and outputs a standby clock received from a 2nd clock source 150. Then, output of the switch section 140 is fed to a phase locked loop 110, from which a clock with a prescribed frequency phase-locked with the received clock is outputted. As a result, when the clock supply circuit is used for the repeater, a standby clock source 130 as a highly accurate clock source is not required by providing the 2nd clock source 150.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in the clock selection method of a clock supply circuit that can be used in both terminal equipment and regenerative repeaters of a high-speed optical transmission system.

[0002] The terminal equipment and regenerative repeaters of high-speed optical transmission systems use clocks for digital data transmission, relay amplification, etc., but the circuit that supplies this clock is not suitable for the terminal equipment from the viewpoint of efficiency, cost, etc. A circuit that can be used as both a regenerator and a regenerative repeater will be prepared. In this case, there is a need for a clock selection method for a clock supply circuit that can be manufactured at as low a cost as possible.

0003

2. Description of the Related Art FIG. 3 is a block diagram of an example of an optical transmission system. FIG. 4 is a block diagram showing the configuration of a conventional clock supply circuit.

In FIG. 3, terminal equipment (hereinafter referred to as LTE) 1 and 3 and optical regenerative repeater (hereinafter referred to as REG) 2 each have a clock supply circuit 4-1 having the same configuration.
, 4-2 and 4-3 are provided, and these LT
E1 and REG2 and REG2 and LTE3 are connected by optical fiber transmission lines, respectively. For example, in LTE1, input signals of a plurality of channels are multiplexed using a clock supplied from a clock supply circuit 4-1, converted into an optical signal, and then sent to an optical fiber transmission line.

The REG 2 receives an optical signal from the optical fiber transmission line, converts it into an electrical signal, and performs regenerative amplification using the clock supplied from the clock supply circuit 4-2. After converting it into an optical signal, it is sent to an optical fiber transmission line. In LTE3, an optical signal is received from the optical fiber transmission line and converted into an electrical signal, and input signals are demultiplexed using a clock supplied from a clock supply circuit 4-3.

The above-mentioned clock supply circuits 4-1 to 4-
The configuration of 3 is shown in Figure 4. Below is the clock supply circuit 4-
The operations of 1 (same as 4-3) and 4-2 will be explained. In FIG. 4, in the case of a clock supply circuit used for LTE 1 and 3, external units 12 (current) and 13 (spare) are connected to the clock supply circuit, and external units 12 and 1 are connected to the clock supply circuit.
3, the working and standby clocks (■, ■) are respectively input to the clock supply circuit.

In the clock supply circuit, the clock disconnection detection unit 5 normally selects and outputs the working clock (■), and when the working clock (■) fails, selects and outputs the spare clock (■) (■). . The output (■) of the clock loss detection unit 5 is applied to one input terminal of a phase comparator (hereinafter referred to as PC) 6 in a phase locked loop (hereinafter referred to as PLL) 11. The other input terminal of PC6 is connected to a voltage controlled oscillator (hereinafter referred to as V
(referred to as CO) 9 is divided into 1/2 by a frequency dividing circuit 10.
A signal whose frequency is divided by N and whose frequency is the same as that of the clock (■) added from the clock disconnection detection section 5 is added.

The PC 6 calculates the phase difference between two input signals (pulses), applies the output voltage corresponding to the phase difference to a low-pass filter (hereinafter referred to as LPF) 7, and outputs the resulting DC voltage component to the amplifier 8. After amplifying it, add it to VCO9. The VCO 9 adjusts the oscillation frequency according to the input DC voltage component and outputs it. The output of this VCO 9 is applied to the frequency dividing circuit 10 described above, and also to a subsequent circuit (not shown).

The external units 12 and 13 select and output one clock source from a plurality of high-precision clock sources (not shown). In addition, in the case of the clock supply circuit used for REG2, the clock extracted from the optical signal on the receiving side is input as the active clock (■), and the external unit 1 is used as the backup clock as in the case of LTE1 and 3 described above.
3 (spare) is input to the clock supply circuit (■).

In the clock supply circuit, the clock disconnection detection unit 5 normally selects and outputs the working clock (■), and when the working clock (■) fails, selects and outputs the spare clock (■) (■). . The output (■) of the clock disconnection detector 5 is set to P
In addition to LL11, the operation of PLL11 is the same as that of LTE1 and LTE3 described above, so its explanation will be omitted.

[0011] In this way, the clock is selected by the clock supply circuit.

0012

[Problems to be Solved by the Invention] However, in the above-mentioned clock supply circuit, only an internal clock is required in REG as a backup clock for REG2, so it is extremely inefficient to use an external unit. However, there were problems in that the cost and power consumption could not be ignored.

Therefore, an object of the present invention is to provide a clock selection system that can be manufactured at low cost.

[0014]

Means for Solving the Problems The above problems are solved by the circuit configuration shown in FIG. That is, in FIG. 1, the clock supply circuit used for the terminal equipment and the repeater is used. A clock is input, and normally the working clock is output, and when the working clock is interrupted, a backup clock is output.In the repeater, the clock extracted from the received signal is input as the working clock, and normally the working clock is output. A clock disconnection detection/switch section 140 outputs a clock and outputs a spare clock input from the second clock source 150 when the current clock is disconnected, and the output of the clock disconnection detection/switch section 140 is input. A phase-locked loop 110 outputs a clock of a predetermined frequency that is phase-synchronized with the clock.

[0015]

[Operation] In FIG. 1, when the clock supply circuit of the present invention is used in a terminal device, clock disconnection is detected for the current and backup clocks output from the current and backup clock sources 120 and 130 having a predetermined frequency accuracy. /switch section 14
Enter 0. The clock disconnection detection/switch section 140 normally outputs the current clock, but when the current clock is disconnected, it detects this and outputs a backup clock.

Next, the clock disconnection detection/switch section 140
The output of the phase-locked loop 110 is added to the phase-locked loop 110, and the phase-locked loop 110 outputs a clock of a predetermined frequency that is phase-synchronized with the input clock. When used in a terminal device, it is the same as the conventional example.

On the other hand, when used in a repeater, the clock extracted from the received signal is input as the current clock to the clock disconnection detection/switch section 140, and normally the current clock is output. Also, when the current clock is disconnected, the clock disconnection detection/switch section 140 detects this and outputs the backup clock input from the newly provided second clock source 150.

Next, clock disconnection detection/switch section 140
The output of the phase-locked loop 110 is added to the phase-locked loop 110, and the phase-locked loop 110 outputs a clock of a predetermined frequency that is phase-synchronized with the input clock.

As a result, by providing the second clock source 150, when the clock supply circuit of the present invention is used in a repeater, the backup clock source 130 as a high-precision clock source is unnecessary, and the cost is reduced. Low power consumption can be achieved.

[0020]

Embodiment FIG. 2 is a block diagram showing the configuration of a clock supply circuit according to an embodiment of the present invention. The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, LTE1 and LTE3 are the same as in the conventional example. That is, in the case of a clock supply circuit used for LTE 1 and 3, external units 12 (current) and 13 (spare) are connected to the clock supply circuit,
From 12 and 13, the working and spare clocks (■
, ■) are input to the clock supply circuit.

In the clock supply circuit, the clock disconnection detection unit 5 normally selects and outputs the working clock (■), and when the working clock (■) fails, selects and outputs the spare clock (■) (■). . The output (■) of the clock loss detection unit 5 is sent to P via a selection circuit (hereinafter referred to as SEL) 14, which will be described later.
It is added to one input terminal of PC6 in LL11. PC6
After dividing the frequency of the output of the VCO 9 to 1/N by the frequency dividing circuit 10 to make it the same frequency as the frequency of the clock (■) applied from the clock disconnection detector 5, the other input terminal of Add via SEL17.

The PC 6 determines the phase difference between the two input signals (pulses), and the output voltage corresponding to the phase difference is applied to the LPF 7. The resulting DC voltage component is amplified by the amplifier 8 and then applied to the VCO 9. The VCO 9 adjusts the oscillation frequency according to the input DC voltage component and outputs it. This VCO9
The output is applied to the frequency dividing circuit 10 described above, and also to a subsequent circuit (not shown).

Next, in the case of the clock supply circuit used for REG2, the clock extracted from the optical signal on the receiving side is input as the active clock (■), and the newly installed oscillator (hereinafter referred to as OSC) is used as the backup clock. The clock (■) from No. 15 is input to the clock supply circuit.

In the clock supply circuit, the clock disconnection detection unit 5 normally receives the current clock (■), and when the current clock (■) fails, the clock from the OSC 15 (■)
Select and output (■). The output (■) of SEL14 is applied to one input terminal of PC6 in PLL11'. The other input terminal of the PC6 is supplied with the frequency of the output of the VCO 9 which is divided into 1/N by the frequency dividing circuit 10, further divided by 1/M by the frequency dividing circuit 16, and then added from the current clock ■ or the OSC 15. After setting the frequency to the same as that of the clock (■),
Add to SEL17. REG use side at SEL17 (■)
The output of the frequency dividing circuit 16 is applied to the other input terminal of the PC 6.

The phase difference between the two input signals (pulses) is determined by the PC 6, and the output voltage corresponding to the phase difference is applied to the LPF 7. The resulting DC voltage component is amplified by the amplifier 8 and then applied to the VCO 9. The VCO 9 adjusts the oscillation frequency according to the input DC voltage component and outputs it. This VCO9
The output is applied to the frequency dividing circuit 10 described above, and also to a subsequent circuit (not shown).

In this way, by providing the OSC 15 for internal clock, an external unit as a high-precision clock source is unnecessary when used in REG, and low cost and low power consumption can be realized. .

[0028]

As explained above, according to the present invention, by providing the second clock source 150 that outputs a spare clock to the clock supply circuit, it can be used as a highly accurate clock source when used in a repeater. No external unit is required, making it possible to achieve low cost and low power consumption.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the principle of the present invention.

FIG. 2 is a block diagram showing the configuration of a clock supply circuit according to an embodiment of the present invention;

FIG. 3 is a configuration diagram of an example optical transmission system.

FIG. 4 is a block diagram showing the configuration of a conventional clock supply circuit.

[Explanation of symbols]

110 is a phase locked loop, 140 is a clock disconnection detection/switch unit, and 150 is a second clock source.

Claims (1)

[Claims] 1. A clock supply circuit used for a terminal device and a repeater, wherein the terminal device includes a working clock source and a standby clock source (120,
130), normally outputs the current clock, outputs the backup clock when the current clock is disconnected, and in the repeater extracts the clock extracted from the received signal. A clock interruption detection/switch unit (140) inputs a clock as a working clock, normally outputs the working clock, and outputs a spare clock input from a second clock source (150) when the working clock is interrupted. ), and a phase-locked loop (110) that inputs the output of the clock disconnection detection/switch section (140) and outputs a clock of a predetermined frequency that is phase-synchronized with the input clock. Supply circuit clock selection method.