JP2002198810A - Input disconnection detection circuit of optical receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the input disconnection detection circuit of an optical receiver which is capable of detecting input disconnection accurately by realizing a circuit that avoids wrong synchronization caused by the effect of synchronous noises in an input disconnection detection based on the synchronous/ asynchronous state of a PLL circuit. SOLUTION: This input disconnection detection circuit of an optical receiver has a circuit structure equipped with a noise superposition unit 20 which superposes asynchronous noises having a frequency component that gets the PLL circuit asynchronous on signals inputted into the phase comparator 5 of the PLL circuit. By this setup, when the input of the optical signals is disconnected, the PLL circuit is hardly affected by synchronous noises, so that an accurate input disconnection can be detected because the PLL circuit gets into an asynchronous state by the effect of the asynchronous noises.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input disconnection detecting circuit of an optical receiver used for optical communication, and more particularly to detecting an input disconnection of an optical signal based on a synchronous / asynchronous state of a phase locked loop (PLL) circuit. The present invention relates to an input disconnection detection circuit of an optical receiver.

[0002]

2. Description of the Related Art An optical receiver used for optical communication generally has an input disconnection detection circuit for detecting an optical input disconnection in accordance with a reception state of an optical signal input via a transmission line or the like. is there. As a conventional input disconnection detection circuit, for example,
As described in Japanese Patent Application Laid-Open No. 9-114925, input of an optical signal is interrupted based on a synchronous / asynchronous state of a phase locked loop (PLL) circuit that generates a timing signal (clock signal) based on a received optical signal. Is detected.

FIG. 22 shows a conventional input disconnection detection as described above.
FIG. 2 is a block diagram illustrating a configuration example of an optical receiver including a circuit.
You. In the configuration example of FIG. 22, the light receiving via an external transmission path or the like is performed.
The optical signal input to the transceiver is received by the light receiving element 1 and
The signal is converted into an air signal and amplified by the preamplifier 2. Preah
The output signal of the amplifier 2 is further supplied to the main amplifier 3 and the
After being amplified to the required level by the
It is input to the comparator 5. The phase comparator 5 has a charge pump
6, low-pass filter (LPF) 7 and voltage control generator
It composes a PLL circuit together with the vibrator (VCO) 8.
is there. In this phase comparator 5,
Output signal Q and inverted output signal / Q and voltage controlled oscillator 8
Phase comparison with the output signal from the
The signal passes through the charge pump 6 and the low-pass filter 7
Is sent to the voltage-controlled oscillator 8 so that the voltage-controlled oscillation
The oscillation frequency of the device 8 is variably controlled. And voltage control
The output signal of the oscillator 8 is free as the clock signal CLK.
The clock signal sent to the flip-flop circuit (F / F) 9
Signal received through the phase comparator 5 according to the signal CLK
Data identification processing is executed, and the data indicating the identification result
The signal and the clock signal CLK are supplied to the flip-flop circuit
Data output terminal OUT from path 9_DATAAnd clock output
Terminal OUT _CLKIs output to the outside through the respective. Ma
In addition, the synchronous / asynchronous state of the PLL circuit
Lock detector using the signal output from the filter 7
Monitored at 10 to detect the asynchronous state of the PLL circuit
Is detected by the input disconnection detection circuit 11
The input disconnection detection alarm signal is output from the alarm output terminal OUT.
_ALMOutput to the outside. The PLL circuit
Configuration that detects input disconnection based on the
It is effective in that it enables downsizing and lower power consumption.
is there.

[0004]

However, in the conventional input disconnection detection circuit as described above, if the PLL circuit is erroneously synchronized due to the influence of noise from peripheral circuits and the like,
Even if the input of the desired optical signal is interrupted, there is a disadvantage that the input disconnection detection alarm signal is not output. In general,
In the optical communication system, the output signal of the optical receiver as shown in FIG. 22 is ^{N N} (N = 2, 3, 4,
…) Is often used after frequency separation.
Many data signals and clock signals having a frequency component synchronized with the LL circuit exist around the optical receiver, and there is a very high possibility that such a signal leaks to the optical receiver as noise. Therefore, there is a problem that erroneous input disconnection is detected due to erroneous synchronization of the PLL circuit under the influence of noise having a frequency component with which the PLL circuit synchronizes (hereinafter, referred to as synchronization noise). Was.

The present invention has been made in view of the above points, and realizes a circuit configuration for detecting an input disconnection based on a synchronous / asynchronous state of a PLL circuit and avoiding erroneous synchronization due to the influence of synchronous noise. An object of the present invention is to provide an input disconnection detection circuit of an optical receiver that enables accurate input disconnection detection.

[0006]

According to a first aspect of the present invention, there is provided a phase locked loop (PLL) circuit for generating a timing signal using an optical reception signal. In the input disconnection detection circuit of the optical receiver for detecting the input disconnection of the optical signal based on the synchronous / asynchronous state of the above, asynchronous noise having a frequency component at which the PLL circuit becomes asynchronous is input to the phase comparator of the PLL circuit. And a noise superimposing unit for superimposing on the signal to be reproduced. It is preferable that the level of the asynchronous noise be set higher than the level of the synchronous noise for which malfunction is to be prevented.

In such a configuration, the asynchronous noise that causes the PLL circuit to be in an asynchronous state is superimposed on the input signal of the phase comparator, so that when the input of the optical signal is interrupted, the PLL circuit is less affected by the synchronous noise, and Asynchronous state due to noise. As a result, the disconnection of the optical signal can be accurately detected based on the synchronous / asynchronous state of the PLL circuit.

Further, the input disconnection detection circuit of the optical receiver according to the second invention detects an input disconnection of an optical signal based on a synchronous / asynchronous state of a PLL circuit that generates a timing signal using the optical received signal. The input disconnection detection circuit of the optical receiver includes a sensitivity control unit that adjusts the sensitivity of the phase comparator of the PLL circuit. In such a configuration, for example, by performing control such that the sensitivity of the phase comparator is reduced according to the amplitude of the synchronization noise, even when the input of the optical signal is interrupted, the PLL circuit does not erroneously synchronize due to the synchronization noise. An input disconnection of an optical signal can be accurately detected based on the synchronous / asynchronous state of the circuit.

The input disconnection detection circuit of the optical receiver according to the third invention detects an input disconnection of an optical signal based on a synchronous / asynchronous state of a PLL circuit that generates a timing signal using the optical received signal. The input disconnection detection circuit of the optical receiver includes a duty control unit that controls a duty ratio of a signal input to a phase comparator of a PLL circuit.

In such a configuration, for example, by controlling the duty ratio of the input signal to the phase comparator in accordance with the spectrum of the synchronization noise, the power of the center frequency component of the input signal is reduced, and Even when the input is disconnected, the PLL circuit does not erroneously synchronize due to the synchronization noise, so that the input disconnection of the optical signal can be accurately detected based on the synchronous / asynchronous state of the PLL circuit.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. First, a basic configuration of an input disconnection detection circuit of an optical receiver according to the present invention will be described. FIG.
FIG. 1 is a block diagram illustrating an example of an optical receiver having a first basic configuration of the present invention. The same parts as those in the conventional configuration shown in FIG. 22 are denoted by the same reference numerals.

In FIG. 1, a first basic configuration of the present invention relates to a circuit configuration for detecting an input disconnection based on a synchronous / asynchronous state of a PLL circuit. Is characterized by providing a noise superimposing unit 20 for superimposing noise having a frequency component to be asynchronous (hereinafter referred to as asynchronous noise), and the level of the superimposed noise is preferably synchronized to prevent malfunction. It is set to be higher than the noise level.

The noise superimposing section 20 superimposes asynchronous noise on the output signal Q and the inverted output signal / Q sent from the limit amplifier 4 to the phase comparator 5, for example. The position where the asynchronous noise is superimposed is not limited to the position between the limit amplifier 4 and the phase comparator 5, but any position where the asynchronous noise can be superimposed on the optical reception signal between the light receiving element 1 and the phase comparator 5. It is possible. Also,
It is desirable to set the level of the asynchronous noise so as to be sufficiently lower than the level of the optical reception signal.

The light receiving element 1 receives an optical signal input to an optical receiver via an external transmission line or the like and converts it into an electric signal. For example, the light receiving element 1 may be an avalanche photodiode (APD) or a PIN photo diode. It is possible to use a diode or the like. Here, it is assumed that the reverse bias applied to the light receiving element 1 is V _PD . Preamplifier 2
This is a known preamplifier that converts a current signal generated in the light receiving element 1 into a voltage signal, amplifies the voltage signal to a required level, and outputs the amplified signal. The main amplifier 3 amplifies the signal output from the preamplifier 2 to a predetermined level according to the reference voltage _VREF and outputs the signal. The limit amplifier 4 further amplifies the signal output from the main amplifier 3 and outputs the output signal Q and the inverted output signal / Q to the phase comparator 5 of the PLL circuit.
Send to

The PLL circuit comprises a phase comparator 5, a charge pump 6, a low-pass filter (LPF) 7, and a voltage controlled oscillator (VCO) 8, and the signals Q and / Q output from the limit amplifier 4 and the voltage controlled oscillator. The phase comparison with the output signal from the output signal 8 is performed by the phase comparator 5, and a signal corresponding to the phase difference is sent to the voltage controlled oscillator 8 via the charge pump 6 and the low-pass filter 7. Is variably controlled.

A flip-flop circuit (F / F) 9 performs data identification processing of the received signal that has passed through the phase comparator 5 in accordance with the clock signal CLK output from the voltage controlled oscillator 8, and data indicating the identification result. The signal and the clock signal CLK are output to the outside via the data output terminal OUT _DATA and the clock output terminal OUT _CLK , respectively.

The lock detector 10 monitors the synchronous / asynchronous state of the PLL circuit using a signal output from the low-pass filter 7, for example. For example, when the output signal level of the low-pass filter 7 is out of the predetermined range, it is determined to be asynchronous. The predetermined range used for the determination of the synchronous / asynchronous state may be set to, for example, a range near the level of the signal output from the low-pass filter 7 when the PLL circuit is synchronized with a desired signal. It is possible.

The input disconnection detection circuit 11 includes a lock detector 10
When the asynchronous state of the PLL circuit is detected in step (1), the disconnection of the optical signal is determined, and an input disconnection detection alarm signal is output to the outside via the alarm output terminal OUT _ALM . In the optical receiver having the above-described first basic configuration, when the input of the optical signal is interrupted, the phase of the synchronous noise having the frequency component synchronized with the PLL circuit and the asynchronous noise from the noise superimposing unit 20 are compared. The signal is sent as an input signal to the device 5 and a phase comparison with a feedback signal from the voltage controlled oscillator 8 is performed. At this time, if the level of the asynchronous noise is higher than the level of the synchronous noise, the PLL circuit is placed in an asynchronous state due to the asynchronous noise, and a state in which the PLL circuit is erroneously synchronized by the influence of the synchronous noise is avoided. As a result, the asynchronous state of the PLL circuit is detected by the lock detector 10, the input disconnection of the optical signal is determined by the input disconnection detection circuit 11, and the input disconnection detection alarm signal is output to the outside via the alarm output terminal OUT _ALM. Become so. On the other hand, when the optical signal is being input to the optical receiver, if the level of the asynchronous noise is set to be sufficiently smaller than the level of the optical received signal input to the phase comparator 5, the PLL The circuit is brought into a synchronized state by the optical reception signal, and a clock signal CLK having a desired frequency is generated.

As described above, according to the first basic configuration of the present invention, the noise superimposing section 20 is provided so that the asynchronous noise is superimposed on the signal input to the phase comparator 5,
When the input of the optical signal is interrupted, the PLL circuit is hardly affected by the synchronous noise and becomes in an asynchronous state due to the effect of the asynchronous noise. Therefore, it is necessary to accurately detect the optical signal input disconnection based on the synchronous / asynchronous state of the PLL circuit. Becomes possible. Further, by adjusting the level of the asynchronous noise, it becomes possible to appropriately set the input light level at which the input disconnection detection alarm signal is issued.

In the first basic configuration shown in FIG. 1, the reception signal on which the asynchronous noise is superimposed is
Is transmitted to the flip-flop 9 via the data bus, so that it may be necessary to consider the influence of the asynchronous noise on the main signal in data identification processing or the like. FIG. 2 shows a modification of the first basic configuration that addresses such a case.
Is shown in the block diagram of FIG.

In the modification of FIG. 2, the output signal of the main amplifier 3 is branched into two paths, the signal transmitted on one path is sent to the flip-flop 9 via the limit amplifier 4, and the signal transmitted on the other path. Is sent to the phase comparator 5 via the limit amplifier 4 '. As described above, if the received signal to be sent to the PLL circuit is separated from the path of the main signal system where the data identification processing is performed, and the asynchronous noise is superimposed, the data identification of the received signal can be performed without being affected by the asynchronous noise. Processing can be performed.

Here, a specific embodiment to which the above-described first basic configuration is applied will be described. FIG. 3 is a block diagram illustrating a configuration of an optical receiver according to Embodiment 1-1 to which the first basic configuration is applied. In FIG. 3, the first embodiment
The optical receiver of -1 has a specific circuit configuration of the noise superimposing unit 20 in the first basic configuration shown in FIG.
It is provided with a level detection circuit 21 and a reverse bias control circuit 22. Here, A is used as the light receiving element 1.
Use PD.

The level detecting circuit 21 detects, for example, the level of a signal sent from the limit amplifier 4 to the phase comparator 5, and transmits the result to the reverse bias control circuit 22.
The reverse bias control circuit 22 controls the reverse bias V _{PD applied} to the light receiving element (APD) 1 according to the detection result of the level detection circuit 21. Specifically, when it is determined based on the detection result of the level detection circuit 21 that the level of the optical signal input to the optical receiver has decreased to a level corresponding to the input interruption, the value of the reverse bias V _PD is determined. And the multiplication factor M of the light receiving element (APD) 1 is increased. As a result, noise due to dark current generated in the light receiving element (APD) 1 increases, and the noise due to the dark current is output from the light receiving element 1 as the asynchronous noise described above, and is sequentially transmitted to the preamplifier 2, the main amplifier 3, and the limit amplifier 4. The signal is amplified and input to the phase comparator 5. The reverse bias V _PD when the input light level becomes a level corresponding to the input disconnection is such that the level after amplifying the dark current generated in the light receiving element (APD) 1 by each of the amplifiers 2 to 4 indicates a malfunction. Light receiving element (APD) 1 that is higher than the level of the synchronization noise to be prevented
Is desirably set in accordance with the multiplication factor M.

Thus, when the input of the optical signal is interrupted, the PLL circuit is likely to be in the asynchronous state due to the asynchronous noise using the dark current of the light receiving element (APD) 1, and the erroneous synchronization due to the influence of the synchronous noise is avoided and the accurate input is prevented. Disconnection detection becomes possible. In the above embodiment 1-1, a specific example corresponding to the above-described circuit configuration shown in FIG. 1 has been described. However, a circuit in which the influence of asynchronous noise on the main signal as shown in FIG. The same applies to the configuration. The specific circuit configuration in this case is shown in the block diagram of FIG. In FIG. 4, for example, the limit amplifier 4 '
The circuit configuration is such that the level of the signal sent from the controller to the phase comparator 5 is detected by the level detection circuit 21.

FIG. 5 is a block diagram showing the configuration of Embodiment 1-2 of the optical receiver to which the first basic configuration is applied. In FIG. 5, the optical receiver of the embodiment 1-2 is the same as that of FIG.
The amplifier 23 is provided as a specific circuit configuration of the noise superimposing unit 20 in the first basic configuration shown in FIG. The amplifier 23 branches the clock signal CLK output from the flip-flop 9 and amplifies it to a required level, and uses the amplified clock signal CLK ′ as asynchronous noise to be output from the limit amplifier 4 to the phase comparator 5. The signal Q and the inverted output signal / Q are superimposed on each other. It is desirable that the amplification operation of the amplifier 23 be set so that the level of the clock signal CLK 'is higher than the level of the synchronization noise for which the influence of the malfunction is desired to be prevented.

The clock signal CLK output from the flip-flop 9 has a frequency corresponding to the bit rate of the received optical signal, and this frequency corresponds to twice the synchronous frequency of the PLL circuit. To Therefore, when the amplified clock signal CLK 'is superimposed on the input signal to the phase comparator 5, when the input of the optical signal is interrupted, the PLL circuit is likely to be in an asynchronous state due to the clock signal CLK', and the influence of the synchronous noise. As a result, erroneous synchronization can be avoided, and accurate input disconnection can be detected.

In the embodiment 1-2, a specific example corresponding to the circuit configuration shown in FIG. 1 has been described.
The same applies to a circuit configuration in which the influence of the asynchronous noise on the main signal as shown in FIG. 2 is taken into consideration. A specific circuit configuration in this case is shown in the block diagram of FIG. 6, the clock signal CLK 'amplified to a required level by the amplifier 23 is superimposed on the output signal Q and the inverted output signal / Q sent from the limit amplifier 4' to the phase comparator 5, respectively. And As a modification of the circuit configuration of FIG. 6, the clock signal CLK ′ amplified by the amplifier 23 is
By giving it as a reference signal of the limit amplifier 4 ', asynchronous noise may be superimposed on the signals Q and / Q output from the limit amplifier 4'. The circuit configuration in this case is shown in the block diagram of FIG.

Next, a second basic configuration of the input disconnection detection circuit of the optical receiver according to the present invention will be described. FIG. 8 is a block diagram showing a second basic configuration of the present invention. In FIG. 8, a second basic configuration of the present invention is a sensitivity control unit that lowers the sensitivity of the phase comparator 5 according to the amplitude of the synchronization noise in the same circuit configuration as the conventional case shown in FIG. 30 is provided. Here, the sensitivity of the phase comparator 5 means the minimum amplitude of the input signal that can bring the PLL circuit into a synchronized state, and lowers the sensitivity of the phase comparator 5 according to the amplitude of the synchronization noise. Then, the minimum amplitude of the synchronizable input signal of the phase comparator 5 becomes large, and the PLL circuit is hardly synchronized by the synchronization noise.

The sensitivity of the phase comparator 5 controlled by the sensitivity control unit 30 depends on the input of the optical reception signal and the PLL.
It is assumed that the sensitivity of the circuit is set to a value higher than the synchronizable sensitivity. In other words, the minimum amplitude of the synchronizable input signal for the phase comparator 5 is set to be smaller than the amplitude of the optical reception signal. In addition, the configuration of the other parts other than the sensitivity control unit 30 is the same as that of the first basic configuration, and the description is omitted here.

In the optical receiver having the second basic configuration as described above, when the input of the optical signal is interrupted, the phase comparator 5
, A synchronization noise having a frequency component to which the PLL circuit can synchronize is input. However, if the minimum amplitude of the synchronizable input signal of the phase comparator 5 is large with respect to the amplitude of the synchronous noise, the PLL circuit is in an asynchronous state, and a state in which the synchronous circuit is erroneously synchronized by the influence of the synchronous noise. Be avoided. As a result, the asynchronous state of the PLL circuit is detected by the lock detector 10, the input disconnection of the optical signal is determined by the input disconnection detection circuit 11, and the input disconnection detection alarm signal is output to the outside via the alarm output terminal OUT _ALM. Become so. On the other hand, when the optical signal is being input to the optical receiver, the phase comparator 5 is set to have a sufficient sensitivity to the optical reception signal input to the phase comparator 5, so that the PLL circuit Are synchronized by the optical reception signal, and a clock signal CLK having a desired frequency is generated.

As described above, according to the second basic configuration of the present invention, the sensitivity control section 30 is provided so that the sensitivity of the phase comparator 5 can be adjusted. When erroneous synchronization is likely to occur, the sensitivity control unit 30 adjusts the sensitivity of the phase comparator 5 in a lowering direction to avoid erroneous synchronization. Note that as the sensitivity is lowered, the guarantee of PLL synchronization with a desired optical reception signal approaches an uncertainty, but since the sensitivity can be adjusted individually according to the degree of influence of the synchronization noise, the desired optical reception signal can be adjusted. P
LL synchronization is not affected uniformly. Further, by adjusting the sensitivity of the phase comparator 5, it becomes possible to appropriately set the input light level at which the input disconnection detection alarm signal is issued.

In the second basic configuration, similarly to the case shown in FIG. 2, the received signal to be sent to the PLL circuit is separated from the path of the main signal system where the data identification processing is performed. Is also good. FIG. 9 is a block diagram showing a modification of the second basic configuration. here,
A specific embodiment to which the above-described second basic configuration is applied will be described.

FIG. 10 is a block diagram showing a configuration of an embodiment 2-1 of the optical receiver to which the second basic configuration is applied.
10, the optical receiver according to the embodiment 2-1 has an offset control circuit 31, resistors 32 and 33, and a specific circuit configuration of the sensitivity control unit 30 in the second basic configuration shown in FIG. This is provided with capacitors 34 and 35.

The offset control circuit 31 generates an offset voltage having a variable level, and
The voltage is applied to each input node of the phase comparator 5 via the reference numerals 2 and 33. Capacitors 34 and 35 are inserted between the offset voltage application points and the output terminals of the limit amplifier 4, respectively, and the AC components of the signals Q and / Q output from the limit amplifier 4 are used as phase comparators. 5 is transmitted.

In the above circuit configuration, the phase comparator 5
By applying an offset voltage to each input node, the effective amplitude of the input signal to the phase comparator 5 is reduced. Specifically, for example, as shown in the upper part of FIG. 11, the input signal of the phase comparator 5 before the application of the offset voltage is output from the limit amplifier 4 as the effective amplitude A for performing the phase comparison. An amplitude corresponding to the difference between the high and low levels of the signals Q and / Q is secured. On the other hand, FIG.
As shown in the lower part of FIG. 1, the input signal of the phase comparator 5 after the application of the offset voltage has an effective amplitude because the DC voltage levels of the signals Q and / Q are shifted in opposite directions by the offset voltage. It becomes smaller from A to A '.
The effect that the effective amplitude is reduced by the application of the offset voltage acts on both the optical reception signal input to the phase comparator 5 and the synchronization noise. Therefore, the fact that the effective amplitude of each of the optical reception signal and the synchronization noise input to the phase comparator 5 becomes smaller means that the minimum amplitude of the synchronizable input signal of the phase comparator 5 becomes relatively larger. become.

Here, assuming that the minimum amplitude of the synchronizable input signal for the phase comparator 5 is set to a constant value, the value of the minimum amplitude is smaller than the effective amplitude of the optical reception signal after the application of the offset voltage. The offset voltage is adjusted so as to reduce the voltage. As a result, while the input of the optical signal is continued, the PLL circuit is synchronized by the optical reception signal, and when the input of the optical signal is interrupted, the PLL circuit is hardly erroneously synchronized by the synchronous noise, and the asynchronous state is realized. In addition, it is possible to perform an adjustment capable of detecting an input disconnection accurately based on the synchronous / asynchronous state of the PLL circuit.

In the above embodiment 2-1, a concrete example corresponding to the circuit configuration shown in FIG.
The same can be applied to a circuit configuration in which a reception signal to be sent to the PLL circuit as shown in FIG. 9 is separated from the path of the main signal system. A specific circuit configuration in this case is shown in the block diagram of FIG. Also in the circuit configuration of FIG. 12, the offset voltage generated by the offset control circuit 31 is connected between the capacitors 34 and 35 at the subsequent stage of the limit amplifier 4 ′ and the input terminals of the phase comparator 5 via the resistors 32 and 33. Applied to nodes in between.

FIG. 13 is a block diagram showing the configuration of an embodiment 2-2 of the optical receiver to which the second basic configuration is applied.
13, the optical receiver of the embodiment 2-2 detects the levels of the signals Q and / Q output from the limit amplifier 4 in the circuit configuration of the embodiment 2-1 shown in FIG. A level detection circuit 36 is provided, and the offset voltage generated by the offset control circuit 31 is automatically controlled according to the detection result of the level detection circuit 36. Specifically, when the offset control circuit 31 determines that the level of the optical signal input to the optical receiver has decreased to a level corresponding to the input interruption based on the detection result of the level detection circuit 36, Control is performed to increase the offset voltage. Thereby, the effective amplitude of the input signal to the phase comparator is reduced, so that the sensitivity of the phase comparator 5 is relatively lower than when an optical signal is input, and erroneous synchronization of the PLL circuit due to synchronization noise is avoided. As a result, accurate input disconnection detection becomes possible.

As described above, if the offset voltage is automatically controlled by detecting the level of the optical reception signal, an appropriate offset voltage can be obtained even if the operating points of the amplifiers 2 to 4 fluctuate, for example. Since the voltage can be applied, it is possible to stably detect the interruption of the input of the optical signal. The circuit configuration of the embodiment 2-2 can be similarly applied to a circuit configuration in which the reception signal to be sent to the PLL circuit shown in FIG. 12 is separated from the path of the main signal system. . The specific circuit configuration in this case is shown in the block diagram of FIG. In FIG. 14, for example,
The level of the signal output from the main amplifier 3 to the limit amplifier 4 is detected by the level detection circuit 36, and the detection result is transmitted to the offset control circuit 31.

In the above embodiments 2-1 and 2-2, the offset voltage is applied between the limit amplifier 4 and the phase comparator 5, but the offset voltage application position is limited to this. Instead, it is possible to apply the offset voltage at an arbitrary position before the phase comparator 5. Next, a third basic configuration of the input disconnection detection circuit of the optical receiver according to the present invention will be described.

FIG. 15 is a block diagram showing a third basic configuration of the present invention. In FIG. 15, a third basic configuration of the present invention is based on a duty control unit 40 that controls the duty ratio of a signal input to the phase comparator 5 for the same circuit configuration as the conventional case shown in FIG. Is provided. The duty control unit 40 includes, for example,
The duty ratio of the signal input to the phase comparator 5 is variably controlled by adjusting the reference voltage V _REF of the main amplifier 3 and the like. Specifically, the duty ratio of the optical signal input to the optical receiver is Assuming that the ratio is set to 100%, the duty ratio of the signal output from the main amplifier 3 is reduced by slightly shifting the reference voltage V _REF of the main amplifier 3 from the center voltage value of the received data. Set. Here, the duty ratio indicates a rate at which data becomes a high level (optical signal is turned on) within one time slot for the input optical signal.

As described above, the signal input to the phase comparator 5
When the duty ratio is reduced, the center frequency of the input signal
The power of several components can be reduced. Sand
That is, for example, as shown in FIG.
When control is performed to B% (A> B), the spectrum of the input signal
The center frequency f₀The power level of the component is P_{0 A}
To P_0BWill decrease. This duty ratio control
Center frequency f₀When the power of the component decreases
The effect of this is that the optical reception signal input to the phase comparator 5 and the
It will work for both the synchronization noise.

Therefore, assuming that the minimum power of the frequency component that can be synchronized with the PLL circuit is set to a predetermined value for the input signal of the phase comparator 5, the minimum power value is the light after the duty ratio adjustment. By controlling the duty ratio within a range that is smaller than the center frequency f ₀ component power of the received signal, even when the input of the optical signal is interrupted,
The PLL circuit is in an asynchronous state regardless of the synchronous noise.

As described above, according to the third basic configuration of the present invention, the duty control unit 40 is provided to control the duty ratio of the input signal to the phase comparator 5 according to the spectrum of the synchronization noise. When the input of the optical signal is cut off,
The L circuit can be hardly erroneously synchronized due to the synchronization noise, and it is possible to accurately detect the interruption of the input of the optical signal based on the synchronous / asynchronous state of the PLL circuit. Further, by adjusting the duty ratio of the input signal to the phase comparator 5, it becomes possible to appropriately set the input light level at which the input disconnection detection alarm signal is issued.

In the third basic configuration, similarly to the case shown in FIG. 2, the received signal to be sent to the PLL circuit is separated from the path of the main signal system where data identification processing is performed. Is also good. FIG. 17 is a block diagram showing a modification of the third basic configuration. FIG.
_Here , the duty ratio of the input signal to the phase comparator 5 is controlled by the duty control unit 40 adjusting the reference voltage V _REF of the limit amplifier 4 ′.

Here, the third basic configuration as described above is applied.
A specific embodiment used will be described. FIG.
Embodiment 3-1 of the optical receiver to which the third basic configuration is applied
FIG. 3 is a block diagram illustrating a configuration. In FIG.
The optical receiver in the state 3-1 is the third base shown in FIG.
Specific circuit configuration of the duty control unit 40 in this configuration
Connected to the reference input terminal of the main amplifier 3.
The variable power supply 41 is provided between the ground terminal. this
The reference supplied to the main amplifier 3 by the variable power supply 41
Reference voltage V_{RE F}To adjust the input signal to the phase comparator 5
By controlling the duty ratio of
The power of the center frequency component of the initial noise is the same as that of the PLL circuit.
Is set to be less than the minimum
This prevents erroneous synchronization due to synchronization noise when the input is disconnected.
Swell.

In the modification of the third basic configuration shown in FIG. 17, the variable power supply 41 can be used for the duty control unit 40 in the same manner as in the embodiment 3-1. is there. The specific circuit configuration in this case is shown in the block diagram of FIG. FIG. 20 is a block diagram illustrating a configuration of Embodiment 3-2 of the optical receiver to which the third basic configuration is applied.

In FIG. 20, the optical receiver of the embodiment 3-2 is different from the circuit configuration of the embodiment 3-1 shown in FIG. A level detection circuit 42 for detecting the levels of the signals Q and / Q, and a reference control circuit 43 for automatically controlling a reference voltage V _REF to the main amplifier 3 according to the detection result of the level detection circuit 42 are provided. is there. Specifically, when the reference control circuit 43 determines based on the detection result of the level detection circuit 42 that the level of the optical signal input to the optical receiver has decreased to a level corresponding to the input interruption, The reference voltage V _REF to the main amplifier 3 is raised to a predetermined level and the phase comparator 5
To control the duty ratio of the input signal. This allows
Even when the input of the optical signal is interrupted, erroneous synchronization due to the synchronization noise can be avoided.

As described above, by automatically controlling the reference voltage V _REF by detecting the level of the optical reception signal, even if the operating points of the amplifiers 2 to 4 fluctuate, for example, the phase comparator Since the duty ratio of the signal input to 5 is appropriately controlled, it is possible to stably detect the input disconnection of the optical signal. Also, in the modification of the embodiment 3-1 shown in FIG. 19, the level detection circuit 4 is replaced with the variable power supply 41 in the same manner as in the embodiment 3-2.
2 and the reference control circuit 43 can be provided. The specific circuit configuration in this case is shown in the block diagram of FIG. In FIG. 21, for example, the level of a signal output from the main amplifier 3 to the limit amplifier 4 is detected by the level detection circuit 42, and the detection result is transmitted to the reference control circuit 43.

In the above embodiments 3-1 and 3-2, the reference voltage of the main amplifier 3 is adjusted. However, the present invention is not limited to this, and the reference voltage of the limit amplifier 4 is adjusted. The duty ratio of the input signal to the phase comparator 5 may be controlled.

(Supplementary Note 1) An input disconnection detection circuit of an optical receiver for detecting an input disconnection of an optical signal based on a synchronous / asynchronous state of a phase locked loop circuit that generates a timing signal using an optical reception signal. An optical receiver comprising: a noise superimposing unit configured to superimpose asynchronous noise having a frequency component at which a phase-locked loop circuit becomes asynchronous with a signal input to a phase comparator of the phase-locked loop circuit. Input disconnection detection circuit.

(Supplementary Note 2) In the input disconnection detection circuit of the optical receiver according to Supplementary Note 1, the noise superimposing unit may output the dark current generated by a light receiving element that converts a received optical signal into an electric signal, using the asynchronous current. An input disconnection detection circuit for an optical receiver, wherein the input disconnection detection circuit is superposed as noise on an input signal of the phase comparator.

(Supplementary Note 3) The input disconnection detection circuit of the optical receiver according to Supplementary Note 2, wherein the light receiving element is an avalanche photodiode, and the noise superimposing unit detects a level of an optical reception signal. An input disconnection detection circuit for an optical receiver, comprising: a detection circuit; and a reverse bias control circuit that controls a reverse bias value applied to the avalanche photodiode according to a detection result of the level detection circuit.

(Supplementary Note 4) The input disconnection detection circuit of the optical receiver according to supplementary note 1, wherein the noise superimposing unit generates the asynchronous noise using a timing signal generated by the phase locked loop circuit. And an input disconnection detection circuit for an optical receiver, which is superimposed on an input signal of the phase comparator.

(Supplementary Note 5) An input disconnection detection circuit of an optical receiver for detecting an input disconnection of an optical signal based on a synchronous / asynchronous state of a phase locked loop circuit that generates a timing signal using an optical reception signal. An input disconnection detection circuit for an optical receiver, comprising: a sensitivity control unit for adjusting the sensitivity of a phase comparator of a phase locked loop circuit.

(Supplementary Note 6) In the input disconnection detection circuit for an optical receiver according to Supplementary Note 5, the sensitivity control unit may include an offset voltage corresponding to a level of a signal input to the phase comparator. Wherein the offset control circuit increases the offset voltage when the level of the input signal decreases, wherein the offset control circuit increases the offset voltage. circuit.

(Supplementary note 7) The input disconnection detection circuit of the optical receiver according to supplementary note 6, wherein the sensitivity control unit includes a level detection circuit that detects a level of an optical reception signal, and the offset control circuit includes: An input disconnection detection circuit for an optical receiver, wherein an offset voltage is controlled in accordance with a detection result of the level detection circuit.

(Supplementary note 8) An input disconnection detection circuit of an optical receiver for detecting an input disconnection of an optical signal based on a synchronous / asynchronous state of a phase locked loop circuit that generates a timing signal using an optical reception signal, An input disconnection detection circuit for an optical receiver, comprising: a duty control unit configured to control a duty ratio of a signal input to a phase comparator of a phase locked loop circuit.

(Supplementary note 9) The input disconnection detection circuit for an optical receiver according to supplementary note 8, wherein the duty control unit controls a reference voltage applied to an amplifier that amplifies an optical reception signal and sends the amplified signal to the phase comparator. An input disconnection detection circuit for an optical receiver, wherein the reference control circuit increases the reference voltage of the amplifier when the level of a signal input to the phase comparator decreases.

(Supplementary note 10) The input disconnection detection circuit of the optical receiver according to supplementary note 9, wherein the duty control unit includes a level detection circuit that detects a level of an optical reception signal, and the reference control circuit includes: An input disconnection detection circuit for an optical receiver, wherein a reference voltage is controlled according to a detection result of the level detection circuit.

[0061]

As described above, the input disconnection detection circuit of the optical receiver according to the present invention, in the first invention, is provided with a noise superimposing section so that asynchronous noise is superimposed on the input signal of the phase comparator. In the second invention, a sensitivity control unit is provided to adjust the sensitivity of the phase comparator. In the third invention, a duty control unit is provided to control the duty ratio of the input signal of the phase comparator. As a result, when the input of the optical signal is interrupted, the PLL circuit is hardly erroneously synchronized due to the synchronization noise and becomes in an asynchronous state. Therefore, it is necessary to accurately detect the optical signal input interruption based on the synchronous / asynchronous state of the PLL circuit. Becomes possible. Also, by adjusting the settings of the level of the asynchronous noise, the sensitivity of the phase comparator, and the duty ratio,
It is also possible to appropriately set the input light level at which the input disconnection detection alarm signal is issued.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first basic configuration of an input disconnection detection circuit of an optical receiver according to the present invention.

FIG. 2 is a block diagram showing a modification of the first basic configuration shown in FIG.

FIG. 3 is a block diagram illustrating a configuration of an embodiment 1-1 of an optical receiver to which a first basic configuration of the present invention has been applied.

FIG. 4 is a block diagram showing a modification of the embodiment 1-1 shown in FIG. 3;

FIG. 5 is a block diagram showing a configuration of Embodiment 1-2 of the optical receiver to which the first basic configuration of the present invention is applied.

FIG. 6 is a block diagram showing a modification of the embodiment 1-2 shown in FIG.

FIG. 7 is a block diagram showing a modification of the circuit configuration shown in FIG. 6;

FIG. 8 is a block diagram showing a second basic configuration of the input disconnection detection circuit of the optical receiver according to the present invention.

9 is a block diagram showing a modification of the second basic configuration shown in FIG.

FIG. 10 is a block diagram showing a configuration of an optical receiver according to Embodiment 2-1 to which the second basic configuration of the present invention is applied.

FIG. 11 is a diagram illustrating a change in effective amplitude due to the application of an offset voltage in the embodiment 2-1.

FIG. 12 is a block diagram showing a modification of the embodiment 2-1 shown in FIG.

FIG. 13 is a block diagram illustrating a configuration of an embodiment 2-2 of an optical receiver to which the second basic configuration of the present invention has been applied.

FIG. 14 is a block diagram showing a modification of the embodiment 2-2 shown in FIG.

FIG. 15 is a block diagram showing a third basic configuration of the input disconnection detection circuit of the optical receiver according to the present invention.

FIG. 16 is a diagram illustrating a change in spectrum due to duty ratio control in the third basic configuration of the present invention.

FIG. 17 is a block diagram showing a modification of the third basic configuration shown in FIG.

FIG. 18 is a block diagram illustrating a configuration of an optical receiver according to Embodiment 3-1 to which the third basic configuration of the present invention is applied.

FIG. 19 is a block diagram showing a modification of the embodiment 3-1 shown in FIG.

FIG. 20 is a block diagram illustrating a configuration of an optical receiver according to Embodiment 3-2 to which the third basic configuration of the present invention is applied.

FIG. 21 is a block diagram showing a modification of the embodiment 3-2 shown in FIG.

FIG. 22 is a block diagram showing a configuration of a conventional input disconnection detection circuit of an optical receiver.

[Explanation of symbols]

 Reference Signs List 1 light receiving element 2 preamplifier 3 main amplifier 4, 4 'limit amplifier 5 phase comparator 6 charge pump 7 low pass filter (LPF) 8 voltage controlled oscillator (VCO) 9 flip-flop (F / F) 10 lock detector 11 input disconnection detection Device 20 noise superimposing unit 21, 36, 42 level detection circuit 22 reverse bias control circuit 23 amplifier 30 sensitivity control unit 31 offset control circuit 32, 33 resistor 34, 35 capacitor 40 duty control unit 41 variable power supply 43 reference control circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04B 10/26 H04B 9/00 B 10/14 Y 10/04 K 10/06 H04L 7/02 B 10 / 08 H04L 7/033 25/02 301 303 (72) Inventor Kazuhiro Suzuki 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Japan Fujitsu Digital Technology Limited In-house (72) Inventor Tomoyuki Otsuka Nakahara, Kawasaki-shi, Kanagawa 4-1-1, Kamikodanaka-ku, Fujitsu Co., Ltd. (72) Inventor Hiroshi Yamada 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture F-term within Fujitsu Limited (reference) 5J106 AA04 BB01 CC02 CC21 CC41 DD32 DD48 EE06 EE10 FF06 GG04 KK12 KK18 KK23 KK30 5K002 AA03 DA05 EA05 5K029 CC04 HH26 KK12 5K047 BB02 GG11 KK05 KK12 KK17 MM46 MM63

Claims (5)

[Claims] 1. An input disconnection detection circuit for an optical receiver for detecting an input disconnection of an optical signal based on a synchronous / asynchronous state of a phase locked loop circuit that generates a timing signal using an optical reception signal. An optical receiver, comprising: a noise superimposing unit configured to superimpose asynchronous noise having a frequency component at which a loop circuit is asynchronous to a signal input to a phase comparator of the phase-locked loop circuit. Input disconnection detection circuit. 2. An input disconnection detection circuit of an optical receiver for detecting an input disconnection of an optical signal based on a synchronous / asynchronous state of a phase locked loop circuit for generating a timing signal using an optical reception signal, An input disconnection detection circuit for an optical receiver, comprising a sensitivity control unit for adjusting the sensitivity of a phase comparator of a loop circuit. 3. The input disconnection detection circuit for an optical receiver according to claim 2, wherein said sensitivity control unit outputs an offset voltage corresponding to a level of a signal input to said phase comparator. Wherein the offset control circuit increases the offset voltage when the level of the input signal decreases, wherein the offset control circuit increases the offset voltage. circuit. 4. An input disconnection detection circuit for an optical receiver for detecting an input disconnection of an optical signal based on a synchronous / asynchronous state of a phase locked loop circuit for generating a timing signal using an optical reception signal, An input disconnection detection circuit for an optical receiver, comprising: a duty control unit configured to control a duty ratio of a signal input to a phase comparator of a loop circuit. 5. The input disconnection detection circuit of an optical receiver according to claim 4, wherein the duty control unit controls a reference voltage applied to an amplifier that amplifies an optical reception signal and sends the amplified signal to the phase comparator. An input disconnection detection circuit for an optical receiver, comprising a reference control circuit, wherein the reference control circuit increases a reference voltage of the amplifier when a level of a signal input to the phase comparator decreases.