JP2004222325A - Phase frequency synchronizing circuit, synchronism judging circuit and photo-detector - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase frequency synchronizing circuit for shortening the time from an asynchronous state to synchronism without unstably operating the phase frequency synchronizing circuit when switching from a frequency-locked loop to a phase-locked loop. <P>SOLUTION: The phase frequency synchronizing circuit is composed of a phase comparator 10 for outputting a voltage corresponding to a phase difference of a clock with an input signal as a reference, a frequency comparator 20 for judging a level of a frequency of a clock with a transmission rate of the input signal as a reference and outputting a binary signal, a synchronism discriminator 30 for judging synchronism of a phase and a frequency, a first switch which receives an output of the phase comparator 10, is closed when the synchronism discriminator 30 discriminates synchronism and is opened when the asynchronous state is judged, a second switch which receives an output of the frequency comparator 20, is opened when the synchronism discriminator 30 judges synchronism and is closed when the asynchronous state is judged, a loop filter 40 which receives an output of the first switch and an output of the second switch, and a voltage controlled oscillator 50 which oscillates on the basis of an output of the loop filter 40. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to an optical transmission system, and particularly to a phase locked loop used for optical fiber transmission.

  In an optical transmission system, a light receiving signal is photoelectrically converted by a light receiving element and converted into an electric signal. The converted NRZ code data obtained by equivalently amplifying the converted electric signal has a small jitter when the optical reception level is large, increases with a decrease in the optical reception level, and has a noise when there is no optical signal. The output is equivalent to infinite jitter. In addition, pulse width distortion occurs in this data due to the optical transmitting circuit and the optical receiving circuit.

  FIG. 1 shows a configuration of a related phase frequency synchronizing circuit for generating a clock signal synchronized with data from such a data signal. The phase comparator 10 outputs a voltage having a peak value or a pulse width according to the phase difference between the input data and the clock signal. The frequency comparator 20 outputs the magnitude of the frequency of the clock signal based on the transmission speed of the input data, and does not output the magnitude of the frequency when the input data and the clock signal are synchronized and within a predetermined phase difference. The output of the phase comparator 10 and the output of the frequency comparator 20 are input to the loop filter 40 via the superposition unit 80. A VCO (VCO) 50 varies the oscillation frequency based on the output of the loop filter 40, outputs a clock signal, and synchronizes input data with the clock signal. Examples of the phase frequency synchronization circuit having this configuration include 1992 IEEE International Solid-State Circuits Conference p. It is described in JP-A-6-216766 (Patent Document 1).

  Also, in a file device using a disk, there is a fluctuation of about 1% of the data speed due to the uneven rotation of the disk, and the data signal from the file device has a jitter and pulse width in view of the data signal from the optical receiving circuit. Small distortion. FIG. 2 shows a configuration of a related phase frequency synchronizing circuit for generating a clock signal synchronized with data from such a data signal. The first phase comparator 10-1 outputs a voltage having a pulse width according to the phase difference between the input data and the clock signal. The frequency comparator 20 compares the input data with the clock signal and determines whether the clock frequency is higher or lower than the data frequency by detecting a state where the mark length limit specified in the data is not exceeded. And output.

  The second phase comparator 10-2 outputs a voltage having a pulse width corresponding to the phase difference between the input and the clock signal, with all of the phase difference between the input and the clock signal as a phase advance or a phase delay. The second phase comparator 10-2 receives the input data, the clock signal, and the output of the frequency comparator 20 as inputs, and receives either the advance or the delay of the phase difference between the input data and the clock signal according to the output of the frequency comparator 20. Outputs the phase difference. The synchronization determiner compares the input data with the clock signal and detects a state in which the mark length defined by the data is out of the limit, thereby determining whether the data is synchronous or asynchronous. The switch 1 is located between the output of the first phase comparator and the first loop filter 40-1. The switch 1 closes to the synchronization signal of the output of the synchronization determiner and opens by the asynchronous signal. The switch 1 is located between the output of the second phase comparator and the second loop filter 40-2, closes to the asynchronous signal of the output of the synchronization determiner, and opens by the synchronous signal. The first loop filter 40-1 and the second loop filter 40-2 are input to the VCO 50 via an adder. The VCO 50 varies the oscillation frequency based on the output of the adder, outputs a clock signal, and synchronizes the input data with the clock signal. A phase frequency synchronizing circuit having this configuration is described in Japanese Patent Application Laid-Open No. 9-284269 (Patent Document 2).

JP-A-6-216766 JP-A-9-284269 1992 IEEE International Solid-State Circuits Conference p.162 `` TP10.3: A 8Gb / s Si Bipolar Phase and Frequency Detector IC for Clock Extraction ''

  In the phase frequency synchronization circuit of FIG. 1, the loop filter constant is determined by a loop characteristic including the phase comparator 10, the loop filter 40, and the VCO 50 in a synchronized state. In the asynchronous state, the loop includes the frequency comparator 20, the loop filter 40, and the VCO 50. However, since a loop filter constant corresponding to the asynchronous state cannot be selected, the time from the asynchronous state to the synchronization becomes long.

  In the phase frequency synchronization circuit of FIG. 2, consider a state in which the data and clock frequencies approach each other and the synchronization determination circuit 30 outputs a synchronization determination signal from an asynchronous state in which the switch 1 is open and the switch 2 is closed. When the synchronization determination signal is output, the output of the adder obtained by adding the first loop filter output and the second loop filter output approaches a predetermined value in view of the oscillation frequency of the VCO 50, and the first phase comparator output It is assumed that there is a difference between the voltage levels of the first and second loop filter outputs. When the switch 1 is closed and the switch 2 is opened, a sharp change occurs in the output of the adder 90 due to the difference between the voltage level of the output of the first phase comparator 10-1 and the voltage level of the output of the first loop filter 40-1. The phase frequency synchronization circuit may be unstable. Therefore, the phase frequency synchronization circuit of FIG. 2 includes two loop filters and can individually set the frequency pull-in characteristic and the phase pull-in characteristic. However, the phase frequency lock circuit is unstable when switching from the frequency pull-in mode to the phase pull-in mode. There is a problem.

In FIG. 1, a case is considered in which data having large jitter obtained by equivalently amplifying a weak optical signal and binarizing the same is input to a phase frequency synchronization circuit. Even when the phase-frequency synchronization circuit of FIG. 1 is in phase synchronization, the input jitter instantaneously exceeds a predetermined phase difference, the frequency comparator 10 operates, and there is a problem that the clock jitter instantaneously increases. . The phase frequency synchronization circuit of FIG. 2 has a problem that when the input jitter instantaneously exceeds a predetermined phase difference, the synchronization determiner 30 erroneously determines that it is asynchronous, switches from the phase synchronization mode to the frequency synchronization mode, and increases the jitter of the clock signal. is there. If a phase frequency synchronizing circuit having the characteristic of increasing the jitter of the clock signal is used in the optical receiving circuit, there is a problem that the error rate sharply increases.
In general, when input data is NRZ code and has pulse width distortion, a phase for outputting a voltage having a peak value or a pulse width according to a phase difference of a clock signal with reference to both rising and falling edges of the input data. The comparator has a problem of outputting voltages having different binary peak values or pulse widths at random periods. In the loop configuration of the phase comparison mode including the phase comparator, the filter, and the VCO, when the phase comparator outputs a voltage having a different binary crest value or a pulse width in a random cycle, the random number of the phase comparator output in the loop band is reduced. The component causes an increase in clock jitter. In a loop configuration consisting of a frequency comparator, a filter, and a VCO, if the phase comparator outputs a different binary peak value or voltage of a pulse width in a random cycle, if the frequency comparison determination interval is an integral multiple of the input data width, The accuracy of the frequency comparison determination is reduced. If the frequency cannot be pulled in the frequency synchronization mode until the frequency that can be pulled in the phase synchronization mode, the phase frequency synchronization circuit has a problem of erroneous synchronization.

  As described above, the object of the present invention is to provide a phase locked loop configuration including a phase comparator, a filter, and a VCO in a synchronous state, and a frequency locked loop configuration including a frequency comparator, a filter, and a VCO in an asynchronous state synchronization. An object of the present invention is to provide a phase frequency synchronizing circuit for shortening the time from the asynchronous state to the synchronization without causing the phase frequency synchronizing circuit to perform unstable operation when switching to the synchronous loop.

  Another object of the present invention is to determine that the output of the synchronization determiner is synchronized when the input data can perform a synchronous operation in the phase comparison mode of the phase frequency synchronization circuit but momentarily exceeds a predetermined phase difference. Even if the input jitter increases and the frequency comparator operates instantaneously, the output of the frequency comparator is not transmitted to the loop filter and the synchronous operation is performed in the phase comparison mode so that the clock jitter does not increase instantaneously. It is to provide.

  Another object of the present invention is to prevent an increase in jitter due to a random component of an NRZ code when input data has a pulse width distortion in an NRZ code, and to prevent a frequency comparison interval when the input data has a pulse width distortion in an NRZ code. An object of the present invention is to provide a phase frequency synchronizing circuit which becomes an integral multiple of input data and can prevent a decrease in frequency comparison accuracy of a frequency comparator.

  In order to solve the above-mentioned problems, a phase comparator that receives input data and a clock signal and outputs a voltage having a peak value or a pulse width according to a phase difference of a clock signal with reference to the input data; A frequency comparator that outputs a signal and outputs the magnitude of the frequency of the clock signal based on the transmission speed of the input data, a synchronization determiner that performs a phase and frequency synchronization determination by using the input data and the clock signal as inputs, A switch 1 that receives the output of the phase comparator as input and closes when the synchronization determiner determines that it is synchronous and opens when it determines that it is asynchronous, and opens and asynchronously when it receives the output of the frequency comparator and determines that the synchronization determiner is synchronous Switch 2, which is closed when determined, a loop filter having switch 1 output and switch 2 output as input, and a frequency based on the loop filter output. Variable to be characterized by providing a VCO that outputs a clock signal.

  According to the present invention, a phase locked loop configuration including a phase comparator, a filter, and a VCO is provided. In an asynchronous state, a frequency locked loop configuration including a frequency comparator, a filter, and a VCO is provided. There is an effect that the time from the asynchronous state to the synchronization can be shortened without causing the frequency synchronization circuit to perform an unstable operation.

  Further, according to the present invention, it is possible to perform a synchronous operation in the phase comparison mode of the phase frequency synchronization circuit, but when the input data has a momentary jitter exceeding a predetermined phase difference, it is determined that the output of the synchronization determiner is synchronized. As a result, even if the input jitter increases and the frequency comparator operates instantaneously, the output of the frequency comparator is not transmitted to the loop filter, the synchronous operation is performed in the phase comparison mode, and the clock jitter does not increase instantaneously.

  Further, according to the present invention, when the input data is an NRZ code and has a pulse width distortion, the phase difference between the input data detected by the phase comparator and the clock signal does not change depending on the presence or absence of the pulse width distortion.

  Further, according to the present invention, in the synchronized state, the loop filter formed by the series connection of the resistor and the capacitor has the effect that the voltage generated at the resistance of the loop filter does not change due to the capacitor terminal voltage of the loop filter and the high-frequency loop characteristic is constant. There is.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 3 shows an embodiment of the phase frequency synchronization circuit according to the present invention.

  The phase frequency synchronizing circuit according to the present invention includes a phase comparator 10 which receives input data and a clock signal, and outputs a voltage having a peak value or a pulse width according to a phase difference between the clock signals with reference to the input data; And a clock signal, and a frequency comparator 20 that outputs the magnitude of the frequency of the clock signal with reference to the transmission speed of the input data, and a synchronization determination that receives the input data and the clock signal and performs a phase and frequency synchronization determination. And a switch 1 that receives the output of the phase comparator 10 as an input and closes when the synchronization determiner 30 determines that the signal is synchronous and opens when it determines that the signal is not synchronous. Switch 2 that opens when it is determined to be synchronous and closes when it is determined to be asynchronous, and a loop filter 4 that receives the output of switch 1 and the output of switch 2 When, and a VCO50 for outputting a clock signal by varying the frequency based on the output of the loop filter 40.

  The synchronization determiner 30 determines whether the input data and the clock signal as the VCO output are synchronous or asynchronous. When the synchronization is determined, SW1 is closed and SW2 is opened, and a loop is formed by the phase comparator 10, a loop filter including the resistor R1 and the capacitor C1, and the VCO 50. If it is determined to be asynchronous, SW1 is opened and SW2 is closed, and a loop is constituted by the frequency comparator 20, a loop filter constituted by the resistor R2 and the capacitor C1, and the VCO 50. Even if the input jitter increases and the frequency comparator 20 operates, if the synchronization determiner 30 determines that synchronization is achieved, the frequency comparator 20 goes out of the loop to prevent an increase in clock jitter. In the asynchronous state, the phase comparator 10 that operates unstable is out of the loop, and therefore does not erroneously synchronize. Moreover, since the loop filter characteristic corresponding to the asynchronous state can be realized by the resistor R2 while maintaining the filter characteristic in the synchronous state, the optimum characteristic in which the time from the asynchronous state to the synchronization is shortened can be realized.

  FIG. 4 shows an embodiment of the synchronization determiner using the present invention.

  The synchronization determiner 30 according to the present invention includes a 90 ° phase shifter 31 that shifts the phase of a clock signal by 90 °, and a clock signal position based on input data, which is input data and an output of the 90 ° phase shifter 31. A second phase comparator 32 which outputs a high level when the phase difference is between -90 ° and + 90 °, and outputs a low level when the phase difference of the clock signal is between -180 ° and -90 ° or between + 90 ° and + 180 °. And a low-pass filter 33 having a predetermined band with the output of the second phase comparator 32 as an input, and a high level and a low level of the output of the second phase comparator 32 with the output of the low-pass filter 33 as an input. And a comparator 35 with a hysteresis in which a threshold value is set between a middle point and a high level.

  Next, a detailed operation of the synchronization determiner 30 according to the present invention will be described.

  The second phase comparator 32 outputs a voltage having a peak value corresponding to the phase difference between the input data and the output of the phase shifter 31 which is a clock signal having a phase shift of 90 °, and the phase difference between the input data and the clock signal is 0. In the case of, the maximum value (or minimum value, hereinafter, the case of the maximum value is described) is output. On the other hand, when a phase difference occurs between the input data and the clock signal, the output of the second phase comparator 32 becomes a beat signal having a phase corresponding to the phase difference between the input data transmission speed and the clock signal frequency.

  The output of the second phase comparator 32 is input to a comparator with hysteresis 35 via a low-pass filter 33. The threshold value of the comparator with hysteresis 35 is set near 0.75 when the high level is set to 1 based on the low level of the output of the second phase comparator 32 as 0. If the phase difference between the input data and the clock signal is larger as the beat signal becomes equal to or more than the band of the low-pass filter 33, the output of the low-pass filter 33 becomes close to the level of 0.5, and the output of the comparator 35 with hysteresis becomes , And outputs the asynchronous determination. When the frequency of the input data and the frequency of the clock signal match, the voltage of the second phase comparator 32 becomes near the maximum value, the output of the low-pass filter 33 becomes near the level of 1, and the output of the comparator with hysteresis 35 becomes Output synchronization judgment.

  If the low-pass filter 33 is used, the instantaneous asynchronous signal output from the second phase comparator 32 is suppressed in the case of input data having a large jitter, so that synchronization determination can be correctly performed even when the jitter of the input data increases. it can.

  The comparator with hysteresis 35 prevents the synchronization determination output from fluctuating due to unstable fluctuation of the low-pass filter 33 during the transition from the asynchronous state to the synchronous state.

  At this time, assuming that the jitter transfer band for transmitting the jitter of the loop configuration including the phase comparator 10, the filter 40, and the VCO 50 in the synchronized state is ftc, the transmission speed of the input data and the frequency difference between the clock signal frequency are determined. Is determined to be synchronous when it is π times or less of ftc. The phase pull-in loop including the phase comparator 10, the filter 40, and the VCO 50 controls the transmission data of the input data and the frequency difference between the clock signal frequencies through control for reducing the phase difference between the input data and the clock signal. Assuming that the frequency shift amount of the clock signal frequency is f (t) and the initial value is Δf, f (t) of the phase pull-in loop can be expressed by Expression (1).

  Assuming that the phase shift at time t = 0 → ∞ in Expression (1) is Δθ, Δθ can be expressed by Expression (2).

  When Δθ becomes several π, the output of the phase comparator leads and lags several times, and it is considered that the phase pull-in loop becomes unstable, and Δθ = π is the stable point of the phase pull-in loop.

  Accordingly, Δf = π * ftc, and the phase pull-in loop operates stably when the frequency difference between the input data transmission speed and the clock signal frequency is π times or less of ftc. In the process of synchronizing from the asynchronous state, when the frequency difference between the input data transmission speed and the clock signal frequency is equal to or less than π times ftc, the synchronization determination circuit 30 outputs a synchronization signal, so that the phase pull-in loop performs frequency locking in a stable operation. False synchronization can be prevented.

  FIG. 5 shows a specific configuration example using the present invention. FIG. 6 shows a specific configuration example of the frequency comparator 20 and the synchronization determiner 30 shown in FIG. Note that the VCO 51 has a configuration in which a clock signal and a clock signal whose phase is shifted by 90 ° are output differentially.

  In the phase comparator with switch 11 in FIG. 5, the NAND 1 outputs a voltage having a pulse width corresponding to the phase difference between the input data and the clock signal, and the NAND 2 outputs a fixed pulse only when the output of the NAND 1 is present. The circuit composed of the bipolar transistors T100 to T103 converts the voltage signals of NAND1 and NAND2 into current signals. When there is no phase difference between the input data and the clock signal, the fixed pulse width of the NAND 2 is set so that the average current output of the phase comparator with switch 11 becomes zero. In the MOS transistors M1 and M2, in the synchronous state, the positive phase output of the synchronization determiner 30 becomes high level to operate the phase phase comparator with switch 11, and in the asynchronous state, the positive phase output of the synchronization determiner 30 becomes low level. The output of the phase comparator with switch 11 is stopped. The output of the phase-phase comparator with switch 11 is connected to R1 of the loop filter 40, and the output of the frequency comparator 20 is connected to R2 of the loop filter 40 via the switch SW2. According to this configuration, when synchronized, a loop configuration including the phase-phase comparator with switch 11, the loop filter 40 configured by R1 and C1, and the VCO 51 is provided. When asynchronous, the frequency comparator 20 and the loop configured by R2 and C1 are used. A loop configuration including the filter 40 and the VCO 51 is provided. The average oscillation frequency of the VCO 51 is controlled by the potential of C1, and there is no change in the average oscillation frequency of the VCO 51 before and after the loop switching. Further, since R2 is not included in the loop at the time of synchronization, it can be optimized only by the asynchronous loop characteristics, so that the time from the asynchronous state to the synchronization can be shortened. Further, even in the case of an asynchronous state in which the frequency is shifted so that the phase-comparator with switch 11 malfunctions, erroneous synchronization can be prevented because the phase-phase comparator with switch 11 is not included in the loop.

  FIG. 6 shows a specific configuration example of the frequency comparator 20 and the synchronization determiner 30 shown in FIG. 5, in which the frequency comparator 20 and the second phase comparator 32 used for the synchronization determiner 30 are shared. is there. A case where the clock signal is a binary digital signal and the frequency comparator 20 and the synchronization determiner 30 operate digitally instead of analogly will be described.

  The frequency comparator 20 includes a phase comparator 21, a second phase comparator 32, and a logic circuit 22. The phase comparator 21 and the second phase comparator 32 are flip-flop circuits that hold the level of the data D at the rising edge of the clock T. The phase comparator 21 connects the input data to the clock T of the flip-flop circuit, connects the clock signal to the data D of the flip-flop circuit, and sets the timing of the phase difference 0 between the input data and the clock signal to the state shown in FIG. I do.

  Accordingly, the phase comparator 21 outputs a low level when the phase of the clock signal advances from −π to 0 with respect to the rising edge of the input data, and outputs a low level when the phase of the clock signal lags from 0 to + π. Outputs a high level. Since the second phase comparator 32 connects the input data to the clock T of the flip-flop circuit and connects the 90 ° clock signal to the data D of the flip-flop circuit, the phase of the clock signal is − based on the rising edge of the input data. When the phase difference is as small as 0.5π to + 0.5π, a high level is output. When the phase difference of the clock signal is as large as −π to −0.5π or + 0.5π to + π, a low level is output. .

  FIG. 7C shows a timing chart when the frequency of the clock signal is lower than that of the input data signal. T21 in the logic circuit: the emitter captures the V point of the second phase comparator output Q in FIG. 7c, and T23 in the logic circuit captures the VV point of the second phase comparator output Q in FIG. 7c. The output of the frequency comparator 20 outputs the middle level of the output amplitude when the frequency cannot be determined, and outputs the low level at the point where the clock frequency can be determined to be low. A high level is output at the point where the clock frequency can be determined to be high.

  The synchronization determiner 30 includes a second phase comparator 32, a low frequency band amplifier 34, and a comparator 35 with hysteresis. The output of the second phase comparator 32 in the timing chart shown in FIG. 7C has a pulse corresponding to the frequency difference between the input data signal and the clock signal. When the low-frequency band amplifier 34 has a narrow band, the waveform becomes a solid line, and when the threshold value of the comparator 35 with hysteresis is set as shown by a dashed line, the output of the comparator 35 with hysteresis always becomes a low level during the period on the timing chart. , Indicating an asynchronous state. When the low-frequency band amplifier 34 has a wide band, the waveform shown by the dotted line is generated, and a point where the threshold is equal to or higher than the threshold of the comparator 35 with hysteresis occurs, and the output of the comparator 35 with hysteresis intermittently outputs a high level indicating a synchronous state. The low frequency band amplifier 34 has a function of preventing the synchronization determiner 30 from intermittently outputting a synchronization signal when the frequency difference between the input data signal and the clock signal is large. The low frequency band amplifier 34 also has an effect of suppressing an instantaneous asynchronous signal generated in the second phase comparator 32 in the case of input data having large jitter.

  FIG. 7C shows a case where the input data is repeated 10 times. However, there is a pattern that is erroneously detected when the input data is a random pattern, and it is necessary to perform frequency determination on average. Do. When this circuit is experimentally evaluated when the input data is a random pattern, if the clock signal frequency exceeds near -85 to + 115% based on the input data transmission speed, the circuit is erroneously determined as a frequency comparator. Thus, the frequency range of the clock signal of the VCO 51 is set to -90% to + 110% based on the input data transmission speed.

  FIG. 8 shows another embodiment of the phase frequency synchronization circuit using the present invention. VCO-A, VCO-B and VCO-C have different clock signal frequencies and correspond to different input data rates. Only the VCO selected by the mode selector signal oscillates and forms a phase frequency loop via the selector 60. The current consumption of the VCO not selected by the mode selector signal becomes zero, and there is no increase in power consumption according to the present invention. The present invention is a technique for converting a phase frequency synchronization circuit manufactured for each of several types of input data rates into one type of phase frequency synchronization circuit, and is suitable for IC production of one kind of mass production. The phase frequency synchronization circuit 100 is an example capable of supporting three types of input data rates. In the present invention, the phase frequency synchronization circuit 100 can support the types of input data rates provided with VCOs having different clock signal frequencies.

  FIG. 9 shows an embodiment of an optical receiving circuit using the present invention. An optical receiving circuit is configured by including a light receiving element 200, a preamplifier 300, a post-amplifier 400, and a discriminator 500 in a phase frequency synchronization circuit 100 using the present invention.

  The output of the low-pass filter when the input data and the clock signal are synchronized is the probability of occurrence when the phase difference of the clock signal with respect to the input data is from −180 ° to −90 ° or from + 90 ° to + 180 °. The occurrence probability increases as the jitter of the input data increases. FIG. 10 shows a calculation result of the data error rate obtained by converting the normalized output voltage of the low-pass filter 33 from the jitter of the input data.

  If the threshold value at which the second comparator 71 with hysteresis issues an alarm is set to the normalized value of the second comparator with hysteresis of 0.85 V, and the threshold value at which the alarm is released is set to the normalized value of the second comparator with hysteresis of 0.95 V, , An alarm can be issued and released at a data error rate of 10-1 to 10-3.

Conventionally, when an alarm is generated when the data error rate is 10-1 to 10-3, the alarm function is realized by a method of detecting the signal power of the optical receiving circuit. In the case of an optical reception signal via an optical amplifier, which is a characteristic of recent years, the optical noise power cannot be ignored compared to the noise power generated in the optical reception circuit, and an alarm cannot be correctly generated by the method of detecting the signal power of the optical reception circuit. . With the above setting, an alarm can be generated at a predetermined data error rate even when the optical noise power is not negligible compared to the noise power generated in the optical receiving circuit.

FIG. 3 shows a related phase frequency synchronization circuit block diagram. FIG. 3 shows a related phase frequency synchronization circuit block diagram. 1 shows a block diagram of a phase frequency synchronization circuit using the present invention. 1 shows a block diagram of a synchronization determiner using the present invention. A specific configuration example according to claim 2 using the present invention, wherein a clock signal shifted by 90 ° from a VCO without using a 90 ° phase shifter is extracted from a VCO, and a phase frequency obtained by integrating a frequency comparator and a synchronization determiner is shown. FIG. 3 shows a synchronous circuit diagram. FIG. 6 is a circuit diagram illustrating a specific configuration example of the integrated frequency comparator and synchronization determiner illustrated in FIG. 5. FIG. 8 is a time chart illustrating operations of the synchronization determination circuit and the frequency comparator in FIGS. 5 to 7. 1 shows a block diagram of a phase frequency synchronization circuit using the present invention. 1 shows a block diagram of an optical receiving circuit using the present invention. FIG. 4 is a diagram illustrating a relationship between a normalized filter output voltage of an optical receiving circuit according to the present invention and an error rate of output data.

Explanation of reference numerals

10, 10-1, 10-2: phase comparator, 11: phase comparator with built-in switch,
20 ... frequency comparator,
21 ... phase comparator,
22 ... Logic circuit,
30 ... Synchronization determiner,
31 ... 90 ° phase shifter,
32 ... second phase comparator,
33: low-pass filter; 34: low-frequency band amplifier;
35: comparator with hysteresis,
40, 40-1, 40-2 ... loop filter,
50, 51 ... voltage controlled oscillator (VCO),
60 ... selector,
70 ... Alarm generator,
71 ... second comparator with hysteresis,
80 ... superposition device,
90 ... adder,
100 ... Phase frequency synchronization circuit of the present invention,
200: light receiving element,
300 ... preamplifier,
400 ... post-amplifier,
500 ... discriminator,
C1: capacity,
R1, R2 ... resistance,
SW1, SW2 ... Switch.

Claims (8)

A 90 ° phase shifter for shifting the phase of the clock signal by 90 °;
Input data and the output of the 90 ° phase shifter are input, and when the phase difference of the clock signal with respect to the input data is from −90 ° to + 90 °, a high level is output. A second phase comparator that outputs a low level when is between -180 ° and -90 ° or between + 90 ° and + 180 °,
A low-pass filter having the input of the second phase comparator output and having a predetermined band;
A synchronization determination circuit comprising a comparator having a hysteresis which receives the output of the low-pass filter as an input, and sets a threshold between a high level of the output of the second phase comparator and a high level from a middle point of the low level. The synchronization determination circuit according to claim 1, wherein:
A synchronization determination circuit for determining that the frequency is asynchronous when a difference between the transmission speed of the input data and the frequency of the clock signal is equal to or greater than a predetermined value. The synchronization determination circuit according to claim 2, wherein
The predetermined value is a jitter transfer band of a loop configuration including a phase comparator in a synchronized state, a loop filter, and a VCO included in a phase frequency synchronization circuit provided at a stage preceding the synchronization determination circuit. And a synchronization determination circuit. A light receiving element that receives an optical signal and performs photoelectric conversion,
An amplifier that amplifies the photoelectrically converted signal and outputs the input data;
A phase frequency synchronization circuit that receives the input data as input and outputs the clock signal;
An optical receiver including an input device and a discriminator that discriminates and reproduces the input data and the clock signal,
An optical receiver characterized in that a jitter threshold of input data determined by the second comparator with hysteresis can be set so that a data error rate becomes a predetermined value. A light receiving element that receives an optical signal and performs photoelectric conversion,
An amplifier that amplifies the photoelectrically converted signal and outputs the input data;
A phase frequency synchronization circuit that receives the input data as input and outputs the clock signal;
An optical receiver including an input device and a discriminator that discriminates and reproduces the input data and the clock signal,
An optical receiver characterized in that a jitter threshold value of input data determined by the second comparator with hysteresis is set so that a data error rate is 10 ^-1 to 10 ^-3 . A phase comparator that receives input data and a clock signal and outputs a voltage having a peak value or a pulse width according to a phase difference between the input data and the clock signal based on the input data;
A frequency comparator that receives the input data and the clock signal as input, determines a magnitude of a frequency of the clock signal based on a transmission speed of the input data, and outputs a binary signal;
A synchronization determiner that performs phase and frequency synchronization determination by using the input data and the clock signal as inputs,
A first switch that receives the output of the phase comparator as an input, closes when the synchronization determiner determines that the output is synchronous, and opens when the synchronization determiner determines that the output is asynchronous;
A second switch that receives the output of the frequency comparator as an input, opens when the synchronization determiner determines synchronization, and closes when the synchronization determiner determines asynchronous;
A loop filter having the first switch output and the second switch output as inputs,
And a voltage-controlled oscillator that varies the frequency based on the output of the loop filter and outputs the clock signal.   The phase frequency synchronization circuit according to claim 6, wherein the phase comparator outputs a current having a peak value or a pulse width according to a phase difference between the input data and the clock signal. The voltage-controlled oscillator is provided with a plurality of voltage-controlled oscillators having different oscillation frequencies, operating and not operating by an external mode selector signal with the loop filter output as an input, and the plurality of voltage-controlled oscillators having different oscillation frequencies as inputs. 7. The phase frequency synchronization circuit according to claim 6, further comprising a selector for outputting one clock signal from a voltage controlled oscillator having a different oscillation frequency depending on a mode selector signal.

Images