JP2014200029A - Communication device, communication system, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a possibility that a buffer to store data received from an asynchronous communication network and transmitted to a synchronous communication network over-flows or under-flows.SOLUTION: A communication device includes: a storage unit that stores data received from a second communication network by communication asynchronous with communication in a first communication network; a transmission unit that reads out the data stored in the storage unit according to a clock signal and transmits it to the first communication network; a detection unit that detects out-of-synchronization of communication with a device receiving data transmitted to the first communication network; a search unit that searches for the upper limit or lower limit of the frequency where the out-of-synchronization is not detected while changing the frequency of the clock signal; and a changing unit that changes the frequency to the upper limit or lower limit according to the amount of data stored in the storage unit.

Description

  The present invention relates to a communication device, a communication system, and a program.

  A device (hereinafter referred to as an “IP converter”) that enables an asynchronous communication network such as an IP network that cannot transmit the clock signal between synchronous communication networks that synchronize communication by transmitting a clock signal. ) Exists.

  For example, one IP converter is installed between one synchronous communication network and an asynchronous communication network, and one IP converter is installed between the other synchronous communication network and the asynchronous communication network. For example, IP packets are transmitted between IP converters via an asynchronous communication network.

  When IP packets are transmitted, even if the transmission side transmits IP packets at regular intervals, the reception side may not always receive IP packets at regular intervals, and there may be fluctuations in the arrival intervals of IP packets. Yes. The IP converter is provided with a reception buffer so that synchronous communication to the synchronous communication network is not interrupted even if such fluctuations occur. The IP converter on the receiving side uses the frequency of the clock signal for reading data from the reception buffer (hereinafter referred to as “buffer data amount”) so that the amount of data in the reception buffer (hereinafter referred to as “buffer data amount”) is stabilized at a predetermined value. “Clock frequency”). Specifically, the IP converter increases the clock frequency when the buffer data amount increases from a predetermined value, and decreases the clock frequency when the buffer data amount decreases from the predetermined value. As a result, one synchronous communication network and the other synchronous communication network can be artificially synchronized. The predetermined value is, for example, a value half the size of the reception buffer (hereinafter referred to as “center value”).

  When the buffer data amount exceeds the center value, the difference between the buffer data amount and the upper limit of the reception buffer is small, so the possibility that the reception buffer overflows is relatively high. It can be said. Similarly, when the buffer data amount is below the center value, it can be said that there is a relatively high possibility that the reception buffer will underflow.

  Since the overflow or underflow of the reception buffer causes a communication error in the synchronous communication network, it is desirable that the state where the buffer data amount deviates from the center value is eliminated early. Therefore, when the buffer data amount exceeds the center value, the clock frequency is changed to the preset maximum value, and when the buffer data amount falls below the center value, the clock frequency is changed to the preset minimum value. Is done. By doing so, the time for the buffer data amount to decrease to the center value or the time for the buffer data amount to increase to the center value can be shortened.

JP 2008-199159 A JP 2012-129677 A

  However, it is difficult to grasp in advance the upper limit or lower limit (maximum allowable input fluctuation amount) of the clock frequency within a range that can be actually allowed by devices connected to the synchronous communication network. Therefore, approximate values are set as the maximum value and the minimum value based on the estimation of the worker who performs the setting operation. The maximum value and the minimum value set by an operator or the like tend to be set on the safe side so as not to be out of the allowable range of devices connected to the synchronous communication network. Specifically, the set maximum value is smaller than the upper limit of the allowable range of the clock frequency of the device connected to the synchronous communication network, and the set minimum value is larger than the lower limit of the allowable range. There is a tendency. Therefore, it can be considered that there is room for improvement in terms of shortening the period in which the buffer data amount deviates from the center value, i.e., reducing the possibility that the reception buffer overflows or underflows.

  Therefore, an object of one aspect is to reduce the possibility that a buffer for storing data received from an asynchronous communication network and transmitted to the synchronous communication network will overflow or underflow.

  In one plan, the communication device stores a data received from the second communication network by communication asynchronous to the communication in the first communication network, and the data stored in the storage unit, Read according to a clock signal, and transmit to the first communication network, a detection unit that detects out-of-synchronization with a device that receives data transmitted to the first communication network, and the clock A search unit that changes the frequency of a signal to search for an upper limit or a lower limit of a frequency at which the loss of synchronization is not detected, and the frequency is set to the upper limit or the lower limit according to the amount of data stored in the storage unit. And a change unit to change to.

  According to one aspect, it is possible to reduce the possibility that a buffer for storing data received from an asynchronous communication network and transmitted to the synchronous communication network will overflow or underflow.

It is a figure which shows the structural example of the communication system in embodiment of this invention. It is a figure which shows the structural example of the hardware of the IP converter in embodiment of this invention. It is a figure which shows the function structural example of the IP converter in embodiment of this invention. It is a figure for demonstrating the outline | summary of the adjustment process of the clock frequency in a 1st case. It is a figure for demonstrating the outline | summary of the adjustment process of the clock frequency in a 2nd case. It is a figure for demonstrating the outline | summary of the adjustment process of the clock frequency in a 3rd case. It is a figure for demonstrating the outline | summary of the adjustment process of the clock frequency in a 4th case. It is a flowchart for demonstrating an example of the process sequence which the IP conversion apparatus of the receiving side performs.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating a configuration example of a communication system according to an embodiment of the present invention. In FIG. 1, legacy devices 10-1 and 10-2 (hereinafter referred to as “legacy device 10” when they are not distinguished from each other) are connected via a synchronous communication network 11-1 or 11-2 constructed with, for example, an optical fiber. Synchronously communicate data. In the present embodiment, synchronous communication refers to communication in which data transmission or reception is synchronized between a data transmission side and a reception side, for example, by a clock signal. However, synchronization may be achieved by means other than the clock signal. As an example of the legacy device 10, voice, 2 Mbps MUX, ITU-T recommendation V. 24, X21, and other devices that perform data communication.

  In FIG. 1, an asynchronous communication network 15 including an IP (Internet Protocol) network 18 is interposed between the synchronous communication networks 11-1 and 11-2. In the present embodiment, asynchronous communication refers to communication asynchronous to the synchronous communication network 11-1 or 11-2. As an example of asynchronous communication, communication such as IP that cannot transmit a clock signal for synchronization used in the synchronous communication network 11-1 or 11-2 or that is not synchronized based on the clock signal can be given. . Note that a communication protocol other than IP may be used in the asynchronous communication network 15.

  An IP conversion device 12-1 is installed between the synchronous communication network 11-1 and the asynchronous communication network 15, and an IP conversion device 12 is provided between the synchronous communication network 11-2 and the asynchronous communication network 15. -2 is installed. The IP conversion apparatuses 12-1 and 12-2 (hereinafter referred to as “IP conversion apparatus 12” when they are not distinguished from each other) execute processing for mediating communication between the legacy devices 10 via the IP network 18. Device.

  Specifically, each IP conversion device 12 sends a legacy network 14-1 or 14-2 to each legacy device 10 of the synchronous communication network 11-1 or 11-2 (hereinafter referred to as “legacy network 14 "). Further, each IP conversion device 12 is connected via the IP network 18 so as to be communicable with the corresponding IP conversion device 12. Each IP conversion device 12 is set with a unique IP address.

  In the present embodiment, it is assumed that the legacy device 10-1 is a data transmission side and the legacy device 10-2 is a data reception side. Therefore, the IP conversion apparatus 12-1 receives the data transmitted from the legacy device 10-1 via the legacy network 14-1. The IP conversion device 12-1 converts the received data into an IP packet format and transmits the data to the IP conversion device 12-2 via the IP network 18. On the other hand, the IP conversion device 12-2 receives an IP packet from the IP network 18. The IP conversion device 12-2 transmits the data included in the received IP packet to the legacy device 10-2 via the legacy network 14-2.

  FIG. 2 is a diagram illustrating a hardware configuration example of the IP conversion apparatus according to the embodiment of the present invention. In FIG. 2, the IP conversion apparatus 12 includes a CPU 36, a RAM 50, a ROM 52, a legacy interface unit 20, an IP interface unit 22, a packet processing unit 24, a variable clock unit 26, and the like that are mutually connected by a bus 48. .

  The ROM 52 stores, for example, a program that causes the IP conversion device 12 to function as each unit shown in FIG. When the IP conversion device 12 is activated, the program stored in the ROM 52 is read into the RAM 50. The program read into the RAM 50 causes the CPU 36 to execute the processing implemented in the program.

  The legacy interface unit 20 is a circuit that receives data from the legacy network 14 or transmits data to the legacy network 14. The IP interface unit 22 is a circuit that receives an IP packet from the IP network 18 or transmits an IP packet to the IP network 18. The packet processing unit 24 is a circuit that performs processing related to transmitted or received IP packets. The variable clock unit 26 is a circuit that generates a clock signal that defines a read cycle of data from the reception buffer 502. The frequency (hereinafter referred to as “clock frequency”) of the clock signal generated by the variable clock unit 26 of the IP converter 12-1 on the data transmission side is fixed to a preset value. The clock frequency of the variable clock unit 26 of the IP converter 12-2 on the data receiving side is the amount of data stored in the reception buffer 502 (hereinafter referred to as “buffer data amount”), for example, the reception buffer 502. It is adjusted so as to be stable to half of the capacity (hereinafter referred to as “center value”). Specifically, when the buffer data amount exceeds the center value, the clock frequency increases, and when the buffer data amount falls below the center value, the clock frequency decreases.

  FIG. 3 is a diagram illustrating a functional configuration example of the IP conversion device according to the embodiment of the present invention. In FIG. 3, the same parts as those of FIG. In FIG. 3, the IP conversion apparatus 12 includes a transmission buffer 501 and a reception buffer 502. Each of these buffers can be realized using the RAM 50, for example. The IP converter 12 also includes a packet assembling unit 241, a packet disassembling unit 242, a receiving buffer monitoring unit 461, a clock fluctuation amount searching unit 462, and the like. The packet assembling unit 241 and the packet disassembling unit 242 are hardware constituting the packet processing unit 24. The reception buffer monitoring unit 461 and the clock fluctuation amount searching unit 462 are realized by processing that the program causes the CPU 46 to execute.

  The transmission buffer 501 stores data transmitted from the legacy device 10 via the legacy network 14 and received by the legacy interface unit 20 (hereinafter, data communicated in the legacy network 14 is referred to as “synchronous communication data”). It is a buffer.

  The packet assembling unit 241 generates an IP packet that stores the data stored in the transmission buffer 501. The IP packet generated by the packet assembly unit 241 is transmitted to the IP network 18 by the IP interface unit 22.

  The packet decomposing unit 242 decomposes the IP packet received by the IP interface unit 22 and extracts data transmitted from the legacy device 10 from the IP packet. The reception buffer 502 stores the data extracted by the packet decomposition unit 242. The data stored in the reception buffer 502 is read by the legacy interface unit 20 and transmitted to the legacy device 10 via the legacy network 14. Data read processing from the reception buffer 502 by the legacy interface unit 20 is synchronized with the frequency of the clock signal generated by the variable clock unit 26.

  The reception buffer monitoring unit 461 monitors whether or not the buffer data amount has reached the upper limit value, the center value, or the lower limit value of the reception buffer 502, and adjusts the variable clock so that the buffer data amount is stabilized at the center value. The clock frequency of the unit 26 is adjusted. However, the clock frequency of the IP converter 12-1 on the transmission side is fixed to a preset fixed value.

  The clock fluctuation amount search unit 462 searches for the upper limit or lower limit (maximum input allowable fluctuation amount) of the allowable range of the clock frequency in the legacy device 10 connected to the IP conversion apparatus 12 via the legacy network 14. The upper limit or lower limit is the maximum value or the minimum value of the frequency of the clock signal by the variable clock unit 26.

  In FIG. 3, the legacy interface unit 20 includes an alarm monitoring unit 201. The alarm monitoring unit 201 monitors the occurrence of loss of synchronization in synchronous communication with the legacy device 10 via the legacy network 14. The loss of synchronization means that the legacy device 10 is synchronized with the synchronous communication data transmitted from the legacy interface unit 20 because the clock frequency of the variable clock unit 26 is outside the allowable range of the legacy device 10. A state that cannot be taken. In other words, it can be said that the state in which the loss of synchronization does not occur is a state in which the clock frequency by the variable clock unit 26 is within the allowable range of the legacy device 10.

  Next, an overview of the clock frequency adjustment processing of the variable clock unit 26 by the receiving-side IP conversion device 12-2 will be described. In addition, since the clock frequency is fixed for the IP conversion device 12-1 on the transmission side, the adjustment process need not be performed.

  FIG. 4 is a diagram for explaining the outline of the clock frequency adjustment process in the first case. In FIG. 4, the horizontal axis of the graph (1) is time, and the vertical axis is the amount of buffer data. On the vertical axis of (1), the upper limit value Cmax is the upper limit value of the buffer fluctuation allowable range of the reception buffer 502. The lower limit value Cmin is a lower limit value of the buffer allowable fluctuation range of the reception buffer 502. The center value Co is synonymous with the center value described above, and is a median value between the upper limit value Cmax and the lower limit value Cmin.

  On the other hand, the horizontal axis of the graph of (2) is time, and is synchronized with the horizontal axis of (1). The vertical axis of (2) is the clock frequency of the variable clock unit 26. In the vertical axis of (2), fo is a reference frequency (hereinafter referred to as “reference frequency fo”). fa is an initial set value of the upper limit of the fluctuation amount of the clock frequency on the + side with respect to the reference frequency fo (hereinafter referred to as “+ side initial set frequency fluctuation amount fa”). fb is an initial set value (hereinafter referred to as “−side initial set frequency fluctuation amount fb”) of the upper limit of the fluctuation amount of the − side clock frequency with respect to the reference frequency fo. For example, the absolute value of the + side initial set frequency fluctuation amount fa based on the reference frequency fo and the absolute value of the − side initial set frequency fluctuation amount fb are the same. The absolute value based on the reference frequency fo refers to the absolute value of the difference from the reference frequency fo. Hereinafter, the absolute value of the frequency means an absolute value based on the reference frequency fo. The + side initial set frequency fluctuation amount fa, the − side initial set frequency fluctuation amount fb, and the reference frequency fo are values set in the reception buffer monitoring unit 461 as set values at the stage of initial setting.

  On the other hand, fc + is the maximum allowable input fluctuation amount on the + side of the legacy device 10-2 on the receiving side (hereinafter referred to as “+ maximum allowable input fluctuation amount fc +”). fc− is the maximum allowable input variation on the − + side of the legacy device 10-2 (hereinafter referred to as “−maximum allowable input variation fc−”). That is, the + side maximum allowable input variation fc + and the −side maximum allowable input variation fc− are unknown values at the time of initial setting, and are values searched by the clock variation search unit 462 after the start of communication.

  In the first case, the buffer data amount tends to increase in a state where the clock frequency of the variable clock unit 26 is set to the reference frequency fo. In the first case, the absolute values of the + side initial set frequency fluctuation amount fa and the − side initial set frequency fluctuation amount fb are the reference values of the + side maximum input allowable fluctuation amount fc + and the − side maximum input allowable fluctuation amount fc−. It is set smaller than the absolute value of the frequency fo (that is, on the safe side).

  In the period from time t0 to t1, the clock frequency of the variable clock unit 26 is the reference frequency fo. Therefore, during this period, the buffer data amount increases and reaches the upper limit value Cmax at time t1. The reception buffer monitoring unit 461 detects that the buffer data amount has reached the upper limit value Cmax. Accordingly, the reception buffer monitoring unit 461 sets the clock frequency to the + side initial set frequency fluctuation amount fa in order to avoid overflow of the reception buffer 502. As a result, the buffer data amount starts to decrease.

  Here, in the first case, the + side initial set frequency fluctuation amount fa is smaller than the + side maximum input allowable fluctuation amount fc +. Therefore, even after the clock frequency is changed to the + side initial set frequency fluctuation amount fa, loss of synchronization does not occur. Therefore, the clock fluctuation amount search unit 462 continuously increases the clock frequency in order to search for the + side maximum input allowable fluctuation amount fc +. For example, the clock frequency increases by α ppm at regular time intervals.

  When the alarm monitoring unit 201 detects a loss of synchronization in the process of continuously increasing the clock frequency, the clock fluctuation amount search unit 462 causes the clock immediately before the clock frequency when the loss of synchronization is detected (time t2). For example, the frequency is stored in the RAM 50 as the + side maximum allowable input fluctuation amount fc +. The clock frequency immediately before the clock frequency when the out-of-synchronization is detected is a clock frequency that is smaller than the clock frequency when the out-of-synchronization is detected by a certain width α. That is, the clock frequency immediately before the clock frequency when the loss of synchronization is detected is the maximum clock frequency until the loss of synchronization is detected. Note that the alarm monitoring unit 201 detects loss of synchronization based on, for example, a response from the legacy device 10-2.

  Thereafter, the clock frequency of the variable clock unit 26 is fixed to the clock frequency immediately before the clock frequency when the synchronization loss is detected. Subsequently, when the buffer data amount decreases to the center value Co at time t3, the reception buffer monitoring unit 461 decreases the clock frequency to the reference frequency fo in order to avoid further decrease of the buffer data amount. As a result, the buffer data amount starts increasing again.

  Thereafter, when the buffer data amount reaches the upper limit value Cmax at time t4, the reception buffer monitoring unit 461 sets the clock frequency to the + side maximum allowable input variation amount fc + stored in the RAM 50. As a result, the buffer data amount decreases from time t4 to time t5. Here, the clock frequency in the period from time t4 to time t5 is a value close to the maximum clock frequency in the allowable range of the legacy device 10-2. Therefore, the period during which the buffer data amount decreases to the center value Co (period from time t4 to time t5) can be shortened as compared with the case where the clock frequency is set to the + side initial set frequency fluctuation amount fa. .

  Thereafter, the same control as that at time t4 and t5 is repeatedly performed. That is, when the buffer data amount reaches the upper limit value Cmax, the clock frequency is set to the + side maximum allowable input variation amount fc + (t6). Thereafter, when the buffer data amount decreases to the center value Co, the clock frequency is set to the reference frequency fo (t7).

  However, the lowering destination of the clock frequency at time t5 may be a frequency higher than the reference frequency fo (for example, the reference frequency fo + β). If the buffer data amount still increases and reaches the upper limit value Cmax, the lowering destination of the clock frequency may be a larger value (for example, the reference frequency fo + 2β). As a result of repeating such control, when the buffer data amount is stabilized near the center value Co, the clock frequency at that time may be set to the reference frequency fo thereafter. By doing so, the period in which the buffer data amount is near the center value Co can be further extended.

  Next, FIG. 5 is a diagram for explaining the outline of the clock frequency adjustment process in the second case. In FIG. 5, the way of viewing the graphs (1) and (2) is the same as that in FIG.

  In the second case, the buffer data amount tends to decrease in a state where the clock frequency of the variable clock unit 26 is set to the reference frequency fo. In the second case, the absolute values of the + side initial set frequency fluctuation amount fa and the −side initial set frequency fluctuation amount fb are the absolute values of the + side maximum input allowable fluctuation amount fc + and the −side maximum input allowable fluctuation amount fc−. It is set smaller than the value (that is, on the safe side).

  In the period from time t0 to t1, the clock frequency of the variable clock unit 26 is the reference frequency fo. Therefore, during this period, the amount of buffer data decreases and reaches the lower limit Cmin at time t1. The reception buffer monitoring unit 461 detects that the buffer data amount has reached the lower limit value Cmin. Therefore, the reception buffer monitoring unit 461 sets the clock frequency to the negative side initial set frequency fluctuation amount fb in order to avoid underflow. As a result, the buffer data amount starts to increase.

  Here, in the second case, the −side initial set frequency fluctuation amount fb is larger than the −side maximum input allowable fluctuation amount fc−. Accordingly, no loss of synchronization occurs even after the clock frequency is changed to the negative side initial set frequency fluctuation amount fb. Therefore, the clock fluctuation amount search unit 462 continuously decreases the clock frequency in order to search for the −side maximum allowable input fluctuation amount fc−. For example, the clock frequency decreases by α ppm at regular time intervals.

  In the process in which the clock frequency continuously decreases, when the alarm monitoring unit 201 detects loss of synchronization, the clock fluctuation amount searching unit 462 causes the clock immediately before the clock frequency when the loss of synchronization is detected (time t2). For example, the frequency is stored in the RAM 50 as the −side maximum allowable input fluctuation amount fc−. The clock frequency immediately before the clock frequency when the out-of-synchronization is detected is a clock frequency larger by a certain width α than the clock frequency when the out-of-synchronization is detected. That is, the clock frequency immediately before the clock frequency when the loss of synchronization is detected is the minimum clock frequency until the loss of synchronization is detected.

  Thereafter, the clock frequency of the variable clock unit 26 is fixed to the clock frequency immediately before the clock frequency when the synchronization loss is detected. Subsequently, when the buffer data amount increases to the center value Co at time t3, the reception buffer monitoring unit 461 increases the clock frequency to the reference frequency fo in order to avoid a further increase in the buffer data amount. As a result, the buffer data amount starts to decrease again.

  After that, when the buffer data amount reaches the lower limit value Cmin at time t4, the reception buffer monitoring unit 461 sets the clock frequency to the −side maximum allowable input fluctuation amount fc− stored in the RAM 50. As a result, the buffer data amount increases from time t4 to time t5. Here, the clock frequency in the period from time t4 to time t5 is a value close to the minimum clock frequency in the allowable range of the legacy device 10-2. Therefore, the period during which the buffer data amount increases to the center value Co (period from time t4 to time t5) can be shortened compared to the case where the clock frequency is set to the negative side initial set frequency fluctuation amount fb. .

  Thereafter, the same control as that at time t4 and t5 is repeatedly performed. That is, when the buffer data amount reaches the lower limit value Cmin, the clock frequency is set to the −side maximum allowable input fluctuation amount fc− (t6). Thereafter, when the buffer data amount increases to the center value Co, the clock frequency is set to the reference frequency fo (t7).

  However, the increase destination of the clock frequency at time t5 may be a frequency smaller than the reference frequency fo (for example, reference frequency fo−β). If the buffer data amount still decreases and reaches the lower limit value Cmin, the lowering destination of the clock frequency may be a smaller value (for example, the reference frequency fo-2β). As a result of repeating such control, when the buffer data amount is stabilized near the center value Co, the clock frequency at that time may be set to the reference frequency fo thereafter. By doing so, the period in which the buffer data amount is near the center value Co can be further extended.

  By the way, the absolute values of the + side initial set frequency fluctuation amount fa and the − side initial set frequency fluctuation amount fb are set larger than the absolute values of the + side maximum input allowable fluctuation amount fc + and the − side maximum input allowable fluctuation amount fc−. There is a possibility that In view of this possibility, the third case and the fourth case will be described below.

  FIG. 6 is a diagram for explaining the outline of the clock frequency adjustment process in the third case. In FIG. 6, the way of viewing the graphs (1) and (2) is the same as in FIG.

  In the third case, the buffer data amount tends to increase in a state where the clock frequency of the variable clock unit 26 is set to the reference frequency fo. In the third case, the absolute values of the + side initial set frequency fluctuation amount fa and the −side initial set frequency fluctuation amount fb are the absolute values of the + side maximum input allowable fluctuation amount fc + and the −side maximum input allowable fluctuation amount fc−. It is set larger than the value.

  In the period from time t0 to t1, the clock frequency is the reference frequency fo. Therefore, during this period, the buffer data amount increases and reaches the upper limit value Cmax at time t1. The reception buffer monitoring unit 461 detects that the buffer data amount has reached the upper limit value Cmax. Therefore, the reception buffer monitoring unit 461 sets the clock frequency to the + side initial set frequency fluctuation amount fa in order to avoid overflow. As a result, the buffer data amount starts to decrease. However, in the third case, the + side initial set frequency fluctuation amount fa is larger than the + side maximum allowable input fluctuation amount fc +. Therefore, loss of synchronization occurs in communication between the IP conversion device 12-2 and the legacy device 10-2. The loss of synchronization is detected by the alarm monitoring unit 201.

  When out-of-synchronization is detected, the clock fluctuation amount search unit 462 continuously decreases the clock frequency until no out-of-synchronization is detected in order to search for the + side maximum allowable input fluctuation amount fc + (time t1 to t1). t2). For example, the clock frequency decreases by α ppm at regular time intervals.

  When the loss of synchronization is not detected at time t2, the clock fluctuation amount search unit 462 stores the clock frequency at time t2 as, for example, the + side maximum input allowable fluctuation amount fc + in the RAM 50.

  Thereafter, when the buffer data amount decreases to the center value Co at time t3, the reception buffer monitoring unit 461 decreases the clock frequency to the reference frequency fo in order to avoid further decrease of the buffer data amount. As a result, the buffer data amount starts increasing again.

  Thereafter, when the buffer data amount reaches the upper limit value Cmax at time t4, the reception buffer monitoring unit 461 sets the clock frequency to the + side maximum allowable input variation amount fc + stored in the RAM 50. As a result, the buffer data amount can be reduced from time t4 to time t5 without causing loss of synchronization. Further, since the + side maximum allowable input fluctuation amount fc + is a value close to the maximum clock frequency in the allowable range of the legacy device 10-2, the period during which the buffer data amount is reduced to the center value Co can be shortened. it can.

  The subsequent steps may be the same as in FIG.

  Next, FIG. 7 is a diagram for explaining the outline of the clock frequency adjustment process in the fourth case. In FIG. 7, the meanings of the graphs (1) and (2) are the same as those in FIG.

  In the fourth case, the buffer data amount tends to decrease in a state where the clock frequency of the variable clock unit 26 is set to the reference frequency fo. In the fourth case, the absolute values of the + side initial set frequency fluctuation amount fa and the −side initial set frequency fluctuation amount fb are the absolute values of the + side maximum input allowable fluctuation amount fc + and the −side maximum input allowable fluctuation amount fc−. It is set larger than the value.

  In the period from time t0 to t1, the clock frequency is the reference frequency fo. Therefore, during this period, the amount of buffer data decreases and reaches the lower limit Cmin at time t1. The reception buffer monitoring unit 461 detects that the buffer data amount has reached the lower limit value Cmin. Therefore, the reception buffer monitoring unit 461 sets the clock frequency to the negative side initial set frequency fluctuation amount fb in order to avoid underflow. As a result, the buffer data amount starts to increase. However, in the fourth case, the −side initial set frequency fluctuation amount fb is smaller than the −side maximum input allowable fluctuation amount fc−. Therefore, loss of synchronization occurs in communication between the IP conversion device 12-2 and the legacy device 10-2. The loss of synchronization is detected by the alarm monitoring unit 201.

  When out-of-synchronization is detected, the clock fluctuation amount search unit 462 continuously increases the clock frequency until no out-of-synchronization is detected in order to search for the −side maximum allowable input fluctuation amount fc− (time t1). ~ T2). For example, the clock frequency increases by α ppm at regular time intervals.

  When loss of synchronization is no longer detected at time t2, the clock fluctuation amount search unit 462 stores the clock frequency at time t2 in the RAM 50, for example, as the −side maximum allowable input fluctuation amount fc−.

  Thereafter, when the buffer data amount increases to the center value Co at time t3, the reception buffer monitoring unit 461 increases the clock frequency to the reference frequency fo in order to avoid further increase of the buffer data amount. As a result, the buffer data amount starts to decrease again.

  After that, when the buffer data amount reaches the lower limit value Cmin at time t4, the reception buffer monitoring unit 461 sets the clock frequency to the −side maximum allowable input fluctuation amount fc− stored in the RAM 50. As a result, the amount of buffer data can be increased from time t4 to time t5 without causing loss of synchronization. Further, since the −side maximum allowable input fluctuation amount fc− is a value close to the minimum clock frequency in the allowable range of the legacy device 10-2, the period during which the buffer data amount is increased to the center value Co is shortened. Can do.

  The subsequent steps may be the same as in FIG.

  Hereinafter, in order to enable the control described in FIG. 4 to FIG. 7, a processing procedure executed by the receiving side IP conversion apparatus 12-2 will be described.

  FIG. 8 is a flowchart for explaining an example of a processing procedure executed by the receiving-side IP conversion apparatus.

  For example, when the IP conversion device 12-2 is activated and reception of an IP packet is started, the legacy interface unit 20 waits until the buffer data amount reaches the center value Co, and then starts reading the reception buffer 502 (S101). Thereafter, the reading of the reception buffer 502 is performed in synchronization with the clock frequency of the variable clock unit 26 (in a cycle based on the clock frequency). At the start of reading of the reception buffer 502, the clock frequency is the reference frequency fo. The reason for waiting until the buffer data amount reaches the center value Co is to reduce the possibility of occurrence of underflow in the reception buffer 502.

  Thereafter, when the reception buffer monitoring unit 461 detects that the buffer data amount has reached the upper limit value Cmax or the lower limit value Cmin (Yes in S102), the + side maximum input allowable variation amount fc + or the −side maximum input allowable variation amount fc. It is determined whether or not − has been searched (S103). This determination may be made, for example, based on whether or not the + side maximum allowable input variation fc + or the −side maximum allowable input variation fc− is stored in the RAM 50.

  When the + side maximum allowable input variation fc + or the −side maximum allowable input variation fc− has not been searched (No in S103), the reception buffer monitoring unit 461 sets the clock frequency of the variable clock unit 26 to the + side initial setting. The frequency fluctuation amount fa or the negative side initial set frequency fluctuation amount fb is set (S104). That is, when the buffer data amount is the upper limit value Cmax, the clock frequency is set to the + side initial set frequency fluctuation amount fa. When the buffer data amount is the lower limit value Cmin, the clock frequency is set to the − side initial set frequency fluctuation amount fb. Note that the clock frequency set here is a clock frequency that is the starting point when the clock fluctuation amount search unit 462 searches for the + side maximum allowable input fluctuation amount fc + or the −side maximum allowable input fluctuation amount fc−.

  When the alarm monitoring unit 201 detects no loss of synchronization (No in S105) in response to setting the clock frequency to the + side initial setting frequency fluctuation amount fa or the − side initial setting frequency fluctuation amount fb. The search unit 462 determines whether or not the buffer data amount is larger than the center value Co (S106). When it is determined that the buffer data amount is larger than the center value Co (Yes in S106), the control described as the first case in FIG. 4 is executed. That is, in step S107, the clock fluctuation amount search unit 462 continuously increases the clock frequency until the alarm monitoring unit 201 detects a loss of synchronization in order to search for the + side maximum allowable input fluctuation amount fc +.

  When out-of-synchronization is detected by the alarm monitoring unit 201, the clock fluctuation amount searching unit 462 uses the clock frequency immediately before the clock frequency when out-of-synchronization is detected as the + side maximum input allowable fluctuation amount fc +, for example, The data is stored in the RAM 50 (S108). Subsequently, the clock frequency is fixed to the clock frequency immediately before the clock frequency when the loss of synchronization is detected (S109).

  On the other hand, when it is determined in step S106 that the buffer data amount is smaller than the center value Co (No in S106), the control described as the second case in FIG. 5 is executed. That is, in step S110, the clock fluctuation amount search unit 462 continuously decreases the clock frequency until the alarm monitoring unit 201 detects a loss of synchronization in order to search for the −side maximum allowable input fluctuation amount fc−. .

  When out-of-synchronization is detected by the alarm monitoring unit 201, the clock fluctuation amount search unit 462 uses, for example, the clock frequency immediately before the clock frequency when out-of-synchronization is detected as the −side maximum allowable input fluctuation amount fc−. And stored in the RAM 50 (S111). Subsequently, the clock frequency of the variable clock unit 26 is fixed to the clock frequency immediately before the clock frequency when the loss of synchronization is detected (S112).

  In step S105, when the alarm monitoring unit 201 detects a loss of synchronization (Yes in S105), the clock fluctuation amount search unit 462 determines whether or not the buffer data amount is larger than the center value Co (step S105). S121). When it is determined that the buffer data amount is larger than the center value Co (Yes in S121), the control described as the third case in FIG. 6 is executed. That is, in step S122, the clock fluctuation amount search unit 462 continuously decreases the clock frequency until no alarm loss is detected by the alarm monitoring unit 201 in order to search for the + side maximum allowable input fluctuation amount fc +.

  When out-of-synchronization is no longer detected by the alarm monitoring unit 201, the clock fluctuation amount search unit 462 stores the clock frequency at which out-of-synchronization is no longer detected as the + side maximum allowable input fluctuation amount fc +, for example, in the RAM 50. (S123). Subsequently, the clock frequency of the variable clock unit 26 is fixed to the clock frequency when no loss of synchronization is detected (S124).

  On the other hand, when it is determined in step S121 that the buffer data amount is smaller than the center value Co (No in S121), the control described as the fourth case in FIG. 7 is executed. That is, in step S125, the clock fluctuation amount search unit 462 continuously increases the clock frequency until no alarm loss is detected by the alarm monitoring unit 201 in order to search for the −side maximum allowable input fluctuation amount fc−. .

  When out-of-synchronization is no longer detected by the alarm monitoring unit 201, the clock fluctuation amount search unit 462 stores the clock frequency at which out-of-synchronization is no longer detected as the −side maximum allowable input fluctuation amount fc−, for example, in the RAM 50. (S126). Subsequently, the clock frequency of the variable clock unit 26 is fixed to the clock frequency when the loss of synchronization is not detected (S127).

  Subsequent to step S109, step S112, step S124, or step S127, when the buffer data amount reaches the center value Co, the reception buffer monitoring unit 461 sets the clock frequency of the variable clock unit 26 to the reference frequency fo ( S128). Subsequently, step S101 and subsequent steps are repeatedly executed.

  Furthermore, in step S103, if the + side maximum allowable input variation fc + or the −side maximum allowable input variation fc− has been searched (Yes in S103), the reception buffer monitoring unit 461 displays the clock of the variable clock unit 26. The frequency is set to the + side maximum allowable input variation fc + or the −side maximum allowable input variation fc− (S104). That is, when the buffer data amount is the upper limit value Cmax, the clock frequency is set to the + side maximum input allowable frequency fluctuation amount fc +. When the buffer data amount is the lower limit value Cmin, the clock frequency is set to the −side maximum allowable input frequency fluctuation amount fc−. Subsequently, step S101 and subsequent steps are repeatedly executed.

  As described above, according to the present embodiment, it is possible to automatically search for the maximum allowable input fluctuation amount of the clock frequency of the legacy device 10-2. As a result, when the buffer data amount is larger than the center value Co or smaller than the center value Co, the clock frequency of the variable clock unit 26 can be adjusted by the fluctuation range of the maximum input allowable fluctuation amount. . Therefore, the state in which the buffer data amount deviates from the center value Co can be quickly resolved. That is, the possibility that the reception buffer 502 overflows or underflows can be reduced, and the possibility that a communication error occurs in synchronous communication can be reduced.

  In the present embodiment, the IP conversion device 12 is an example of a communication device. The synchronous communication network 11-1 or 11-2 is an example of a first communication network. The asynchronous communication network 15 is an example of a second communication network. The reception buffer 502 is an example of a storage unit. The legacy interface unit 20 is an example of a transmission unit. The alarm monitoring unit 201 is an example of a detection unit. The clock fluctuation amount search unit 462 is an example of a search unit. The reception buffer monitoring unit 461 is an example of a changing unit.

  As mentioned above, although the Example of this invention was explained in full detail, this invention is not limited to such specific embodiment, In the range of the summary of this invention described in the claim, various deformation | transformation・ Change is possible.

Regarding the above description, the following items are further disclosed.
(Appendix 1)
A storage unit for storing data received from the second communication network by communication asynchronous to communication in the first communication network;
The data stored in the storage unit is read according to a clock signal, and transmitted to the first communication network,
A detection unit that detects loss of communication with a device that receives data transmitted to the first communication network;
A search unit that changes the frequency of the clock signal to search for an upper limit or a lower limit of a frequency at which the loss of synchronization is not detected;
A change unit that changes the frequency to the upper limit or the lower limit according to the amount of data stored in the storage unit,
A communication device.
(Appendix 2)
The search unit
When the out-of-synchronization is not detected at the starting frequency of the process of changing the frequency and the amount of data in the storage unit is greater than a predetermined value, the frequency is continuously increased and the storage unit When the amount of data is less than the predetermined value, the frequency is continuously decreased, and when the loss of synchronization is detected according to the increase or decrease of the frequency, The communication device according to supplementary note 1, wherein a minimum frequency is determined as the upper limit or the lower limit.
(Appendix 3)
The search unit
When the out-of-synchronization is detected at the frequency of the starting point of the process of changing the frequency, and the data amount in the storage unit is larger than a predetermined value, the frequency is continuously lowered, and the storage unit When the amount of data at is less than the predetermined value, the frequency is continuously increased, and the frequency at which the loss of synchronization is not detected according to the increase or decrease of the frequency is defined as the upper limit or the lower limit. The communication apparatus according to Supplementary Note 1 or 2 for determination.
(Appendix 4)
A communication system including a first communication device and a second communication device connected via a second communication network that performs asynchronous communication with respect to communication in the first communication network,
The first communication device is:
A first transmission unit for transmitting data to the second communication network;
The second communication device is
A storage unit for storing data received from the second communication network;
A second transmission unit that reads out data stored in the storage unit according to a clock frequency and transmits the data to a second communication network;
A detection unit for detecting out-of-synchronization of communication with a device that receives data transmitted to the second communication network;
A search unit that changes the frequency of the clock signal to search for an upper limit or a lower limit of a frequency at which the loss of synchronization is not detected;
A communication system comprising: a changing unit that changes the frequency to the upper limit or the lower limit according to a data amount of data stored in the storage unit.
(Appendix 5)
The search unit
When the out-of-synchronization is not detected at the starting frequency of the process of changing the frequency and the amount of data in the storage unit is greater than a predetermined value, the frequency is continuously increased and the storage unit When the amount of data is less than the predetermined value, the frequency is continuously decreased, and when the loss of synchronization is detected according to the increase or decrease of the frequency, The communication system according to appendix 4, wherein a minimum frequency is determined as the upper limit or the lower limit.
(Appendix 6)
The search unit
When the out-of-synchronization is detected at the frequency of the starting point of the process of changing the frequency, and the data amount in the storage unit is larger than a predetermined value, the frequency is continuously lowered, and the storage unit When the amount of data at is less than the predetermined value, the frequency is continuously increased, and the frequency at which the loss of synchronization is not detected according to the increase or decrease of the frequency is defined as the upper limit or the lower limit. The communication system according to Supplementary Note 4 or 5 for determination.
(Appendix 7)
A storage unit for storing data received from the second communication network by communication asynchronous to communication in the first communication network;
The data stored in the storage unit is read according to a clock signal, and transmitted to the first communication network,
A communication device having a detection unit that detects loss of communication with a device that receives data transmitted to the first communication network.
Change the frequency of the clock signal to search for the upper or lower limit of the frequency at which the loss of synchronization is not detected,
In accordance with the amount of data stored in the storage unit, the frequency is changed to the upper limit or the lower limit.
A program that executes processing.
(Appendix 8)
The searching process is as follows:
When the out-of-synchronization is not detected at the starting frequency of the process of changing the frequency and the amount of data in the storage unit is greater than a predetermined value, the frequency is continuously increased and the storage unit When the amount of data is less than the predetermined value, the frequency is continuously decreased, and when the loss of synchronization is detected according to the increase or decrease of the frequency, The program according to appendix 7, wherein the minimum frequency is determined as the upper limit or the lower limit.
(Appendix 9)
The searching process is as follows:
When the out-of-synchronization is detected at the frequency of the starting point of the process of changing the frequency, and the data amount in the storage unit is larger than a predetermined value, the frequency is continuously lowered, and the storage unit When the amount of data at is less than the predetermined value, the frequency is continuously increased, and the frequency at which the loss of synchronization is not detected according to the increase or decrease of the frequency is defined as the upper limit or the lower limit. The program according to Supplementary Note 7 or 8 for determination.

10-1, 10-2 Legacy devices 11-1, 11-2 Synchronous communication networks 12-1, 12-2 IP converters 14-1, 14-2 Legacy network 15 Asynchronous communication network 18 IP network 20 Legacy interface unit 22 IP interface unit 24 packet processing unit 26 variable clock unit 36 CPU
50 RAM
52 ROM
201 Alarm monitoring unit 241 Packet assembly unit 242 Packet decomposition unit 461 Reception buffer monitoring unit 462 Clock fluctuation amount searching unit 501 Transmission buffer 502 Reception buffer

Claims (5)

A storage unit for storing data received from the second communication network by communication asynchronous to communication in the first communication network;
The data stored in the storage unit is read according to a clock signal, and transmitted to the first communication network,
A detection unit that detects loss of communication with a device that receives data transmitted to the first communication network;
A search unit that changes the frequency of the clock signal to search for an upper limit or a lower limit of a frequency at which the loss of synchronization is not detected;
A change unit that changes the frequency to the upper limit or the lower limit according to the amount of data stored in the storage unit,
A communication device. The search unit
When the out-of-synchronization is not detected at the starting frequency of the process of changing the frequency and the amount of data in the storage unit is greater than a predetermined value, the frequency is continuously increased and the storage unit When the amount of data is less than the predetermined value, the frequency is continuously decreased, and when the loss of synchronization is detected according to the increase or decrease of the frequency, The communication apparatus according to claim 1, wherein a minimum frequency is determined as the upper limit or the lower limit. The search unit
When the out-of-synchronization is detected at the frequency of the starting point of the process of changing the frequency, and the data amount in the storage unit is larger than a predetermined value, the frequency is continuously lowered, and the storage unit When the amount of data at is less than the predetermined value, the frequency is continuously increased, and the frequency at which the loss of synchronization is not detected according to the increase or decrease of the frequency is defined as the upper limit or the lower limit. The communication device according to claim 1, wherein the communication device is determined. A communication system including a first communication device and a second communication device connected via a second communication network that performs asynchronous communication with respect to communication in the first communication network,
The first communication device is:
A first transmission unit for transmitting data to the second communication network;
The second communication device is
A storage unit for storing data received from the second communication network;
A second transmission unit that reads out data stored in the storage unit according to a clock frequency and transmits the data to a second communication network;
A detection unit for detecting out-of-synchronization of communication with a device that receives data transmitted to the second communication network;
A search unit that changes the frequency of the clock signal to search for an upper limit or a lower limit of a frequency at which the loss of synchronization is not detected;
A communication system comprising: a changing unit that changes the frequency to the upper limit or the lower limit according to a data amount of data stored in the storage unit. A storage unit for storing data received from the second communication network by communication asynchronous to communication in the first communication network;
The data stored in the storage unit is read according to a clock signal, and transmitted to the first communication network,
A communication device having a detection unit that detects loss of communication with a device that receives data transmitted to the first communication network.
Change the frequency of the clock signal to search for the upper or lower limit of the frequency at which the loss of synchronization is not detected,
In accordance with the amount of data stored in the storage unit, the frequency is changed to the upper limit or the lower limit.
A program that executes processing.

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