KR100532446B1 - 반도체 소자의 금속배선층 형성방법 - Google Patents

반도체 소자의 금속배선층 형성방법 Download PDF

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Publication number
KR100532446B1
KR100532446B1 KR10-2003-0047006A KR20030047006A KR100532446B1 KR 100532446 B1 KR100532446 B1 KR 100532446B1 KR 20030047006 A KR20030047006 A KR 20030047006A KR 100532446 B1 KR100532446 B1 KR 100532446B1
Authority
KR
South Korea
Prior art keywords
layer
hard mask
via hole
etching
forming
Prior art date
Application number
KR10-2003-0047006A
Other languages
English (en)
Korean (ko)
Other versions
KR20050007004A (ko
Inventor
김일구
하상록
손세일
이경우
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR10-2003-0047006A priority Critical patent/KR100532446B1/ko
Priority to JP2004021868A priority patent/JP4988148B2/ja
Priority to US10/888,577 priority patent/US7157366B2/en
Publication of KR20050007004A publication Critical patent/KR20050007004A/ko
Application granted granted Critical
Publication of KR100532446B1 publication Critical patent/KR100532446B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
KR10-2003-0047006A 2002-04-02 2003-07-10 반도체 소자의 금속배선층 형성방법 KR100532446B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR10-2003-0047006A KR100532446B1 (ko) 2003-07-10 2003-07-10 반도체 소자의 금속배선층 형성방법
JP2004021868A JP4988148B2 (ja) 2003-07-10 2004-01-29 半導体素子の金属配線の形成方法
US10/888,577 US7157366B2 (en) 2002-04-02 2004-07-09 Method of forming metal interconnection layer of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2003-0047006A KR100532446B1 (ko) 2003-07-10 2003-07-10 반도체 소자의 금속배선층 형성방법

Publications (2)

Publication Number Publication Date
KR20050007004A KR20050007004A (ko) 2005-01-17
KR100532446B1 true KR100532446B1 (ko) 2005-11-30

Family

ID=34214643

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2003-0047006A KR100532446B1 (ko) 2002-04-02 2003-07-10 반도체 소자의 금속배선층 형성방법

Country Status (2)

Country Link
JP (1) JP4988148B2 (ja)
KR (1) KR100532446B1 (ja)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100744068B1 (ko) * 2005-04-29 2007-07-30 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 제조 방법
KR100770540B1 (ko) * 2005-12-28 2007-10-25 동부일렉트로닉스 주식회사 반도체 소자 제조 방법
KR100752176B1 (ko) 2005-12-29 2007-08-24 동부일렉트로닉스 주식회사 플라즈마 반응 부산물을 이용한 박막의 패터닝 방법
KR100727259B1 (ko) * 2005-12-29 2007-06-11 동부일렉트로닉스 주식회사 반도체 장치의 배선 형성방법
US20090014887A1 (en) * 2006-01-06 2009-01-15 Nec Corporation Method of producing multilayer interconnection and multilayer interconnection structure
JP4684924B2 (ja) * 2006-03-16 2011-05-18 東京エレクトロン株式会社 プラズマエッチング方法、プラズマエッチング装置及びコンピュータ記憶媒体
JP5072531B2 (ja) * 2007-10-24 2012-11-14 東京エレクトロン株式会社 プラズマエッチング方法及び記憶媒体
KR100928507B1 (ko) * 2007-12-03 2009-11-26 주식회사 동부하이텍 반도체 소자의 제조 방법
CN104170068B (zh) * 2012-04-24 2019-05-10 应用材料公司 用于低蚀刻速率硬模膜的具有氧掺杂的pvd氮化铝膜
JP6163820B2 (ja) * 2013-03-27 2017-07-19 日本ゼオン株式会社 エッチング方法
CN105632886B (zh) * 2014-10-30 2018-08-10 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
CN112415799A (zh) * 2020-11-10 2021-02-26 Tcl华星光电技术有限公司 阵列基板及其制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3312604B2 (ja) * 1998-11-06 2002-08-12 日本電気株式会社 半導体装置の製造方法
US6461955B1 (en) * 1999-04-29 2002-10-08 Texas Instruments Incorporated Yield improvement of dual damascene fabrication through oxide filling
US6861347B2 (en) * 2001-05-17 2005-03-01 Samsung Electronics Co., Ltd. Method for forming metal wiring layer of semiconductor device
JP2002373936A (ja) * 2001-06-14 2002-12-26 Nec Corp デュアルダマシン法による配線形成方法
US6620727B2 (en) * 2001-08-23 2003-09-16 Texas Instruments Incorporated Aluminum hardmask for dielectric etch
JP3880851B2 (ja) * 2001-12-10 2007-02-14 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
KR20050007004A (ko) 2005-01-17
JP2005033168A (ja) 2005-02-03
JP4988148B2 (ja) 2012-08-01

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