KR100526845B1 - Circuit board and its manufacturing method - Google Patents
Circuit board and its manufacturing method Download PDFInfo
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- KR100526845B1 KR100526845B1 KR10-2000-0081977A KR20000081977A KR100526845B1 KR 100526845 B1 KR100526845 B1 KR 100526845B1 KR 20000081977 A KR20000081977 A KR 20000081977A KR 100526845 B1 KR100526845 B1 KR 100526845B1
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- thin film
- pattern
- circuit board
- insulating layer
- hole
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
이 발명은 회로기판 및 그 제조 방법에 관한 것으로, 솔더 조인트 신뢰성(Solder Joint Reliability)을 향상시킬 수 있도록, 제1면과 제2면을 갖는 동시에, 다수의 관통공이 어레이된 대략 판상의 절연층이 구비되고, 상기 절연층의 관통공을 제외한 제2면에는 접착층이 접착되어 있으며, 상기 절연층의 관통공 내측에는 바텀패턴이 형성되어 있고, 상기 바텀패턴으로부터는 상기 관통공의 내벽 전체를 따라 상기 제2면까지 절곡패턴이 형성되어 있으며, 상기 절곡패턴으로부터는 상기 접착층 일정 영역까지 대략 라인(Line) 형태의 탑패턴이 형성되어 이루어진 회로기판을 특징으로 함.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board and a method for manufacturing the same, and includes a substantially plate-like insulating layer having a first surface and a second surface and having a plurality of through holes arranged therein so as to improve solder joint reliability. And an adhesive layer is bonded to the second surface of the insulating layer except for the through hole, and a bottom pattern is formed inside the through hole of the insulating layer, and the bottom pattern is formed along the entire inner wall of the through hole. A bending pattern is formed to a second surface, and the circuit board is formed by forming a top pattern in a substantially line shape from the bending pattern to a predetermined region of the adhesive layer.
Description
본 발명은 회로기판 및 그 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 솔더 조인트 신뢰성(Solder Joint Reliability)을 향상시킬 수 있는 회로기판 및 그 제조 방법에 관한 것이다.The present invention relates to a circuit board and a method for manufacturing the same, and more particularly, to a circuit board and a method for manufacturing the same that can improve solder joint reliability.
통상 랜드그리드어레이(LGA, Land Grid Array) 반도체패키지는 그 구성 요소중 하나인 회로기판에 있어서, 상기 회로기판의 하면에 마더보드와의 접속을 위한 랜드가 어레이된 형태를 한다. 이러한 형태는 최근 반도체칩의 크기에 가까운 칩스케일(Chip Scale Package) 반도체패키지에 주로 적용되고 있으며, 또한 전자기기의 크기가 점차 작아지는 추세에 따라 많은 이용률을 보이고 있다.In general, a land grid array (LGA) semiconductor package is a circuit board, which is one of its components, in which lands for connection with a motherboard are arrayed on a lower surface of the circuit board. This type is mainly applied to a chip scale package that is close to the size of a semiconductor chip, and also shows a large utilization rate as the size of electronic devices is gradually reduced.
이러한 종래의 LGA 반도체패키지(100') 및 이것과 마더보드(7')의 접속 구조가 도1에 도시되어 있다.This conventional LGA semiconductor package 100 'and its connection structure with the motherboard 7' are shown in FIG.
도시된 바와 같이 종래의 반도체패키지(100')는, 표면에 다수의 입출력패드(2a')를 갖는 반도체칩(2')이 구비되어 있고, 상기 반도체칩(2')의 하면에는 접착층(5')에 의해 회로기판(10')이 접착되어 있다. 여기서, 상기 회로기판은 인쇄회로기판, 써킷테이프, 써킷필름 등이 가능하다.As illustrated, the conventional semiconductor package 100 'includes a semiconductor chip 2' having a plurality of input / output pads 2a 'on its surface, and an adhesive layer 5 on the bottom surface of the semiconductor chip 2'. The circuit board 10 'is bonded by'). The circuit board may be a printed circuit board, a circuit tape, a circuit film, or the like.
상기 회로기판(10')은 본드핑거(12a') 및 랜드(12b')를 포함하는 다수의 배선패턴(12')이 형성되어 있으며, 상기 배선패턴(12')은 절연층(11')(예를 들면, 폴리이미드(Polyimide))상에 형성되어 있다. 여기서, 상기 배선패턴(12')중 랜드(12b') 하면은 절연층(11')을 통해 하부로 노출되어 있으며, 이러한 랜드(12b')는 행과 열을 가지며 회로기판 하면에 다수가 어레이(Array)된 형태를 한다.The circuit board 10 'is formed with a plurality of wiring patterns 12' including a bond finger 12a 'and a land 12b', and the wiring pattern 12 'is formed of an insulating layer 11'. (E.g., polyimide). Here, the lower surface of the land 12b 'of the wiring pattern 12' is exposed downward through the insulating layer 11 ', and the lands 12b' have rows and columns, and a plurality of lands are arranged on the lower surface of the circuit board. It takes an array.
계속해서, 상기 반도체칩(2')의 입출력패드(2a')와 회로기판(10')의 배선패턴(12')중 본드핑거(12a')는 전기적 접속수단(3')에 의해 상호 접속되어 있고, 상기 회로기판(10') 상면의 반도체칩(2'), 전기적 접속수단(3') 등은 봉지재로 봉지되어 일정 형태의 봉지부(4')를 이루고 있다.Subsequently, the bond fingers 12a 'of the input / output pads 2a' of the semiconductor chip 2 'and the wiring patterns 12' of the circuit board 10 'are interconnected by electrical connection means 3'. The semiconductor chip 2 'and the electrical connection means 3' on the upper surface of the circuit board 10 'are encapsulated with an encapsulant to form a certain encapsulation portion 4'.
한편, 이러한 반도체패키지(100')는 회로기판(10')의 랜드(12b')와 마더보드(7')의 보드랜드(8') 위치를 일치시킨 상태에서, 솔더(6')를 리플로우(Reflow)하여, 상기 회로기판(10')의 랜드(12b')와 마더보드(7')의 보드랜드(8')가 상호 접속(솔더 조인트)되도록 하고 있다. 물론, 상기 솔더(6')는 상기 보드(7')의 보드랜드(8')에 미리 프린팅되어 있거나, 또는 반도체패키지(100')의 랜드(12b')에 프린팅된 상태이다.Meanwhile, the semiconductor package 100 'ripples the solder 6' in a state where the land 12b 'of the circuit board 10' and the board land 8 'of the motherboard 7' are aligned. In order to reflow, the land 12b 'of the circuit board 10' and the board land 8 'of the motherboard 7' are interconnected (solder joint). Of course, the solder 6 'is preprinted on the board land 8' of the board 7 'or printed on the land 12b' of the semiconductor package 100 '.
그러나, 상기와 같은 종래의 반도체패키지 및 이것과 마더보드 사이의 접속 구조는 제조 공정중 전적으로 마더보드의 보드랜드(또는 반도체패키지의 랜드)에 프린팅된 솔더의 량에 따라 접속률이 결정되는 단점이 있다.However, such a conventional semiconductor package and the connection structure between it and the motherboard have a disadvantage in that the connection rate is determined in accordance with the amount of solder printed entirely on the motherboard land (or land of the semiconductor package) during the manufacturing process. .
즉, 도1에 도시된 확대도에서와 같이 반도체패키지의 랜드 하면은 일정두께를 갖는 절연층의 하면에서 상부로 일정거리 이격된 영역에 위치되기 때문에, 그것과 대응되는 솔더의 량이 작을 경우, 리플로우 공정에서 상기 솔더가 상기 랜드 하면에까지 융용되어 올라가지 않음으로써, 결국 반도체패키지와 마더보드의 접속불량이 발생하게 된다.That is, as shown in the enlarged view of FIG. 1, the land lower surface of the semiconductor package is located in a region spaced a predetermined distance upward from the lower surface of the insulating layer having a predetermined thickness, so that when the amount of solder corresponding thereto is small, the ripple In the row process, the solder is not melted up to the lower surface of the land, resulting in a poor connection between the semiconductor package and the motherboard.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 반도체패키지와 마더보드 사이의 솔더 조인트 신뢰성(Solder Joint Reliability)을 향상시킬 수 있는 회로기판 및 그 제조 방법을 제공하는데 있다.Accordingly, an aspect of the present invention is to provide a circuit board and a method of manufacturing the same, which can improve solder joint reliability between a semiconductor package and a motherboard.
상기한 목적을 달성하기 위해 본 발명에 의한 회로기판은 제1면과 제2면을 갖는 동시에, 다수의 관통공이 어레이된 대략 판상의 절연층이 구비되고, 상기 절연층의 관통공을 제외한 제2면에는 접착층이 접착되어 있으며, 상기 절연층의 관통공 내측에는 바텀패턴이 형성되어 있고, 상기 바텀패턴으로부터는 상기 관통공의 내벽 전체를 따라 상기 제2면까지 절곡패턴이 형성되어 있으며, 상기 절곡패턴으로부터는 상기 접착층 일정 영역까지 대략 라인(Line) 형태의 탑패턴이 형성되어 이루어진 것을 특징으로 한다.In order to achieve the above object, the circuit board according to the present invention has a first plate and a second surface, and is provided with a substantially plate-like insulating layer in which a plurality of through holes are arranged, and the second except the through holes of the insulating layer. An adhesive layer is adhered to the surface, a bottom pattern is formed inside the through hole of the insulating layer, and a bending pattern is formed from the bottom pattern to the second surface along the entire inner wall of the through hole. From the pattern is characterized in that the top pattern of approximately a line (Line) form is formed to a predetermined region of the adhesive layer.
여기서, 상기 바텀패턴은 상기 절연층의 제1면과 동일한 평면에 형성됨이 바람직하다.Here, the bottom pattern is preferably formed on the same plane as the first surface of the insulating layer.
또한, 상기 바텀패턴과 절곡패턴은 단면상 대략 "U"형 또는 "V"형중 어느 하나로 형성될 수도 있다.In addition, the bottom pattern and the bending pattern may be formed in one of approximately "U" type or "V" type in cross section.
더불어, 상기한 목적을 달성하기 위해 본 발명에 의한 회로기판의 제조 방법은 제1면과 제2면을 갖는 동시에, 다수의 관통공이 어레이되고, 상기 제2면에는 접착층이 접착되어 있는 절연층과, 바텀박막 및 상기 바텀박막으로부터 상방향으로 절곡박막이 연장되고, 상기 절곡박막에는 상기 절연층의 제2면과 수평 방향으로 탑박막이 형성된 도전성 박막을 제공하는 단계와; 상기 절연층의 관통공 내측에 도전성 박막중중 바텀박막 및 절곡박막이 위치하도록 하고, 탑박막은 상기 접착층에 접착되도록 하는 단계와; 상기 도전성 박막에서 바텀박막, 절곡박막 및 탑박막이 일체의 배선패턴이 되도록, 상기 탑박막중 불필요한 부분을 에칭하여 제거하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, in order to achieve the above object, the method of manufacturing a circuit board according to the present invention has a first surface and a second surface, and a plurality of through holes are arrayed, and the second surface has an insulating layer having an adhesive layer bonded thereto; Providing a conductive thin film having a top thin film extending in a horizontal direction from the bottom thin film and the bottom thin film, wherein the bent thin film extends in a horizontal direction with the second surface of the insulating layer; A bottom thin film and a bent thin film in the conductive thin film are positioned inside the through hole of the insulating layer, and the top thin film is adhered to the adhesive layer; And etching unnecessary portions of the top thin film so that the bottom thin film, the bent thin film, and the top thin film are integrated wiring patterns in the conductive thin film.
여기서, 상기 도전성 박막 제공단계는 상기 도전성 박막이 펀치에 의해 일정 깊이 타발됨으로써, 상기 바텀박막 및 절곡박막이 형성될 수 있다.Here, in the providing of the conductive thin film, the bottom thin film and the bent thin film may be formed by punching the conductive thin film by a predetermined depth.
또한, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 일면에 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 타면에 접착층으로 접착되어 있되, 제1면과 제2면을 갖는 동시에, 다수의 관통공이 어레이된 대략 판상의 절연층이 구비되고, 상기 절연층의 관통공 내측에는 바텀패턴이 형성되고, 상기 바텀패턴으로부터는 상기 관통공의 내벽 전체를 따라 상기 제2면까지 절곡패턴이 형성되며, 상기 절곡패턴으로부터는 상기 제2면 일정 영역까지 대략 라인(Line) 형태의 탑패턴이 형성된 회로기판과; 상기 반도체칩의 입출력패드와 회로기판의 탑패턴을 상호 전기적으로 접속시키는 전기적 접속수단과; 상기 회로기판의 상면, 반도체칩 및 전기적 접속수단을 봉지재로 봉지하여 형성된 봉지부를 포함하여 이루어진 것을 특징으로 한다.In addition, the semiconductor package according to the present invention to achieve the above object is a semiconductor chip having a plurality of input and output pads on one surface; It is bonded to the other surface of the semiconductor chip with an adhesive layer, and has a substantially plate-like insulating layer having a first surface and a second surface and an array of a plurality of through holes, and a bottom pattern formed inside the through hole of the insulating layer. And a bending pattern is formed along the entire inner wall of the through hole from the bottom pattern to the second surface, and a top pattern having a substantially line shape from the bending pattern to a predetermined area of the second surface is formed. A substrate; Electrical connection means for electrically connecting the input / output pad of the semiconductor chip with the top pattern of the circuit board; And an encapsulation portion formed by encapsulating the upper surface of the circuit board, the semiconductor chip, and the electrical connection means with an encapsulant.
상기와 같이 하여 본 발명에 의한 회로기판 및 그 제조 방법에 의하면, 회로기판에 형성된 배선패턴중 바텀패턴이 절연층의 제1면과 일치하는 관통공의 일정영역에 형성됨으로써, 차후 마더보드와의 솔더를 이용한 접속 신뢰성이 향상되는 장점이 있다. 즉, 마더보드의 보드랜드에 프린팅된 솔더와 상기 바텀패턴의 거리가 매우 가깝게 됨으로써, 그 솔더의 융착이 용이하게 수행되며, 종래와 같이 바텀패턴 즉, 랜드에 별도의 솔더를 충진할 필요도 없게 된다.According to the circuit board and the manufacturing method thereof according to the present invention as described above, the bottom pattern of the wiring pattern formed on the circuit board is formed in a predetermined region of the through hole coinciding with the first surface of the insulating layer, so as to There is an advantage in that connection reliability using solder is improved. That is, since the distance printed between the solder printed on the motherboard of the motherboard and the bottom pattern is very close, fusion of the solder is performed easily, so that the bottom pattern, that is, conventionally, does not need to fill a separate solder in the land. do.
더불어, 봉지부가 회로기판의 바텀패턴과 절곡패턴 사이의 공간에 인터락킹됨으로써, 봉지부와 회로기판 상호간의 계면 박리 현상을 더욱 효과적으로 억제할 수 있게 된다.In addition, since the encapsulation part is interlocked in the space between the bottom pattern and the bent pattern of the circuit board, it is possible to more effectively suppress the interface peeling phenomenon between the encapsulation part and the circuit board.
또한, 반도체칩과 회로기판의 바텀패턴 및 절곡패턴 사이의 공간에 충진되는 접착층도 그 접착면적이 넓어짐으로써, 반도체칩과 회로기판 상호간의 접착력도 향상되는 장점이 있다.In addition, the adhesive layer filled in the space between the bottom pattern and the bending pattern of the semiconductor chip and the circuit board also has a wider adhesive area, thereby improving the adhesion between the semiconductor chip and the circuit board.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도2a 내지 도2c는 본 발명에 의한 회로기판(10)을 도시한 단면도, 평면도 및 저면도이다.2A to 2C are a cross-sectional view, a plan view, and a bottom view showing a circuit board 10 according to the present invention.
먼저 대략 평면인 제1면(1a)과 제2면(1b)을 갖는 동시에, 상기 제1면(1a) 및 제2면(1b)을 관통하는 다수의 관통공(2)이 어레이(Array)된 절연층(1)이 구비되어 있다.First, the first surface 1a and the second surface 1b are substantially planar, and a plurality of through holes 2 penetrating the first surface 1a and the second surface 1b are arranged in an array. Insulating layer 1 is provided.
여기서, 상기 절연층(1)으로서는 폴리이미드(Polyimide) 또는 통상적인 접착테이프 및 접착필름이 가능하다.Here, as the insulating layer 1, polyimide or conventional adhesive tape and adhesive film may be used.
계속해서, 상기 절연층(1)의 관통공(2)을 제외한 제2면(1b)에는 일정 두께의 접착층(4)이 접착되어 있으며, 상기 접착층(4)에는 도전성 배선패턴(3)이 일정한 모양을 가지며 접착되어 있다.Subsequently, an adhesive layer 4 having a predetermined thickness is adhered to the second surface 1b except for the through hole 2 of the insulating layer 1, and the conductive wiring pattern 3 is fixed to the adhesive layer 4. It is shaped and glued.
즉, 상기 배선패턴(3)은 절연층(1)의 관통공(2) 내측에 바텀패턴(3a)이 형성되어 있고, 상기 바텀패턴(3a)으로부터는 상기 관통공(2)의 내벽 전체를 따라 상기 제2면(1b) 즉, 접착층(4)까지는 절곡패턴(3b)이 형성되어 있으며, 상기 절곡패턴(3b)으로부터는 상기 접착층(4) 일정 영역까지 대략 라인(Line) 형태로 탑패턴(3c)이 형성되어 있다.That is, the wiring pattern 3 has a bottom pattern 3a formed inside the through hole 2 of the insulating layer 1, and the entire inner wall of the through hole 2 is formed from the bottom pattern 3a. Accordingly, a bending pattern 3b is formed on the second surface 1b, that is, the adhesive layer 4, and the top pattern is formed in a line shape from the bending pattern 3b to a predetermined region of the adhesive layer 4. (3c) is formed.
여기서, 상기 바텀패턴(3a)에는 실장 공정중 솔더(60)가 융착되며, 상기 탑패턴(3c)에는 패키징 공정중 전기적 접속수단(30)이 접속된다.Here, the solder 60 is welded to the bottom pattern 3a during the mounting process, and the electrical connection means 30 is connected to the top pattern 3c during the packaging process.
한편, 상기 바텀패턴(3a)은 상기 절연층(1)의 제1면(1a)과 동일한 평면에 형성됨이 바람직하다. 또한, 상기 바텀패턴(3a)의 면적은 상기 관통공(2)의 면적과 동일하게 형성됨이 바람직하다. 더불어, 상기 바텀패턴(3a)과 절곡패턴(3b)의 합성 형상은 도2a에 단면상 대략 "┗┛"형으로 형성되어 있으나 이러한 형상으로만 한정되는 것이아니라, 대략 "U"형 또는 "V"형중 어느 하나로 형성될 수도 있다.On the other hand, the bottom pattern (3a) is preferably formed on the same plane as the first surface (1a) of the insulating layer (1). In addition, the area of the bottom pattern 3a is preferably equal to the area of the through hole 2. In addition, the composite shape of the bottom pattern (3a) and the bending pattern (3b) is formed in a substantially "┗┛" shape in cross-section in Figure 2a, but is not limited to this shape, but approximately "U" or "V" It may be formed of any one of the molds.
이어서, 도3a 내지 도3c는 본 발명에 의한 회로기판(10)의 제조 방법을 도시한 순차 설명도이다.3A to 3C are sequential explanatory diagrams showing a method for manufacturing the circuit board 10 according to the present invention.
1. 절연층 및 도전성 박막 제공 단계로서, 대략 평면인 제1면(1a)과 제2면(1b)을 갖는 동시에, 다수의 관통공(2)이 일정 간격으로 어레이되어 있고, 상기 제2면(1b)에는 접착층(4)이 접착되어 있는 절연층(1)을 제공한다.1. A step of providing an insulating layer and a conductive thin film, the first surface 1a and the second surface 1b being substantially planar, and a plurality of through holes 2 are arranged at regular intervals, and the second surface In 1b, the insulating layer 1 to which the adhesive layer 4 is bonded is provided.
또한, 일정크기의 구경을 가지며 일측으로 돌출된 바텀박막(3a') 및 상기 바텀박막(3a')으로부터 일방향으로 절곡된 절곡박막(3b')이 형성되어 있으며, 상기 절곡박막(3b')은 대략 판상의 탑박막(3c')에 연결되어 있는 도전성 박막(3")을 제공한다.In addition, a bottom thin film 3a 'having a predetermined size and protruding to one side and a bent thin film 3b' bent in one direction from the bottom thin film 3a 'are formed, and the bent thin film 3b' is formed. A conductive thin film 3 "connected to the substantially plate-like top thin film 3c 'is provided.
여기서, 상기 바텀박막(3a') 및 절곡박막(3b')은 일정 길이를 갖는 펀치로 상기 도전성 박막(3")을 타발함으로써 형성할 수 있다.Here, the bottom thin film 3a 'and the bent thin film 3b' may be formed by punching the conductive thin film 3 "with a punch having a predetermined length.
또한, 여기서 상기 절연층(1)의 관통공(2) 피치와 상기 바텀박막의 피치는 동일하게 되도록 한다. 또한, 상기 절연층(1)의 두께(관통공(2)의 높이)와 상기 절곡박막(3b')의 두께(절곡박막의 높이)는 동일해지도록 한다.In this case, the pitch of the through hole 2 of the insulating layer 1 and the pitch of the bottom thin film are the same. In addition, the thickness of the insulating layer 1 (the height of the through hole 2) and the thickness of the bent thin film 3b '(the height of the bent thin film) are made equal.
2. 절연층과 도전성 박막 접착 단계로서, 상기 절연층(1)의 관통공(2) 내측에 도전성 박막(3")중 바텀박막(3a') 및 절곡박막(3b')이 위치하도록 하고, 상기 탑박막(3c')은 상기 접착층(4)에 접착되도록 한다.2. Bonding the insulating layer and the conductive thin film, so that the bottom thin film 3a 'and the bent thin film 3b' of the conductive thin film 3 "are positioned inside the through hole 2 of the insulating layer 1, The top thin film 3c 'is bonded to the adhesive layer 4.
3. 배선패턴 형성 단계로서, 상기 도전성 박막(3")에서 바텀박막(3a'), 절곡박막(3b') 및 탑박막(3c')이 일체의 배선패턴(3)이 되도록, 상기 탑박막(3c')중 불필요한 부분을 에칭하여 제거함으로써, 바텀패턴(3a), 절곡패턴(3b) 및 탑패턴(3c)이 하나의 배선패턴(3)을 이루도록 한다.3. A wiring pattern forming step, wherein the top thin film is formed such that the bottom thin film 3a ', the bent thin film 3b', and the top thin film 3c 'are integrated wiring patterns 3 in the conductive thin film 3 ". By removing unnecessary portions of 3c ', the bottom pattern 3a, the bent pattern 3b, and the top pattern 3c form one wiring pattern 3.
도4는 본 발명에 의한 회로기판(10)을 이용한 반도체패키지(100)를 도시한 단면도이다.4 is a cross-sectional view showing a semiconductor package 100 using the circuit board 10 according to the present invention.
먼저, 상면에 다수의 입출력패드(22)가 형성된 반도체칩(21)이 구비되어 있다.First, a semiconductor chip 21 having a plurality of input / output pads 22 formed thereon is provided.
상기 반도체칩(21)의 하면에는 상술한 구조의 회로기판(10)이 접착층(40)(4)으로 접착되어 있다. 즉, 대략 평면인 제1면(1a)과 제2면(1b)을 갖는 동시에, 다수의 관통공(2)이 어레이된 대략 판상의 절연층(1)이 구비되고, 상기 절연층(1)의 관통공(2) 내측에는 바텀패턴(3a)이 형성되고, 상기 바텀패턴(3a)으로부터는 상기 관통공(2)의 내벽 전체를 따라 상기 제2면(3b)까지 절곡패턴(3b)이 형성되며, 상기 절곡패턴(3b)으로부터는 상기 제2면(3b) 일정 영역까지 대략 라인(Line) 형태의 탑패턴(3c)이 형성된 회로기판(10)이 상기 반도체칩(21)의 하면에 접착층(40)으로 접착되어 있다.The circuit board 10 having the above-described structure is bonded to the lower surface of the semiconductor chip 21 by the adhesive layers 40 and 4. That is, a substantially plate-like insulating layer 1 having a first plane 1a and a second surface 1b which are substantially planar and an array of a plurality of through holes 2 is provided, and the insulating layer 1 A bottom pattern 3a is formed inside the through hole 2, and a bending pattern 3b is formed from the bottom pattern 3a to the second surface 3b along the entire inner wall of the through hole 2. And a circuit board 10 having a top pattern 3c having a substantially line shape from the bending pattern 3b to a predetermined region of the second surface 3b is formed on the bottom surface of the semiconductor chip 21. It is bonded by the adhesive layer 40.
여기서 상기 반도체칩(21)과 회로기판(10)을 접착시키는 접착층(40)은 회로기판(10)의 바텀패턴(3a)과 절곡패턴(3b) 사이의 공간에 충진됨으로써, 그 접착면적이 넓어져 반도체칩(21)의 접착력이 향상된다.Here, the adhesive layer 40 for adhering the semiconductor chip 21 and the circuit board 10 is filled in the space between the bottom pattern 3a and the bending pattern 3b of the circuit board 10, thereby increasing the adhesion area. The adhesion of the semiconductor chip 21 is improved.
계속해서, 상기 반도체칩(21)의 입출력패드(22)와 회로기판(10)의 탑패턴(3c)은 도전성와이어와 같은 전기적 접속수단(30)에 의해 상호 접속되어 있다.Subsequently, the input / output pad 22 of the semiconductor chip 21 and the top pattern 3c of the circuit board 10 are connected to each other by electrical connection means 30 such as conductive wires.
또한, 상기 회로기판(10)의 상면, 반도체칩(21) 및 전기적 접속수단(30)은 에폭시몰딩컴파운드(Epoxy Molding Compound) 또는 글럽탑(Glop Top)과 같은 봉지재로 봉지되어 일정 형태의 봉지부(50)가 형성되어 있다. 여기서도, 상기 봉지부(50)는 회로기판(10)의 바텀패턴(3a)과 절곡패턴(3b) 사이의 공간에 충진됨으로써, 접착면적이 넓어짐과 동시에 인터락킹(Inter-locking) 효과를 유발하여 계면간의 박리 현상을 억제할 수 있게 된다.In addition, the upper surface of the circuit board 10, the semiconductor chip 21 and the electrical connection means 30 is encapsulated with an encapsulant such as an epoxy molding compound or a glove top to encapsulate a certain type of encapsulation. The part 50 is formed. In this case, the encapsulation part 50 is filled in the space between the bottom pattern 3a and the bending pattern 3b of the circuit board 10, thereby increasing the adhesive area and inducing an inter-locking effect. The peeling phenomenon between interfaces can be suppressed.
도5는 본 발명에 의한 반도체패키지(100)의 실장 상태를 도시한 단면도이다.5 is a cross-sectional view showing a mounting state of the semiconductor package 100 according to the present invention.
도시된 바와 같이 본 발명에 의한 반도체패키지(100)는 바텀패턴(3a)(종래의 랜드에 해당)이 절연층(1)의 제1면(3a)과 동일면에 형성되어 있음으로써, 솔더(60)와의 융착력 또는 접착력이 향상될 수 있도록 되어 있다. 즉, 마더보드(70)의 보드랜드(71) 또는 상기 반도체패키지(100)의 바텀패턴(3a)에 일정크기의 솔더(60)가 위치되고, 리플로우 공정을 통과할 때, 융용된 솔더(60)와 상기 반도체패키지(100)의 바텀패턴(3a) 사이의 거리가 매우 가까움으로써 그 융창력 또는 접착력이 향상되고, 결국은 솔더 조인트 신뢰성(Solder Joint Reliability)이 향상된다.As shown in the figure, the semiconductor package 100 according to the present invention has a bottom pattern 3a (corresponding to a conventional land) formed on the same surface as the first surface 3a of the insulating layer 1, whereby the solder 60 Fusion or adhesion with)) can be improved. That is, a predetermined size solder 60 is positioned on the board land 71 of the motherboard 70 or the bottom pattern 3a of the semiconductor package 100, and when the solder 60 passes through the reflow process, the molten solder ( The distance between the bottom pattern 3a of the semiconductor package 100 and the semiconductor package 100 is very close, thereby improving the fusion or adhesion, and ultimately, the solder joint reliability.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
따라서, 본 발명에 의한 회로기판 및 그 제조 방법에 의하면, 회로기판에 형성된 배선패턴중 바텀패턴이 절연층의 제1면과 일치하는 관통공의 일정영역에 형성됨으로써, 차후 마더보드와의 솔더를 이용한 접속 신뢰성이 향상되는 효과가 있다. 즉, 마더보드의 보드랜드에 프린팅된 솔더와 상기 바텀패턴의 거리가 매우 가깝게 됨으로써, 그 솔더의 융착이 용이하게 수행되며, 종래와 같이 바텀패턴 즉, 랜드에 별도의 솔더를 충진할 필요도 없게 된다. Therefore, according to the circuit board and the manufacturing method thereof according to the present invention, the bottom pattern of the wiring patterns formed on the circuit board is formed in a predetermined region of the through hole coinciding with the first surface of the insulating layer, so that the solder with the motherboard is subsequently The used connection reliability is improved. That is, since the distance printed between the solder printed on the motherboard of the motherboard and the bottom pattern is very close, fusion of the solder is performed easily, so that the bottom pattern, that is, conventionally, does not need to fill a separate solder in the land. do.
또한, 봉지부가 회로기판의 바텀패턴과 절곡패턴 사이의 공간에 인터락킹됨으로써, 봉지부와 회로기판 상호간의 계면 박리 현상을 더욱 효과적으로 억제할 수 있는 효과가 있다.In addition, since the encapsulation part is interlocked in the space between the bottom pattern and the bent pattern of the circuit board, there is an effect of more effectively suppressing the interface peeling phenomenon between the encapsulation part and the circuit board.
더불어, 반도체칩과 회로기판의 바텀패턴 및 절곡패턴 사이의 공간에 충진되는 접착층도 그 접착면적이 넓어짐으로써, 반도체칩과 회로기판 상호간의 접착력도 향상되는 효과가 있다.In addition, the adhesion area of the adhesive layer filled in the space between the bottom pattern and the bending pattern of the semiconductor chip and the circuit board also increases, thereby improving the adhesion between the semiconductor chip and the circuit board.
도1은 종래의 반도체패키지 및 그 실장 상태를 도시한 단면도이다.1 is a cross-sectional view showing a conventional semiconductor package and its mounting state.
도2a 내지 도2c는 본 발명에 의한 회로기판을 도시한 단면도, 평면도 및 저면도이다.2A to 2C are a cross-sectional view, a plan view, and a bottom view showing a circuit board according to the present invention.
도3a 내지 도3c는 본 발명에 의한 회로기판의 제조 방법을 도시한 순차 설명도이다.3A to 3C are sequential explanatory diagrams showing a method for manufacturing a circuit board according to the present invention.
도4는 본 발명에 의한 회로기판을 이용한 반도체패키지를 도시한 단면도이다.4 is a cross-sectional view showing a semiconductor package using a circuit board according to the present invention.
도5는 본 발명에 의한 반도체패키지의 실장 상태를 도시한 단면도이다.5 is a cross-sectional view showing a mounting state of a semiconductor package according to the present invention.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
10; 본 발명에 의한 회로기판 1; 절연층10; A circuit board 1 according to the present invention; Insulation layer
2; 관통공 3; 배선패턴2; Through hole 3; Wiring pattern
3a; 바텀패턴 3b; 절곡패턴3a; Bottom pattern 3b; Bending Pattern
3c; 탑패턴 4; 접착층3c; Top pattern 4; Adhesive layer
100; 본 발명에 의한 반도체패키지 21; 반도체칩100; A semiconductor package 21 according to the present invention; Semiconductor chip
22; 입출력패드 30; 전기적 접속수단22; Input and output pads 30; Electrical connection means
40; 접착층 50; 봉지부40; Adhesive layer 50; Encapsulation
60; 솔더 70; 마더보드60; Solder 70; Motherboard
71; 보드랜드71; Bodland
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0081977A KR100526845B1 (en) | 2000-12-26 | 2000-12-26 | Circuit board and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0081977A KR100526845B1 (en) | 2000-12-26 | 2000-12-26 | Circuit board and its manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| KR20020052583A KR20020052583A (en) | 2002-07-04 |
| KR100526845B1 true KR100526845B1 (en) | 2005-11-08 |
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| KR10-2000-0081977A KR100526845B1 (en) | 2000-12-26 | 2000-12-26 | Circuit board and its manufacturing method |
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| Country | Link |
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| KR (1) | KR100526845B1 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970072341A (en) * | 1996-04-25 | 1997-11-07 | 김광호 | A package in which a bump of a bonding pad and a built-in lead frame are bonded and a manufacturing method thereof |
| KR19990002607U (en) * | 1997-06-27 | 1999-01-25 | 김영환 | Semiconductor package |
| KR20000011430A (en) * | 1998-07-03 | 2000-02-25 | 아오야기 모리키 | Wiring board for bump bonding, semiconductor device assembled from the wiring board and manufacturing method of wiring board for bump bonding |
-
2000
- 2000-12-26 KR KR10-2000-0081977A patent/KR100526845B1/en active IP Right Grant
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970072341A (en) * | 1996-04-25 | 1997-11-07 | 김광호 | A package in which a bump of a bonding pad and a built-in lead frame are bonded and a manufacturing method thereof |
| KR19990002607U (en) * | 1997-06-27 | 1999-01-25 | 김영환 | Semiconductor package |
| KR20000011430A (en) * | 1998-07-03 | 2000-02-25 | 아오야기 모리키 | Wiring board for bump bonding, semiconductor device assembled from the wiring board and manufacturing method of wiring board for bump bonding |
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| KR20020052583A (en) | 2002-07-04 |
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