KR100511820B1 - 상태 버스트 출력을 갖는 동기형 플래시 메모리 - Google Patents

상태 버스트 출력을 갖는 동기형 플래시 메모리 Download PDF

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Publication number
KR100511820B1
KR100511820B1 KR10-2003-7001296A KR20037001296A KR100511820B1 KR 100511820 B1 KR100511820 B1 KR 100511820B1 KR 20037001296 A KR20037001296 A KR 20037001296A KR 100511820 B1 KR100511820 B1 KR 100511820B1
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KR
South Korea
Prior art keywords
register
data
read
memory device
command
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2003-7001296A
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English (en)
Korean (ko)
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KR20030028556A (ko
Inventor
프랭키에 에프. 루흐파르바
Original Assignee
마이크론 테크놀로지, 인크.
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Application filed by 마이크론 테크놀로지, 인크. filed Critical 마이크론 테크놀로지, 인크.
Publication of KR20030028556A publication Critical patent/KR20030028556A/ko
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Publication of KR100511820B1 publication Critical patent/KR100511820B1/ko
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
KR10-2003-7001296A 2000-07-28 2001-07-27 상태 버스트 출력을 갖는 동기형 플래시 메모리 Expired - Fee Related KR100511820B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/626,190 US6728798B1 (en) 2000-07-28 2000-07-28 Synchronous flash memory with status burst output
US09/626,190 2000-07-28
PCT/US2001/023695 WO2002011148A1 (en) 2000-07-28 2001-07-27 Synchronous flash memory with status burst output

Publications (2)

Publication Number Publication Date
KR20030028556A KR20030028556A (ko) 2003-04-08
KR100511820B1 true KR100511820B1 (ko) 2005-09-05

Family

ID=24509337

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2003-7001296A Expired - Fee Related KR100511820B1 (ko) 2000-07-28 2001-07-27 상태 버스트 출력을 갖는 동기형 플래시 메모리

Country Status (9)

Country Link
US (4) US6728798B1 (enExample)
EP (1) EP1305804B1 (enExample)
JP (1) JP3809909B2 (enExample)
KR (1) KR100511820B1 (enExample)
CN (2) CN100578659C (enExample)
AT (1) ATE492880T1 (enExample)
AU (1) AU2001277210A1 (enExample)
DE (2) DE60143700D1 (enExample)
WO (1) WO2002011148A1 (enExample)

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US9741442B2 (en) * 2013-03-12 2017-08-22 Sandisk Technologies Llc System and method of reading data from memory concurrently with sending write data to the memory
US9430411B2 (en) * 2013-11-13 2016-08-30 Sandisk Technologies Llc Method and system for communicating with non-volatile memory
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US11776591B2 (en) * 2019-09-26 2023-10-03 Arm Limited Concurrent access techniques utilizing wordlines with the same row address in single port memory
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Also Published As

Publication number Publication date
US20050289313A1 (en) 2005-12-29
KR20030028556A (ko) 2003-04-08
EP1305804A1 (en) 2003-05-02
CN1466762A (zh) 2004-01-07
JP2004505404A (ja) 2004-02-19
DE60143700D1 (enExample) 2011-02-03
DE1305804T1 (de) 2003-11-27
US6728798B1 (en) 2004-04-27
US7603534B2 (en) 2009-10-13
CN100578659C (zh) 2010-01-06
ATE492880T1 (de) 2011-01-15
US20100088484A1 (en) 2010-04-08
EP1305804B1 (en) 2010-12-22
US8010767B2 (en) 2011-08-30
US7096283B2 (en) 2006-08-22
CN101930794A (zh) 2010-12-29
AU2001277210A1 (en) 2002-02-13
JP3809909B2 (ja) 2006-08-16
WO2002011148A1 (en) 2002-02-07
US20040199713A1 (en) 2004-10-07

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