KR100472033B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR100472033B1 KR100472033B1 KR10-2002-0081993A KR20020081993A KR100472033B1 KR 100472033 B1 KR100472033 B1 KR 100472033B1 KR 20020081993 A KR20020081993 A KR 20020081993A KR 100472033 B1 KR100472033 B1 KR 100472033B1
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- photoresist
- metal
- semiconductor device
- manufacturing
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 239000002184 metal Substances 0.000 claims abstract description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 20
- YPSXFMHXRZAGTG-UHFFFAOYSA-N 4-methoxy-2-[2-(5-methoxy-2-nitrosophenyl)ethyl]-1-nitrosobenzene Chemical compound COC1=CC=C(N=O)C(CCC=2C(=CC=C(OC)C=2)N=O)=C1 YPSXFMHXRZAGTG-UHFFFAOYSA-N 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 description 19
- 238000004140 cleaning Methods 0.000 description 4
- 239000006117 anti-reflective coating Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
금속층을 형성하는 단계; 금속층 위에 감광막을 형성하는 단계; 감광막을 현상, 노광하여 감광막 패턴을 형성하는 단계; 감광막 패턴을 마스크로 하여 금속층을 식각함으로써 금속 패턴을 형성하는 단계; O2, H2O, 및 C2F6 를 포함하는 감광막 제거 가스를 이용하여 감광막 패턴을 제거하는 단계;를 포함하는 반도체 소자의 제조 방법.Forming a metal layer; Forming a photoresist film on the metal layer; Developing and exposing the photoresist film to form a photoresist pattern; Forming a metal pattern by etching the metal layer using the photoresist pattern as a mask; Removing the photoresist pattern using a photoresist removal gas comprising O 2 , H 2 O, and C 2 F 6 .
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 금속 식각 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a metal etching method.
일반적으로 반도체 소자의 제조 공정에서는 원하는 반도체 소자를 제조하기 위해 여러 가지의 회로 패턴들이 형성된다. 그러한 회로 패턴들 중에서 여러 가지 회로의 원활한 전기적 연결을 위해서 형성되는 금속 패턴은 반도체 소자가 고 집적화되고 고속화되면서 점점 작은 선 폭의 금속 패턴이 요구된다. 그러나, 금속 패턴의 형성과정에서는 불필요한 부산물인 폴리머 잔여물(Polymer residue)이 발생한다. 따라서, 폴리머 잔여물의 발생을 억제하거나, 발생된 폴리머 잔여물을 적절히 제거할 수 있는 방법이 요구된다. In general, in the manufacturing process of a semiconductor device, various circuit patterns are formed to manufacture a desired semiconductor device. Among such circuit patterns, metal patterns formed for smooth electrical connection of various circuits require metal patterns with smaller and smaller line widths as semiconductor devices become more integrated and faster. However, in the formation of the metal pattern, polymer residues, which are unnecessary by-products, are generated. Therefore, there is a need for a method capable of suppressing the generation of polymer residues or appropriately removing the generated polymer residues.
특히, 금속 식각 공정에서는 금속 패턴의 선 폭이 작아짐에 따라 폴리머 잔여물이 완전히 제거되지 않고 남아있는 경우가 빈번하다. 이 경우에 마이크로 브리지(Micro Bridge)에 의한 누설 전류의 증가나 단락 등의 문제가 야기된다. 또한, 금속 식각 공정 후에 진행되는 감광막 제거 공정에서 이러한 폴리머 잔여물이 감광막의 제거를 방해하여 감광막 잔여물이 발생하는 문제점을 야기 할 수 있다. In particular, in the metal etching process, as the line width of the metal pattern becomes smaller, the polymer residue is often left without being completely removed. In this case, problems such as an increase in leakage current or short circuit caused by a micro bridge are caused. In addition, in the photoresist removal process performed after the metal etching process, such a polymer residue may interfere with the removal of the photoresist, thereby causing a problem that the photoresist residue occurs.
이러한 문제점을 해결하기 위해 금속 식각 및 감광막 제거를 한 후 습식 클리닝 공정을 두어 폴리머 잔여물을 제거하는 방법이 제기되었다. 그러나, 이는 폴리머 잔여물의 제거에는 탁월하나 금속 패턴의 측벽에 큰 손상을 가하고, 고가의 장비를 사용함에 따른 제조 원가 비용의 상승 등의 문제점이 있다. In order to solve this problem, a method of removing polymer residues has been proposed through a wet cleaning process after metal etching and photoresist removal. However, this is excellent for removing the polymer residue, but it causes a great damage to the sidewall of the metal pattern, there is a problem such as the increase in manufacturing cost by using expensive equipment.
본 발명은 상기 문제점을 해결하기 위한 것으로서, 금속 식각 공정 중에 발생하는 폴리머 잔여물을 제거하는 방법을 제공하는 데 목적이 있다. An object of the present invention is to provide a method for removing polymer residues generated during a metal etching process.
상기 목적을 달성하기 위하여 본 발명은, 금속층을 형성하는 단계; 상기 금속층 위에 감광막을 형성하는 단계; 상기 감광막을 현상, 노광하여 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 마스크로 하여 상기 금속층을 식각함으로써 금속 패턴을 형성하는 단계; O2, H2O, 및 C2F6를 포함하는 감광막 제거 가스를 이용하여 상기 감광막 패턴을 제거하는 단계;를 포함한다.The present invention to achieve the above object, forming a metal layer; Forming a photoresist film on the metal layer; Developing and exposing the photoresist to form a photoresist pattern; Forming a metal pattern by etching the metal layer using the photoresist pattern as a mask; And removing the photoresist pattern by using a photoresist removal gas including O 2 , H 2 O, and C 2 F 6 .
또한, 상기 금속 패턴을 형성하는 단계는 Cl2, BCl2, CHF3 를 포함하는 플라즈마 상태의 식각 가스로 식각한다.In addition, the forming of the metal pattern may be etched with an etching gas in a plasma state including Cl 2 , BCl 2 , CHF 3 .
또한, 상기 감광막 패턴을 제거하는 단계에서 사용되는 감광막 제거 가스는 플라즈마 상태이다. In addition, the photoresist removing gas used in the step of removing the photoresist pattern is in a plasma state.
또한, 상기 감광막 패턴을 제거하는 단계는 5 내지 10 Torr의 압력 하에서 진행한다. In addition, the removing of the photoresist pattern is performed under a pressure of 5 to 10 Torr.
또한, 상기 감광막 패턴을 제거하는 단계에서 첨가되는 상기 C2F6 는 1 내지 10 sccm이다.In addition, the C 2 F 6 added in the step of removing the photoresist pattern is 1 to 10 sccm.
또한, 상기 감광막 패턴을 제거하는 단계는 공정 시간이 30 내지 90 초 내이며, 180 내지 260℃의 온도에서 진행한다. In addition, the step of removing the photosensitive film pattern is within a process time of 30 to 90 seconds, and proceeds at a temperature of 180 to 260 ℃.
이하 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 상세하게 설명하면 다음과 같다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1에 도시된 바와 같이, 본 발명의 일 실시예에 따른 반도체 소자의 제조 방법은 우선 산화막 위에 금속층을 형성한다. 산화막은 웨이퍼(Wafer)가 될 수도 있고, 반도체 소자 제조 공정 중에 형성된 산화막이 될 수도 있다. 그리고, 산화막 위에 형성된 금속층은 스퍼터링(sputtering)의 방법으로 형성할 수 있다. 다음으로, 금속층을 패터닝하기 위해 금속층 위에 감광막을 형성한다. As shown in FIG. 1, a method of manufacturing a semiconductor device according to an embodiment of the present invention first forms a metal layer on an oxide film. The oxide film may be a wafer or an oxide film formed during a semiconductor device manufacturing process. The metal layer formed on the oxide film may be formed by sputtering. Next, a photosensitive film is formed on the metal layer in order to pattern the metal layer.
그리고, 도 2에 도시된 바와 같이, 감광막을 현상, 노광하여 감광막 패턴을 형성한다. 감광막 패턴은 나중에 형성될 금속 패턴과 동일한 패턴으로 형성한다. As shown in FIG. 2, the photoresist film is developed and exposed to form a photoresist pattern. The photosensitive film pattern is formed in the same pattern as the metal pattern to be formed later.
그리고, 도 3에 도시된 바와 같이, 감광막 패턴을 마스크로 하여 식각함으로써 금속 패턴을 형성한다. 이 경우에 Cl2, BCl2, CHF3 를 포함하는 플라즈마 상태의 식각제로 식각한다. 이 때, 감광막 패턴도 식각의 영향으로 형상이 변하고, 금속 패턴의 측벽에 폴리머 잔여물이 발생한다.As shown in FIG. 3, the metal pattern is formed by etching the photosensitive film pattern as a mask. In this case, it is etched with an etchant in the plasma state containing Cl 2 , BCl 2 , CHF 3 . At this time, the photoresist pattern also changes in shape due to etching, and polymer residues are generated on the sidewalls of the metal pattern.
이러한 폴리머 잔여물의 발생에 대해 상세히 설명한다. The generation of such polymer residues is described in detail.
반도체 소자의 고 집적화에 따라 금속 패턴의 선 폭이 작을 것이 요구된다. 선 폭이 작은 금속 패턴을 형성하기 위해서는 감광막의 두께를 줄이고, 감광막의 패턴을 형성함에 있어서, 단파장의 광을 이용하는 것이 바람직하다. 그러나 단파장의 광을 금속층에 조사하면 빛의 반사가 많이 발생하므로 이를 줄이기 위해 산화막 계열의 ARC(Anti- reflect coating)층과 TiN 등을 금속층 위에 형성한다. 이에 따라 금속 식각 공정에서도 ARC 층을 식각하기 위한 CHF3 등의 폴리머 유발 가스(Gas)가 사용된다. 또한, 금속 식각 공정 중에 메탈릭 폴리머(Metallic polymer)도 발생한다. 이러한 폴리머 잔여물은 금속 패턴 사이에 마이크로 브리지를 형성하거나 단락 현상을 일으킬 수 있다.With high integration of semiconductor devices, the line width of the metal pattern is required to be small. In order to form a metal pattern with a small line width, it is preferable to use the light of short wavelength in reducing the thickness of a photosensitive film and forming a pattern of a photosensitive film. However, when a short wavelength of light is irradiated to the metal layer, a lot of light reflection is generated. Thus, an oxide-based anti-reflective coating (ARC) layer and TiN are formed on the metal layer. Accordingly, in the metal etching process, polymer induced gas (Gas) such as CHF 3 is used to etch the ARC layer. In addition, a metallic polymer is also generated during the metal etching process. Such polymer residues can form micro bridges or short circuits between metal patterns.
이러한 폴리머 잔여물을 제거하기 위해, 다음으로, 도 4에 도시된 바와 같이, O2, H2O, 및 C2F6를 포함하는 감광막 제거제를 이용하여 감광막 패턴을 제거한다. 감광막 제거제는 O2, H2O, 및 C2F6 를 포함하는 플라즈마 상태로 이용한다.To remove this polymer residue, the photoresist pattern is then removed using a photoresist remover comprising O 2 , H 2 O, and C 2 F 6 , as shown in FIG. 4. The photoresist remover is used in a plasma state containing O 2 , H 2 O, and C 2 F 6 .
이 경우에 C2F6 는 1 내지 10 sccm 의 소량만을 첨가한다. 이는 플라즈마를 발생시키는 장비가 대부분 석영 재질이므로 C2F6 이 플라즈마 발생 장비를 부식시키는 것을 미연에 방지하기 위함이다. 또한, O2, H2O 는 200 내지 5000 sccm 정도의 양이 바람직하다.In this case C 2 F 6 adds only a small amount of 1 to 10 sccm. This is to prevent C 2 F 6 from corroding the plasma generating equipment because most of the plasma generating equipment is quartz material. In addition, the amount of O 2 and H 2 O is preferably about 200 to 5000 sccm.
이러한 감광막 패턴을 제거하는 단계는 압력을 5 내지 10 Torr로 설정하고, 공정 시간이 30 내지 90 초 내인 것이 바람직하다. 또한, 온도는 180 내지 260℃ 로 설정하고, 500 내지 2000 Watt 의 파워로 공정을 진행하는 것이 바람직하다. Removing the photoresist pattern may be set to a pressure of 5 to 10 Torr, and the process time is within 30 to 90 seconds. In addition, it is preferable to set the temperature to 180-260 degreeC and to advance a process by the power of 500-2000 Watt.
이러한 감광막 패턴을 제거하는 단계를 거친 경우에는, 도 5에 도시된 바와 같이, 금속 패턴의 측벽과 선 폭에는 폴리머 잔여물이 남아 있지 않고 완전히 제거된다. 따라서, 별도의 습식 클리닝 공정이 요구되지 않는다. In the case where the photoresist pattern is removed, as shown in FIG. 5, polymer residues are completely removed on the sidewalls and line widths of the metal pattern. Thus, no separate wet cleaning process is required.
본 발명은 첨부된 도면에 도시된 일 실시예를 참고로 설명되었으나 이는 예시적인 것에 불과하며, 당해 기술분야에서 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 수 있을 것이다. 따라서, 본 발명의 진정한 보호범위는 첨부된 청구범위에 의해서만 정해져야 할 것이다.Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.
본 발명에 따른 반도체 소자의 제조 방법은 감광막 제거 공정 중에 폴리머 잔여물 제거에 효과가 큰 C2F6 을 사용함으로써 폴리머 잔여물에 의한 누설 전류의 증가 및 단락 현상을 방지 할 수 있다.In the method of manufacturing a semiconductor device according to the present invention, by using C 2 F 6, which is effective in removing polymer residues during the photoresist removal process, it is possible to prevent an increase in leakage current and short circuit caused by the polymer residues.
또한, 별도의 클리닝 공정이 필요하지 않아서 공정 시간이 단축되고, 별도의 클리닝 장비을 사용하지 않음으로써 제조 원가의 상승을 방지할 수 있다는 장점이 있다. In addition, since a separate cleaning process is not required, the process time is shortened, and an increase in manufacturing cost can be prevented by not using a separate cleaning equipment.
도 1은 본 발명의 일 실시예에 따른 반도체 소자의 제조 방법을 도시한 도면으로서, 산화막 위에 금속층, 감광막이 형성된 것을 나타낸 단면도이고,1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein a metal layer and a photosensitive film are formed on an oxide film.
도 2는 도 1의 다음 단계로서, 감광막 패턴이 형성된 것을 나타낸 단면도이고, FIG. 2 is a cross-sectional view illustrating a photoresist pattern formed as a next step of FIG. 1;
도 3은 도 2의 다음 단계로서, 금속 패턴이 형성된 것을 나타낸 단면도이고, 3 is a sectional view showing a metal pattern formed as a next step of FIG.
도 4는 도 3의 다음 단계로서, 감광막을 제거하는 것을 나타낸 단면도이고,4 is a sectional view showing the removal of the photosensitive film as a next step of FIG.
도 5는 도 4의 다음 단계로서, 감광막 및 폴리머 잔유물이 완전히 제거된 상태를 나타낸 단면도이다. 5 is a cross-sectional view illustrating a state in which the photoresist film and the polymer residues are completely removed as a next step of FIG. 4.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 ; 산화막 20a ; 금속층 패턴10; Oxide film 20a; Metal layer pattern
30a ; 감광막 패턴 40 ; 폴리머 잔유물 30a; Photosensitive film pattern 40; Polymer residues
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0081993A KR100472033B1 (en) | 2002-12-20 | 2002-12-20 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0081993A KR100472033B1 (en) | 2002-12-20 | 2002-12-20 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040055349A KR20040055349A (en) | 2004-06-26 |
| KR100472033B1 true KR100472033B1 (en) | 2005-03-10 |
Family
ID=37348039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2002-0081993A KR100472033B1 (en) | 2002-12-20 | 2002-12-20 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100472033B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180091297A (en) | 2017-02-06 | 2018-08-16 | 이상운 | Flow regulator for medical infusion set |
| KR102220569B1 (en) | 2020-09-24 | 2021-02-26 | 류양렬 | Infusion line connection device |
-
2002
- 2002-12-20 KR KR10-2002-0081993A patent/KR100472033B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180091297A (en) | 2017-02-06 | 2018-08-16 | 이상운 | Flow regulator for medical infusion set |
| KR102220569B1 (en) | 2020-09-24 | 2021-02-26 | 류양렬 | Infusion line connection device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040055349A (en) | 2004-06-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100472033B1 (en) | Manufacturing method of semiconductor device | |
| JP4335441B2 (en) | Etching process of organic antireflection coating | |
| US5840203A (en) | In-situ bake step in plasma ash process to prevent corrosion | |
| KR100484896B1 (en) | Method for preventing metal-corrosion in the metal-etch process | |
| KR19990057882A (en) | Semiconductor device manufacturing method | |
| KR100271915B1 (en) | Method of stripping photoresist | |
| KR0137619B1 (en) | Manufacturing method of semiconductor device | |
| CN101740374A (en) | Method for etching more than 10mu m of dielectric layer | |
| KR20100077858A (en) | Method for forming metal line of semiconductor device | |
| KR0172232B1 (en) | Method of forming metal pattern | |
| KR0168166B1 (en) | Polymer removing method of semiconductor device | |
| KR100217904B1 (en) | Resist strip method | |
| KR100205096B1 (en) | Removing method of photoresist film in the semiconductor device | |
| KR100267771B1 (en) | Method for manufacturing semiconductor material | |
| KR100568098B1 (en) | Method for forming metal pattern | |
| KR20020007589A (en) | Ashing method using CF4gas | |
| KR100520849B1 (en) | Method for forming metal pattern in semiconductor device with low selectivity to photoresist | |
| KR20030091452A (en) | Method of forming pattern inhibiting pitting effect | |
| KR960015485B1 (en) | Foot eleminating method of barrier metal | |
| KR100265340B1 (en) | Method of fabricating semiconductor device | |
| KR100186508B1 (en) | Polymer removing method | |
| KR100464660B1 (en) | Etch byproduct removal method of semiconductor device | |
| KR100332647B1 (en) | Method of forming a contact hole in a semiconductor device | |
| KR20000027241A (en) | Method for forming metal wires of semiconductor devices | |
| KR100284311B1 (en) | Method of manufacturing semiconductor device for improving via contact resistance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20080103 Year of fee payment: 4 |
|
| LAPS | Lapse due to unpaid annual fee |