KR0172232B1 - Method of forming metal pattern - Google Patents
Method of forming metal pattern Download PDFInfo
- Publication number
- KR0172232B1 KR0172232B1 KR1019940034122A KR19940034122A KR0172232B1 KR 0172232 B1 KR0172232 B1 KR 0172232B1 KR 1019940034122 A KR1019940034122 A KR 1019940034122A KR 19940034122 A KR19940034122 A KR 19940034122A KR 0172232 B1 KR0172232 B1 KR 0172232B1
- Authority
- KR
- South Korea
- Prior art keywords
- metal layer
- film
- pattern
- reflection film
- plasma
- Prior art date
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 43
- 239000002184 metal Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000000460 chlorine Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 6
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 230000018109 developmental process Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 금속패턴 형성방법에 관한 것으로, 반도체기판 상부에 금속층을 형성하고, 상기 금속층 상부에 반사방지막을 형성한 다음, 상기 반사방지막을 염소분위기의 플라즈마로 식각하고, 상기 반사방지막과 금속층 계면에 형성된 절연막을 삼염화붕소 분위기의 플라즈마로 식각하고, 상기 금속층을 염소분위기의 플라즈마로 식각하고, 상기 감광막 패턴을 제거함으로써 상기 반도체 기판에 잔류물을 남기지 않고 금속패턴을 형성하여 후속공정을 용이하게 함으로써 반도체소자의 수율을 향상시키고 반도체 소자의 신뢰성을 향상시키는 기술이다.The present invention relates to a method of forming a metal pattern, wherein a metal layer is formed on a semiconductor substrate, an anti-reflection film is formed on the metal layer, and the anti-reflection film is etched by plasma in a chlorine atmosphere, and the anti-reflection film and the metal layer interface are formed. The formed insulating film is etched with plasma of boron trichloride atmosphere, the metal layer is etched with plasma of chlorine atmosphere, and the photosensitive film pattern is removed to form a metal pattern without leaving residue on the semiconductor substrate, thereby facilitating subsequent processes. It is a technique for improving the yield of the device and the reliability of the semiconductor device.
Description
제1a도 내지 제1c도는 본 발명의 실시예에 따른 금속패턴 형성공정을 도시한 단면도.1A to 1C are cross-sectional views illustrating a metal pattern forming process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 기판 13 : 하부절연층11 semiconductor substrate 13 lower insulating layer
17 : 알루미늄막 19 : 반사방지막17: aluminum film 19: antireflection film
21 : 감광막 패턴 23 : 산화막21: photosensitive film pattern 23: oxide film
25 : 크랙25: crack
본 발명은 금속패턴 형성방법에 관한 것으로, 특히 반도체소자의 고집적화에 따라 반사방지막을 사용한 금속패턴 형성시 상기 반사방지막과 금속층의 응력으로 인하여 발생하는 문제점을 방지하기 위하여 플라즈마를 이용한 식각방법으로 균일한 금속패턴을 형성함으로써 반도체 소자의 수율 및 신뢰성을 향상시키는 기술에 관한 것이다.The present invention relates to a method of forming a metal pattern, in particular, in order to prevent the problems caused by stress of the anti-reflection film and the metal layer when forming a metal pattern using an anti-reflection film according to the high integration of the semiconductor device uniform by an etching method using a plasma The present invention relates to a technique for improving the yield and reliability of semiconductor devices by forming metal patterns.
반도체 소자가 고집적화됨에 따라 노광공정시 사용되는 광원의 반사에 의하여 측면에 형성된는 패턴에 손상을 주게된다. 이르 방지하기 위하여 식각되는 층 하부에 반사방지막을 형성한다. 이때, 상기 반사방지막은 금속 계통의 물질로 형성된다. 예를 들어, TiN 또는 Ti/TiN의 적층구조를 형성한다.As the semiconductor devices are highly integrated, damage to the patterns formed on the side surface by reflection of the light source used in the exposure process is damaged. In order to prevent this, an anti-reflection film is formed under the etched layer. In this case, the anti-reflection film is formed of a metal-based material. For example, a stacked structure of TiN or Ti / TiN is formed.
반도체기판 상부에 금속패턴을 형성하는 경우, 금속층 상부에 반사방지막을 형성하고, 그 상부에 감광막 패턴을 형성한 다음, 상기 감광막 패턴을 이용한 식각공정으로 상기 금속층을 식각한다.When the metal pattern is formed on the semiconductor substrate, an anti-reflection film is formed on the metal layer, a photoresist pattern is formed on the metal layer, and the metal layer is etched by an etching process using the photoresist pattern.
여기서, 상기 금속층은 알루미늄이 사용된 것이다. 이때, 상기 반사방지막과 금속층의 열팽창계수가 상이하여 발생되는 응력으로 인하여 크랙(crack)이 발생한다. 그리고, 감광막 패턴을 형성하기 위한 현상공정 시 현상액이 상기 크랙을 통하여 상기 금속층과 반응하여 금속층의 표면을 손상시킨다. 그로 인하여 일종의 산화막인 Al2O3가 형성된다.Here, the metal layer is aluminum is used. In this case, cracks are generated due to stresses generated by different thermal expansion coefficients of the anti-reflection film and the metal layer. In the developing process for forming the photoresist pattern, the developer reacts with the metal layer through the crack to damage the surface of the metal layer. As a result, Al 2 O 3 , which is a kind of oxide film, is formed.
그 다음에, 상기 감광막 패턴을 마스크로하여 상기 금속층을 식각하면 상기 금속층이 균일하게 제거되지 않고 잔류물을 남긴다. 그리고, 상기 잔류물은 후속공정에 어려움을 주어 반도체소자의 수율 및 신뢰성을 저하시키는 문제점이 있다.Subsequently, when the metal layer is etched using the photoresist pattern as a mask, the metal layer is not uniformly removed but leaves a residue. In addition, the residue may cause difficulty in subsequent processes, thereby lowering the yield and reliability of the semiconductor device.
따라서, 본 발명은 종래 기술의 문제점을 해결하기 위하여, 감광막 패턴을 형성하고, 플라즈마를 이용한 식각공정으로 반사방지막을 식각하고, 반사방지막과 금속층의 경계부에 형성된 절연막을 제거하고 금속층을 식각함으로써 잔류물을 남기지 않고 금속패턴을 형성하여 반도체소자의 수율과 신뢰성을 향상시키는 금속패턴 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the problems of the prior art, the present invention provides a residue by forming a photoresist pattern, etching an antireflection film by an etching process using plasma, removing an insulating film formed at the boundary between the antireflection film and the metal layer, and etching the metal layer. It is an object of the present invention to provide a metal pattern forming method for improving the yield and reliability of a semiconductor device by forming a metal pattern without leaving.
이상의 목적을 달성하기 위해 본 발명에 따른 금속패턴 형성방법의 특징은, 하부절연층이 형성된 반도체기판 상부에 금속층과 반사방지막을 형성하는 공정과, 상기 반사방지막 상부에 노광 및 현상공정을 이용하여 감광막 패턴을 형성하되, 상기 현상공정시 현상액이 반사방지막과 금속층의 응력차이로 유발된 크랙을 통하여 상기 금속층과 반응하여 산화막을 형성하는 공정과, 상기 감광막 패턴을 마스크로 하여 상기 반사방지막을 식각하되, 염소 분위기의 플라즈마를 이용하여 실시하는 공정과, 상기 산화막을 삼염화붕소 분위기의 플라즈마로 제거하는 공정과, 상기 감광막 패턴을 마스크로하여 상기 금속층을 식각하는 공정과, 상기 감광막 패턴을 제거하는 공정을 포함하는 것이다.In order to achieve the above object, a feature of the metal pattern forming method according to the present invention is to form a metal layer and an antireflection film on the semiconductor substrate on which the lower insulating layer is formed, and a photoresist film using an exposure and development process on the antireflection film. Forming a pattern, during the development process, the developer reacts with the metal layer to form an oxide film through cracks caused by the stress difference between the anti-reflection film and the metal layer, and the anti-reflection film is etched using the photosensitive film pattern as a mask, Performing plasma using a chlorine atmosphere, removing the oxide film with a plasma of boron trichloride atmosphere, etching the metal layer using the photosensitive film pattern as a mask, and removing the photosensitive film pattern. It is.
이하,첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1c도는 본 발명의 실시예에 따른 금속패턴 형성공정을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a metal pattern forming process according to an embodiment of the present invention.
제1a도를 참조하면, 반도체기판(11)상부에 하부절연층(13)을 형성한다. 그리고 상기 하부절연층(13) 상부에 알루미늄막(17)을 형성한다 .그리고, 반사방지막(19)을 형성한다. 이때, 상기 반사방지막(19)은 Ti로 형성된 것이다. 그 후에, 상기 반사방지막(19) 상부에 감광막 패턴(21)을 형성한다. 이때, 상기 감광막 패턴(21)은 금속패턴을 형성하기 위한 것이다.Referring to FIG. 1A, a lower insulating layer 13 is formed on the semiconductor substrate 11. An aluminum film 17 is formed on the lower insulating layer 13, and an anti-reflection film 19 is formed. At this time, the anti-reflection film 19 is formed of Ti. Thereafter, the photoresist pattern 21 is formed on the anti-reflection film 19. In this case, the photoresist pattern 21 is for forming a metal pattern.
여기서, 상기 알루미늄막(17)과 반사방지막(19)의 경계부에 일종의 산화막(23)인 Al2O3가 형성된다. 상기 산화막(23)은 상기 알루미늄막(17)과 반사방지막(19)의 열팽창계수 차이로 인한 응력으로 발생된 크랙(25)을 통하여 상기 감광막 패턴(21)을 형성하기 위한 현상공정시 현상액이 침투되어 형성된 것이다. 일반적으로 상기 현상액은 알칼리성이다.Here, Al 2 O 3 , which is a kind of oxide film 23, is formed at the boundary between the aluminum film 17 and the anti-reflection film 19. The oxide film 23 penetrates the developer during the development process for forming the photoresist pattern 21 through the crack 25 generated by the stress due to the difference in thermal expansion coefficient between the aluminum film 17 and the antireflection film 19. It is formed. Generally, the developer is alkaline.
제1b도를 참조하면, 상기 감광막 패턴(21)을 마스크로하여 상기 반사방지막(19) 식각공정은 염소(Cl2)분위기의 플라즈마를 이용한 식각공정으로 실시된 것이다.Referring to FIG. 1B, the etching process of the anti-reflection film 19 using the photoresist pattern 21 as a mask is performed by an etching process using plasma in a chlorine (Cl 2 ) atmosphere.
그 다음에, 상기 크랙(25)을 통하여 형성된 상기 산화막(23)을 제거한다. 여기서, 상기 산화막(23)제거공정은 삼염화붕소(BCl3)분위기의 플라즈마를 이용한 식각공정으로 상기 산화막(23)을 제거한다. 이때, 상기 산화막(23)제거시 공정은 싱글챔버(single chamber)에서 RF전력을 500 내지 2000와트(watt)로 하고, 압력은 100 내지 500mTorr 로 한다.Next, the oxide film 23 formed through the crack 25 is removed. Here, the oxide film 23 removal process is to remove the oxide film 23 by an etching process using a plasma of boron trichloride (BCl 3 ) atmosphere. At this time, the process of removing the oxide film 23 is to set the RF power to 500 to 2000 watts (watt) in a single chamber (single chamber), the pressure is 100 to 500mTorr.
그 후에 상기 감광막 패턴(21)을 마스크로하여 상기 알루미늄막(17)을 식각한다. 이때, 상기 알루미늄막(17) 식각공정은 염소부위기의 플라즈마를 이용하여 실시된 것이다.Thereafter, the aluminum film 17 is etched using the photoresist pattern 21 as a mask. At this time, the etching process of the aluminum film 17 is performed by using a plasma of the chlorine site.
그 다음에, 상기 감광막 패턴(21)을 제거함으로써 잔류물이 발생되지 않은 금속패턴을 형성한다.Next, the photoresist pattern 21 is removed to form a metal pattern in which no residue is generated.
이상에서 설명한 바왁 같이 본 발명에 따른 금속패턴 형성방법은, 싱글챔버를 이용하는 금속패턴 형성공정시 금속잔류물을 발생시키지 않고 형성함으로써 반도체소자의 수율과 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, the metal pattern forming method according to the present invention has an advantage of improving the yield and reliability of the semiconductor device by forming the metal pattern without generating metal residues in the metal pattern forming process using the single chamber.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940034122A KR0172232B1 (en) | 1994-12-14 | 1994-12-14 | Method of forming metal pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940034122A KR0172232B1 (en) | 1994-12-14 | 1994-12-14 | Method of forming metal pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960026271A KR960026271A (en) | 1996-07-22 |
| KR0172232B1 true KR0172232B1 (en) | 1999-03-30 |
Family
ID=19401411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940034122A KR0172232B1 (en) | 1994-12-14 | 1994-12-14 | Method of forming metal pattern |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0172232B1 (en) |
-
1994
- 1994-12-14 KR KR1019940034122A patent/KR0172232B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960026271A (en) | 1996-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR0172232B1 (en) | Method of forming metal pattern | |
| US5840203A (en) | In-situ bake step in plasma ash process to prevent corrosion | |
| GB2286721A (en) | Method for fabricating semiconductor device | |
| KR100472033B1 (en) | Manufacturing method of semiconductor device | |
| KR100271915B1 (en) | Method of stripping photoresist | |
| KR20060015949A (en) | Method for forming metal patterns | |
| KR100568098B1 (en) | Method for forming metal pattern | |
| KR100329787B1 (en) | A method for eleminating of photoresistor in semiconductor device | |
| US6375859B1 (en) | Process for resist clean up of metal structures on polyimide | |
| KR0137619B1 (en) | Manufacturing method of semiconductor device | |
| KR100236077B1 (en) | Manufacturing method for semiconductor material | |
| KR100217904B1 (en) | Resist strip method | |
| KR960015485B1 (en) | Foot eleminating method of barrier metal | |
| KR100368985B1 (en) | Method for patterning metal film in fabrication process of semiconductor device | |
| KR100632644B1 (en) | Method of etching a polysilicon layer in a semiconductor device | |
| KR100265340B1 (en) | Method of fabricating semiconductor device | |
| KR0156148B1 (en) | Fabrication method of semiconductor device | |
| KR100408847B1 (en) | Method for removing residence in process of semiconductor manufacture | |
| KR20010093006A (en) | Method of processing wafer edge | |
| KR950009284B1 (en) | Fine patterning method | |
| KR100237025B1 (en) | Metal layer etching method for semiconductor material | |
| KR0131729B1 (en) | Method for forming metal connection layer | |
| KR100447986B1 (en) | Manufacturing method of color filter of optical sensing element | |
| JPH04157723A (en) | Dry etching method of aluminum film | |
| KR0168166B1 (en) | Polymer removing method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20081006 Year of fee payment: 11 |
|
| LAPS | Lapse due to unpaid annual fee |