KR100368985B1 - Method for patterning metal film in fabrication process of semiconductor device - Google Patents
Method for patterning metal film in fabrication process of semiconductor device Download PDFInfo
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- KR100368985B1 KR100368985B1 KR1019950058235A KR19950058235A KR100368985B1 KR 100368985 B1 KR100368985 B1 KR 100368985B1 KR 1019950058235 A KR1019950058235 A KR 1019950058235A KR 19950058235 A KR19950058235 A KR 19950058235A KR 100368985 B1 KR100368985 B1 KR 100368985B1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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Abstract
Description
본 발명은 반도체 디바이스 제조공정의 금속층 패터닝(Patterning) 방법에 관한 것으로, 특히 건식각을 이용하여 고융점 금속총의 패터닝 시 발생되는 폴리머(Polymer)를 효과적으로 제거하기에 적당한 반도체 디바이스 제조공정의 금속충 패터닝(Patterning) 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of patterning a metal layer in a semiconductor device manufacturing process. In particular, metal filling in a semiconductor device manufacturing process suitable for effectively removing a polymer generated during patterning of a high melting point metal gun using dry etching It relates to a patterning method.
일반적으로 반도체 디바이스 금속 배선 등의 형성을 위한 금속층 패터닝은, 반도체 기판 위에 금속층을 형성한 후, 식각가스의 플라즈마로 건식각을 수행하고, 식각 공정에서 식각 마스크로 사용된 포토레지스트와 건식각시 발생된 폴리머륵 제거하므로써, 금속배선라인 등을 형성하게 되는 과정이다.In general, metal layer patterning for forming a semiconductor device metal wiring is performed during dry etching after forming a metal layer on a semiconductor substrate, performing dry etching with plasma of an etching gas, and using a photoresist used as an etching mask in an etching process. By removing the polymer, a metal wiring line is formed.
제 1도 내지 제 3도는 종래의 금속층 패터닝 방법을 설명하기 도시한 도면으로써, 제 1도는 종래 방법의 공정 플로우차트(Flowchart)이고, 제 2도는 반도체 소자 일부를 도시한 종래의 공정 단면도이고, 제 3도는 종래의 금속층 패터닝 방법에 의해 형성된 금속배선라인의 사진이다.1 through 3 illustrate a conventional metal layer patterning method, in which FIG. 1 is a process flowchart of the conventional method, and FIG. 2 is a conventional process cross-sectional view showing a part of a semiconductor device. 3 is a photograph of a metal wiring line formed by a conventional metal layer patterning method.
종래의 금속층 패터닝 방법은 제 1도에 도시한 바와 같이, 반도체 기판상에 형성된 금속층 상에 포토레지스트 마스크를 형성하고 건식각을 실시한후, 포토레지스트론 제거한 다음, 폴리머를 제거하는 단계로 구성되어 있다.In the conventional metal layer patterning method, as shown in FIG. 1, a photoresist mask is formed on a metal layer formed on a semiconductor substrate, subjected to dry etching, the photoresist is removed, and then the polymer is removed. .
즉, 제 2도의 (가)와 같이 실리콘 기판(11) 위에 형성된 비피에스지(BPSG)와같은 절연막(12) 상의 전면에 스퍼터링을 이용하여 금속층(13) 예로써 TiN(13-1)과 W(13-2)을 형성한 다음, 그 위에 포토레지스트 마스크(14)를 형성한다.That is, as shown in FIG. 2A, TiN 13-1 and W (for example, the metal layer 13 are formed by sputtering on the entire surface of the insulating film 12, such as BPSG formed on the silicon substrate 11). 13-2), and then a photoresist mask 14 is formed thereon.
이어 10℃ 내지 40℃ 정도의 상온에서 SF6가스를 이용한 플라즈마로 W층(13-2)을 식각하고 연속하여 Cl2+ N2가스를 이용한 플라즈마로 TiN층(13-1)을 식각하여 제 2도의 (나)와 같이 형성한다. 도면부호(13-1',2')로 이루어진 (13')은 금속배선라인이며, 도시한 바와 같이 식각 후 금속배선라인(13') 측면과 포토레지스트 마스크(14) 표면 등에 폴리머(Polymer)(15)가 잔류하게 된다.Subsequently, the W layer 13-2 is etched by plasma using SF 6 gas at room temperature of about 10 ° C. to 40 ° C., and the TiN layer 13-1 is etched by plasma using Cl 2 + N 2 gas. It is formed as (b) of 2 degrees. (13 ') consisting of reference numerals 13-1' and 2 'is a metal wiring line, and as shown, a polymer is formed on the side of the metal wiring line 13' and the surface of the photoresist mask 14 after etching. (15) remains.
이어서, 제 2도의 (다)와 같이 O2/N2가스를 이용하여 포토레지스트 마스크를 제거한 후, NMD III 화학 용액을 이용하여 폴리머(15)를 제거하여 제 2도의 (라)와 같이 된다.Subsequently, the photoresist mask is removed using an O 2 / N 2 gas as shown in FIG. 2C, and then the polymer 15 is removed using an NMD III chemical solution to obtain the same as in FIG.
그러나 종래의 방법은 약 250℃ 정도의 고온 공정인 포토레지스트 마스크 제거공정을 먼저 수행한 후 폴리머 제거작업을 하게 되므로써, 포토레지스트 마스크 제거시 폴리머가 경화되어 제 2도의 (라)와 같이 폴리머 제거 작업 후에도 폴리머가 완전히 제거되지 않고 잔존 폴리머(15')가 남게 되는 문제점이 있다. 더욱이 포토레지스트 제거 작업 중에도 미량의 폴리머가 발생되고 있으며, 제 3도의 사진에서 알수 있는 바와 같이 금속라인 측면의 잔존 폴리머가 넘어져서 배선 라인간 단락(Short)를 일으키게 된다.However, in the conventional method, since the photoresist mask removal process, which is a high temperature process of about 250 ° C., is first performed, the polymer removal operation is performed, so that the polymer is cured when the photoresist mask removal is performed. Even after the polymer is not completely removed, the remaining polymer 15 'remains. In addition, a small amount of polymer is generated during the photoresist removal operation, and as shown in the photograph of FIG. 3, the remaining polymer on the side of the metal line falls, causing short circuit between the wiring lines.
이에 본 발명은 상술한 종래 방법의 문제점을 해결하기 위해 안출된 것으로써, 건식각 시 발생된 폴리머를 경화되기 전에 제거하므로써 일련의 금속층 패터링공정 후에 폴리머의 잔류량이 거의 없는 금속층 패터닝 방법을 제공하고자 한다.Accordingly, the present invention has been made to solve the above-described problems of the conventional method, and to provide a metal layer patterning method having little residual amount of polymer after a series of metal layer patterning processes by removing the polymer generated during dry etching before curing. do.
본 발명의 반도체 디바이스 제조공정의 금속층 패터닝 방법은, 반도체기판 상에 형성된 금속층 위에 포토레지스트 마스크를 형성하고, 상기 금속층을 건식각한 후, 상기 포토레지스트 마스크를 제거하기 전에 건식각시에 발생된 폴리머를 먼저 제거하는 것이 특징이다.The metal layer patterning method of the semiconductor device manufacturing process of the present invention comprises forming a photoresist mask on a metal layer formed on a semiconductor substrate, dry etching the metal layer, and then removing the polymer generated during dry etching before removing the photoresist mask. It is characterized by removing first.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제 4도 내지 제 6도는 본 발명에 따른 금속층 패터닝 방법의 일실시예를 설명하기 도시한 도면으로써, 제 4도는 본 발명에 따른 일실시예의 공정 플로우차트(Flowchart)이고, 제 5도는 반도체 소자 일부를 도시한 본 발명에 따른 일실시예의 공정 단면도이고, 제 6도는 본 발명의 금속층 패터닝 방법의 일실시예에 의해 형성된 금속배선라인의 사진이다.4 to 6 illustrate one embodiment of a metal layer patterning method according to the present invention, and FIG. 4 is a process flowchart of one embodiment according to the present invention, and FIG. 5 is a part of a semiconductor device. 6 is a cross-sectional view showing a process of an embodiment according to the present invention, and FIG. 6 is a photograph of a metal wiring line formed by an embodiment of the metal layer patterning method of the present invention.
본 발명에 따른 일실시예의 금속층 패터링 방법은 제 4도에 도시한 바와 같이, 반도체 기판 상에 형성된 금속층 상에 포토레지스트 마스크를 형성하고 건식각을 실시한 후, 폴리머 제거단계를 실시한 후, 포토레지스트를 제거하는 단계를 수행하게 되며, 포토레지스트 제거후에 재차 폴리머를 제거하는 단계를 포함하여 이루어진다.In the metal layer patterning method according to the embodiment of the present invention, as shown in FIG. 4, after forming a photoresist mask on the metal layer formed on the semiconductor substrate, performing dry etching, and then performing a polymer removal step, the photoresist Removing the polymer, and removing the polymer after removing the photoresist.
즉, 제 5도의 (가)와 같이 실리콘 기판(21) 위에 형성된 비피에스지(BPSG)와 같은 절연막(22) 상의 전면에 스퍼터링을 이용하여 금속층(23) 예로써 TiN층(23-1)과 W층(23-2)을 형성한 다음, 그 위에 포토레지스트 마스크(24)를 형성한다.That is, as shown in FIG. 5A, the TiN layers 23-1 and W are formed by sputtering on the entire surface of the insulating film 22 such as BPSG formed on the silicon substrate 21, for example. After forming layer 23-2, a photoresist mask 24 is formed thereon.
이어, 10℃ 내지 40℃ 정도의 상온에서, 90sccm의 SF6가스를 이용한 플라즈마로 80mT 및 450W등의 공정 조건에서 W막을 식각하고, 연속하여 C12+ N2가스를 이용한 플라즈마로 TiN막을 식각하여 제 5도의 (나)와 같이 형성하며, 도면부호(23-1',2')로 이루어진 (23')는 건식각에 의해 형성된 금속배선라인을 나타낸다. 이때, Cl2는 35sccm, N2는 20sccm이며 90mT, 450W 등의 공정조건이다.Subsequently, at room temperature of about 10 ° C. to 40 ° C., the W film is etched using a plasma using 90 sccm of SF 6 gas at 80 mT and 450 W, and the TiN film is subsequently etched by plasma using C1 2 + N 2 gas. Formed as shown in (b) of FIG. 5, reference numeral 23 'consisting of reference numerals 23-1' and 2 'denotes a metal wiring line formed by dry etching. At this time, Cl 2 is 35sccm, N 2 is 20sccm and the process conditions, such as 90mT, 450W.
종래와 마찬가지로 식각 후 금속배선라인(23') 측면과 포토레지스트 마스크(24)표면 등에 폴리머(25)가 잔류하게 되는데, 제 5도의 (다)와 같이 NMD-III 화학용액을 이용하여 플리머 제거작업을 수행한다. 즉, 포토레지스트 마스크 제거 공정 등과 같은 고온 공정에 의해 폴리머가 경화되기 전에 폴리머 제거 작업을 수행하는 것으로써, 건식각 후 발생된 폴리머의 거의 전부가 제거되게 된다.As in the prior art, the polymer 25 remains on the metal wiring line 23 'side and the photoresist mask 24 surface after etching. As shown in FIG. 5C, the polymer is removed using NMD-III chemical solution. Do the work. That is, by performing the polymer removal operation before the polymer is cured by a high temperature process such as a photoresist mask removal process, almost all of the polymer generated after dry etching is removed.
그다음, 제 5도의 (라)와 같이 O2/N2가스를 이용하여 포토레지스트 마스크를 제거한다. 이때 종래와 마찬가지로 미량의 폴리머가 발생하여 제 5도의 (다)로 도시한 폴리머 제거 공정에서 미제거된 폴리머와 함께 잔존 폴리머(25')가 생길 가능성이 있으며, 따라서 재차 NMD-III 화학용액을 이용하여 폴리머 제거작업을 수행하면 제 5도의 (마)와 같이 플리머가 거의 없는 금속 배선라인(23')을 형성할 수 있게 된다.Then, the photoresist mask is removed using O 2 / N 2 gas as shown in FIG. At this time, as in the prior art, a small amount of polymer may be generated, and the remaining polymer 25 'may be formed together with the unremoved polymer in the polymer removal process shown in FIG. 5C. Thus, the NMD-III chemical solution is used again. By performing the polymer removal operation, it is possible to form a metal wiring line 23 ′ having almost no polymers as shown in FIG.
본 발명에 따른 일실시예의 금속층 패터닝 방법에 의해 형성된 금속라인의 사진이 제 6도에 나타나 있다. 즉, 제 6도에서 알 수 있는 바와 같이 본 발명의 방법은, 폴리머 제거 작업보다 고온공정인 포토레지스트 제거 공정을 먼저 실시하여폴리머가 경화되므로써 폴리머 제거가 불충분한 종래의 방법과는 달리, 건식각 공정 직후에 즉, 폴리머의 경화 전에 제거하므로써 대부분의 폴리머가 제거되며, 또한 포토레지스트 제거공정 후에 재차 미량의 잔존 폴리머를 제거하므로, 거의 완벽한 폴리머 제거를 이룰 수 있는 효과가 있다.A photograph of a metal line formed by the metal layer patterning method of one embodiment according to the present invention is shown in FIG. That is, as can be seen in FIG. 6, the method of the present invention is different from the conventional method in which the polymer is hardened by performing the photoresist removal process, which is a high temperature process, rather than the polymer removal operation, thereby curing the polymer. Most of the polymer is removed immediately after the process, i.e., prior to curing of the polymer, and also after removing the trace amount of remaining polymer again after the photoresist removal process, there is an effect of achieving almost perfect polymer removal.
제 1도는 종래의 반도체 디바이스 제조공정의 금속층 패터닝 방법을 설명하기 위해 도시한 공정 플로우차트(Flowchart).1 is a process flowchart shown for explaining a metal layer patterning method of a conventional semiconductor device manufacturing process.
제 2도는 종래의 반도체 디바이스 제조공정의 금속층 패터닝 방법을 설명하기 위해 반도체 소자 일부를 도시한 공정단면도.2 is a process cross-sectional view showing a portion of a semiconductor device to explain a metal layer patterning method of a conventional semiconductor device manufacturing process.
제 3도는 종래의 반도체 디바이스 제조공정의 금속층 패터닝 방법에 의해 형성된 금속 배선 라인의 사진.3 is a photograph of a metal wiring line formed by a metal layer patterning method of a conventional semiconductor device manufacturing process.
제 4도는 본 발명에 따른 일실시예의 반도체 디바이스 제조공정의 금속층 패터닝 방법을 설명하기 위해 도시한 공정 플로우차트(Flowchart).4 is a process flowchart shown for explaining a metal layer patterning method of a semiconductor device manufacturing process of an embodiment according to the present invention.
제 5도는 본 발명에 따른,일실시예의 반도체 디바이스 제조공정의 금속층 패터닝 방법을 설명하기 위해 반도체 소자 일부를 도시한 공정단면도.5 is a cross-sectional view of a portion of a semiconductor device for explaining a method of patterning a metal layer in a semiconductor device manufacturing process in accordance with an embodiment of the present invention.
제 6도는 본 발명에 따른 일실시예의 반도체 디바이스 제조공정의 금속층 패터닝 방법에 의해 형성된 금속 배선 라인의 사진.6 is a photograph of a metal wiring line formed by a metal layer patterning method of a semiconductor device manufacturing process of an embodiment according to the present invention.
※ 도면의 주요부분에 대한 부호의 설명 ※※ Explanation of code about main part of drawing ※
11. 21. 실리콘 기판 12. 22. 절연막11.21.Silicone substrate 12.22.Insulation film
13, 23. 금속층 13', 23'. 금속배선라인13, 23. Metal layers 13 ', 23'. Metal wiring line
13-1. 13-1'. 23-1. 23-1'. TiN층 13-2. 13-2'. 23-2. 23-2'. W층13-1. 13-1 '. 23-1. 23-1 '. TiN layer 13-2. 13-2 '. 23-2. 23-2 '. W floor
14. 24. 포토레지스트 마스크 15. 15'. 25. 25'. 폴리머14. 24. Photoresist Mask 15. 15 '. 25. 25 '. Polymer
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950058235A KR100368985B1 (en) | 1995-12-27 | 1995-12-27 | Method for patterning metal film in fabrication process of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950058235A KR100368985B1 (en) | 1995-12-27 | 1995-12-27 | Method for patterning metal film in fabrication process of semiconductor device |
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| Publication Number | Publication Date |
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| KR970054601A KR970054601A (en) | 1997-07-31 |
| KR100368985B1 true KR100368985B1 (en) | 2003-03-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950058235A KR100368985B1 (en) | 1995-12-27 | 1995-12-27 | Method for patterning metal film in fabrication process of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9761513B2 (en) | 2012-04-20 | 2017-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating three dimensional integrated circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07122541A (en) * | 1993-10-25 | 1995-05-12 | Sony Corp | Machining method for aluminium based wiring |
-
1995
- 1995-12-27 KR KR1019950058235A patent/KR100368985B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07122541A (en) * | 1993-10-25 | 1995-05-12 | Sony Corp | Machining method for aluminium based wiring |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9761513B2 (en) | 2012-04-20 | 2017-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating three dimensional integrated circuit |
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| KR970054601A (en) | 1997-07-31 |
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