CN101740374A - Method for etching more than 10mu m of dielectric layer - Google Patents
Method for etching more than 10mu m of dielectric layer Download PDFInfo
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- CN101740374A CN101740374A CN200810043915A CN200810043915A CN101740374A CN 101740374 A CN101740374 A CN 101740374A CN 200810043915 A CN200810043915 A CN 200810043915A CN 200810043915 A CN200810043915 A CN 200810043915A CN 101740374 A CN101740374 A CN 101740374A
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Abstract
The invention discloses a method for etching a more than 10mu m of dielectric layer. The method comprises the following steps: 1. coating optical resist on the dielectric layer, exposing under light for development, then removing the optical resist above the etching window of the dielectric layer, maintaining residual optical resist; 2. etching the dielectric layer by using the anisotropic etching technology to remove 1/5-1/3 of the thickness of the dielectric layer on the etching window; 3. etching the dielectric layer by using the isotropic etching technology to further remove 1/3-3/5 of the thickness of the dielectric layer on the etching window; 4. removing optical resist and polymer; 5. repeating the step 1; 6. etching the dielectric layer by using the anisotropic etching technology to remove 1/5-1/3 of the thickness of the dielectric layer on the etching window until exposing the next layer of dielectric layer; and 7. removing optical resist and polymer. The method of the invention can be used to remove more than 10mu m of dielectric layer.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to a kind of lithographic method.
Background technology
The passivation layer of surface of silicon has silica (SiO
2), silicon nitride (Si
3N
4) and oxidized silicon nitride (SiO
xN
y) etc., traditional passivation layer thickness is generally less than 2 μ m, and the etching passivation layer only needs a photoetching can finish once the step etching.Its lithographic method is: resist coating on passivation layer at first, remove the photoresist of the etching window top of passivation layer behind the exposure imaging, and keep the photoresist of remainder; With anisotropic etch process etching passivation layer, etch away passivation layer until exposing substrate then in etching window.
Be applied to thicker passivation layer at some special dimension, its thickness may be 10～30 μ m.For the passivation layer of thickness more than 10 μ m, traditional lithographic method will run into challenge.This be since photoresist thickness usually on the order of magnitude of 1 μ m, 5 μ m only at the most, generally adopt dry plasma technology at present, continuously long-time plasma etching causes the photoresist of passivation layer top to burn easily, and the overheap such as (as the polymer of etching pattern side wall and/or bottom) that causes etch by-products easily and etching is stopped.
Above only for example with the passivation layer on the metal level.Similarly, all there is same problem in the etching of the dielectric layer of thickness more than 10 μ m.
Summary of the invention
Technical problem to be solved by this invention provides the method for the above dielectric layer of a kind of etching 10 μ m.
For solving the problems of the technologies described above, the method for the above dielectric layer of etching 10 μ m of the present invention comprises the steps:
In the 1st step, resist coating on dielectric layer is removed the photoresist of the etching window top of dielectric layer behind the exposure imaging, keep the photoresist of remainder;
In the 2nd step,, etch away the dielectric layer of 1/5～1/3 thickness in etching window with anisotropic etch process etching dielectric layer;
In the 3rd step,, further etch away the dielectric layer of 1/3～3/5 thickness in etching window with isotropic etching technology etching dielectric layer;
In the 4th step, remove photoresist and polymer;
In the 5th step, resist coating on dielectric layer is removed the photoresist of the etching window top of dielectric layer behind the exposure imaging, keep the photoresist of remainder;
In the 6th step,, further etch away the dielectric layer of 1/5～1/3 thickness again in etching window, until the following one deck that exposes dielectric layer with anisotropic etch process etching dielectric layer;
In the 7th step, remove photoresist and polymer.
The method of the above dielectric layer of etching 10 μ m of the present invention can be carried out etching to the dielectric layer of thickness more than 10 μ m under the prerequisite of the photoresist thickness (generally being not more than 5 μ m) that existing photoetching process can be accomplished.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1～Fig. 7 is respectively the schematic diagram in～the 7 step of the 1st step of the method for the invention.
Reference numeral is among the figure: the 1-photoresist; The 2-insulating medium layer; The 21-etching window; The sidewall of 22-etching section; The 221-side wall upper part; The 222-lower sidewall; The bottom of 23-etching section; α-the sidewall of etching section and the angle of bottom; 3-metal level or silicon substrate; Δ T-dielectric layer gross thickness; Δ T
1The thickness that etch away-first time; Δ T
2The thickness that etch away-second time; Δ T
3-the thickness that etches away for the third time.
Embodiment
The method of the above dielectric layer of etching 10 μ m of the present invention, dielectric layer 2 is positioned on metal level or the silicon substrate 3, and described method comprises the steps:
The 1st step saw also Fig. 1, and resist coating 1 on dielectric layer 2, removed the photoresist of etching window 21 tops of dielectric layer 2 behind the exposure imaging, kept the photoresist 1 of remainder.Briefly, this step is transferred to mask plate patterns on the photoresist, exposes the etching window 21 of dielectric layer 2 behind the exposure imaging, the dielectric layer 2 of the remainder of photoresist 1 protection except that etching window 21.
The 2nd step saw also Fig. 2, with anisotropic etch process etching dielectric layer 2, and the thickness deltat T of the dielectric layer 2 that etches away in etching window 21
1Be equivalent to dielectric layer 2 gross thickness Δ T 1/5～1/3.
Owing to adopted anisotropic etch process, the sidewall 22 of the etching section of etching figure to become 90～105 degree with the angle α of bottom 23, be preferably 95～100 degree.
The 3rd step saw also Fig. 3, with isotropic etching technology etching dielectric layer 2, and the thickness deltat T of the dielectric layer 2 that further etches away in etching window 21
2Be equivalent to dielectric layer 2 gross thickness Δ T 1/3～3/5.
Owing to adopted isotropic etching technology, photoresist 1 below of etching window 21 neighboring areas produces undercutting, so the etching section of etching figure has circular-arc sidewall 22.
The 4th step saw also Fig. 4, removed photoresist 1 and polymer.Remove photoresist and can adopt wet method to peel off, also can adopt dry plasma to remove photoresist.When removing photoresist, removal may appear at the sidewall of etching figure and/or polymer and other etch residues that may occur of bottom.
The 5th step saw also Fig. 5, and is identical with the 1st step, and resist coating 1 on dielectric layer 2, removes the photoresist of etching window 21 tops of dielectric layer 2 behind the exposure imaging, keeps the photoresist 1 of remainder.This step can adopt and identical mask of the 1st step, but owing to be to carry out photoetching on the silicon chip of figure having, therefore need adjust at aspects such as exposure energy, development conditions.
The 6th step saw also Fig. 6, with anisotropic etch process etching dielectric layer 2, further etched away the thickness deltat T of dielectric layer 2 again in etching window 21
3Be equivalent to dielectric layer 2 gross thickness Δ T 1/5～1/3, until metal level that exposes dielectric layer 2 belows or silicon substrate 3.
The 7th step saw also Fig. 7, and is identical with the 4th step.
After the three step etchings in the 2nd step, the 3rd step and the 6th step, the sidewall 22 of the etching section of etching figure is divided into top 221 and bottom 222, side wall upper part 221 is circular-arc, and lower sidewall 222 becomes 90～105 degree with the angle α of the bottom 23 of etching section, is preferably 95～100 degree.
In the said method, dielectric layer is the insulating medium layer for metal level, silicon substrate, and the lower floor of dielectric layer can be metal level or silicon substrate.
In the said method, anisotropic etch process can adopt dry plasma etc., and isotropic etching technology can adopt wet chemical etching technique or dry plasma that some is special etc.
The method of etching dielectric layer of the present invention realizes the etching of the dielectric layer of 10～30 μ m thickness is particularly suitable for the etching to the dielectric layer of 10～20 μ m (as 15 μ m) thickness by a mask, secondary photoetching, three step etchings.The photoresist that this method can avoid long-time plasma bombardment to cause on the one hand burns, and can reduce the accumulation of polymer in the etching process on the other hand, reduces follow-up polymer and removes difficulty.
Claims (9)
1. the method for the above dielectric layer of etching 10 μ m, it is characterized in that: described method comprises the steps:
In the 1st step, resist coating on dielectric layer is removed the photoresist of the etching window top of dielectric layer behind the exposure imaging, keep the photoresist of remainder;
In the 2nd step,, etch away the dielectric layer of 1/5～1/3 thickness in etching window with anisotropic etch process etching dielectric layer;
In the 3rd step,, further etch away the dielectric layer of 1/3～3/5 thickness in etching window with isotropic etching technology etching dielectric layer;
In the 4th step, remove photoresist and polymer;
In the 5th step, resist coating on dielectric layer is removed the photoresist of the etching window top of dielectric layer behind the exposure imaging, keep the photoresist of remainder;
In the 6th step,, further etch away the dielectric layer of 1/5～1/3 thickness again in etching window, until the following one deck that exposes dielectric layer with anisotropic etch process etching dielectric layer;
In the 7th step, remove photoresist and polymer.
2. the method for the above dielectric layer of etching 10 μ m according to claim 1 is characterized in that: in the 1st step and the 5th step of described method, adopt same mask.
3. the method for the above dielectric layer of etching 10 μ m according to claim 1 is characterized in that: in the 2nd step of described method, etch away the dielectric layer of 1/3 thickness in etching window;
In the 3rd step of described method, further etch away the dielectric layer of 1/3 thickness in etching window;
In the 6th step of described method, further etch away the dielectric layer of 1/3 thickness again in etching window.
4. the method for the above dielectric layer of etching 10 μ m according to claim 1 is characterized in that: in the 2nd step of described method, the sidewall of the etching section of etching figure becomes 90～105 degree angles with the bottom.
5. the method for the above dielectric layer of etching 10 μ m according to claim 1 is characterized in that: in the 3rd step of described method, the etching section of etching figure has circular-arc sidewall.
6. the method for the above dielectric layer of etching 10 μ m according to claim 1 is characterized in that: in the 6th step of described method, the side wall upper part of the etching section of etching figure is circular-arc, and lower sidewall becomes 90～105 degree angles with the bottom.
7. the method for the above dielectric layer of etching 10 μ m according to claim 1 is characterized in that: described anisotropic etch process adopts dry plasma.
8. the method for the above dielectric layer of etching 10 μ m according to claim 1 is characterized in that: described isotropic etching process using wet chemical etching technique or dry plasma.
9. the method for the above dielectric layer of etching 10 μ m according to claim 1, it is characterized in that: described dielectric layer is silica, silicon nitride or oxidized silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810043915A CN101740374A (en) | 2008-11-11 | 2008-11-11 | Method for etching more than 10mu m of dielectric layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810043915A CN101740374A (en) | 2008-11-11 | 2008-11-11 | Method for etching more than 10mu m of dielectric layer |
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| Publication Number | Publication Date |
|---|---|
| CN101740374A true CN101740374A (en) | 2010-06-16 |
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ID=42463643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810043915A Pending CN101740374A (en) | 2008-11-11 | 2008-11-11 | Method for etching more than 10mu m of dielectric layer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107123596A (en) * | 2017-05-19 | 2017-09-01 | 武汉新芯集成电路制造有限公司 | A kind of dry etching method |
| CN115050645A (en) * | 2022-08-11 | 2022-09-13 | 广州粤芯半导体技术有限公司 | Method for improving adhesive film residue on surface of wafer |
-
2008
- 2008-11-11 CN CN200810043915A patent/CN101740374A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107123596A (en) * | 2017-05-19 | 2017-09-01 | 武汉新芯集成电路制造有限公司 | A kind of dry etching method |
| CN115050645A (en) * | 2022-08-11 | 2022-09-13 | 广州粤芯半导体技术有限公司 | Method for improving adhesive film residue on surface of wafer |
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Application publication date: 20100616 |