CN107123596A - A kind of dry etching method - Google Patents
A kind of dry etching method Download PDFInfo
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- CN107123596A CN107123596A CN201710358532.6A CN201710358532A CN107123596A CN 107123596 A CN107123596 A CN 107123596A CN 201710358532 A CN201710358532 A CN 201710358532A CN 107123596 A CN107123596 A CN 107123596A
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- dry etching
- etching
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- dry
- flow
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- 238000001312 dry etching Methods 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 49
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052802 copper Inorganic materials 0.000 claims abstract description 35
- 239000010949 copper Substances 0.000 claims abstract description 35
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 18
- 239000001301 oxygen Substances 0.000 claims abstract description 18
- 229920002313 fluoropolymer Polymers 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract description 10
- 238000001035 drying Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- 238000004140 cleaning Methods 0.000 claims description 15
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 230000003628 erosive effect Effects 0.000 claims 2
- 230000007547 defect Effects 0.000 abstract description 15
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 15
- 229920000642 polymer Polymers 0.000 description 5
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004811 fluoropolymer Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 101100298888 Arabidopsis thaliana PAD2 gene Proteins 0.000 description 1
- 101100030928 Arabidopsis thaliana PAF1 gene Proteins 0.000 description 1
- 101100465385 Arabidopsis thaliana PAF2 gene Proteins 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 101100288173 Enterococcus faecalis (strain ATCC 700802 / V583) prs1 gene Proteins 0.000 description 1
- 101100398338 Enterococcus faecalis (strain ATCC 700802 / V583) prs2 gene Proteins 0.000 description 1
- 101100510342 Listeria ivanovii prs gene Proteins 0.000 description 1
- 101000905241 Mus musculus Heart- and neural crest derivatives-expressed protein 1 Proteins 0.000 description 1
- 101100137870 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) PRE10 gene Proteins 0.000 description 1
- 101100465401 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SCL1 gene Proteins 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000012459 cleaning agent Substances 0.000 description 1
- 229940125904 compound 1 Drugs 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 101150077839 pac1 gene Proteins 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 101150086435 prs1 gene Proteins 0.000 description 1
- 101150016674 prs2 gene Proteins 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention provides a kind of dry etching method, including：One dry-process etching cavity is provided；Semiconductor substrate is provided, semiconductor base includes the mask layer of device layer, copper interconnection layer, dielectric layer and patterning successively from the bottom to top；The step of main etching, dry etching is carried out with the mask layer of patterning, to remove part of dielectric layer；The step of over etching, continue the mask layer to pattern, coordinate fluorocarbon polymer and excessive oxygen to carry out dry etching, to expose copper interconnection layer；Remove mask layer.Beneficial effects of the present invention：Original replaced with by disposable dry etching exposure copper interconnection layer is exposed into copper interconnection layer by dry etching twice, more excessive oxygen in due to be with the addition of in over etching step relative to main etch step, and oxygen can suppress fluorocarbon polymer and be reacted with copper, so that avoiding fluorocarbon polymer and the copper of wafer from reacting causes pit defect.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of dry etching method.
Background technology
With gradually increasing super large-scale integration high integration and high performance demand, semiconductor technology is towards more
Small feature size technologies development, the complexity of technique is continuously increased, and higher requirement is proposed to etching technics.
The dry etching method of prior art comprises the following steps：
One dry-process etching cavity is provided；
Semiconductor substrate is provided, the semiconductor base includes device layer, copper interconnection layer, dielectric layer successively from the bottom to top
And the mask layer of patterning；
Main etching technique is carried out, i.e., above-mentioned dielectric layer is performed etching successively by conventional dry etching mode, is removed
Dielectric layer, the above-mentioned copper interconnection layer of exposure；
Remove unnecessary photoresist layer.
Above-mentioned dry etching method mainly includes main etching (Main Etch, ME) and photoresist removes (Strip) two steps
Suddenly, main etch step is used for by disposably etching the above-mentioned copper interconnection layer of exposure, and photoresist step is used to complete main etching
Photoresist layer is removed after step.Because when carrying out dry etching, multiple wafers (Wafer) are located at same dry-process etching cavity
In, completed dry etching wafer can not be unavoidably in main etch step produce some CF for containing*Macromolecule
Polymer, these CF contained*High molecular polymer not only can be with having completed dry etching wafer on copper occur it is anti-
It should generateOther in the surface of the wafer of unfinished dry etching, wafer box can be also attached to and do not complete dry method also
The wafer of etching complete main etch step after also can with containing CF*High molecular polymer react generationIf wafer after dry etching the copper on its surface with containing CF*High molecular polymer react life
IntoIn cleaning step (generally using ST250) then after dry etch step,Meeting and cleaning agent
In alkalescence (alkalescent) material for containing react generation CU 2+, so as to cause copper surface to produce pit defect.Once
Pit defect is generated in some processing operations after carrying out cleaning step, pit defect can constantly be amplified, and be ultimately resulted in tight
The defective workmanship of weight.
Fig. 1-3 completes a kind of processing operation after dry etch step and cleaning step, such as Fig. 1 for wafer in the prior art
Shown, above-mentioned pit defect is located on TM layers, TM layers is sequentially provided with silicon nitride (SiN) layer and oxide (Oxide) from the bottom to top
Layer, SiN layer and the Oxide layers of groove being formed with above pit defect, depositing TiN/AL/TiN layers and in TiN/AL/TiN
Layer continuously forms the groove above pit defect, and Oxide layers of deposition is simultaneously continuously formed on pit defect at Oxide layers
The groove of side, can be clearly seen in figure, when carrying out above-mentioned processing operation, and the pit defect in TM layers is increasing, from
And cause increasingly severe defective workmanship.
The electron microscope schematic diagram of wafer after processing operations of the Fig. 4-5 to complete Fig. 1-3 in the prior art, in figure
It can be seen that the pit defect in TM layers is increasing.
In summary, how to be reduced in dry etching containing CF*Influence of the high molecular polymer to wafer, it is to avoid
Produce the problem of pit defect is those skilled in the art's urgent need to resolve.
The content of the invention
For problems of the prior art, the invention provides a kind of dry etching for being avoided that generation pit defect
Method.
The present invention is adopted the following technical scheme that：
A kind of dry etching method, including：
One dry-process etching cavity is provided；
Semiconductor substrate is provided, the semiconductor base includes device layer, copper interconnection layer, dielectric layer successively from the bottom to top
And the mask layer of patterning；
The dry etching method also includes：
The step of main etching, dry etching is carried out with the mask layer of the patterning, to remove the part dielectric layer；
The step of over etching, continue with the mask layer of the patterning, coordinate fluorocarbon polymer and excessive oxygen to carry out
Dry etching, with the exposure copper interconnection layer；
Remove the mask layer.
It is preferred that, before the main etch step is carried out, the dry etching method also includes：
The step of pre-cleaning, the oxygen of predetermined is passed through into the dry-process etching cavity to remove and is attached to described half
Fluorocarbon polymer on the mask layer of conductor substrate.
It is preferred that, when carrying out the pre-cleaning, the pressure in the reaction chamber is 300mt.
It is preferred that, when carrying out the main etching, the pressure in the reaction chamber is 60mt.
It is preferred that, when carrying out the over etching, the pressure in the reaction chamber is 60mt.
It is preferred that, when carrying out the pre-cleaning, the flow of the oxygen is 1500sccm.
It is preferred that, the main etching is carried out using the first etching gas, first etching gas include carbon tetrafluoride, three
Fluoromethane and nitrogen；
The flow of the carbon tetrafluoride is 150sccm, and the flow of the fluoroform is 50sccm, the flow of the nitrogen
For 170sccm.
It is preferred that, carry out the over etching using the second etching gas, second etching gas include carbon tetrafluoride,
Argon, oxygen and nitrogen；
The flow of the carbon tetrafluoride is 80sccm, and the flow of the argon is 500sccm, and the flow of the oxygen is
20sccm, the flow of the nitrogen is 170sccm.
Beneficial effects of the present invention：Replaced with original by disposable dry etching exposure copper interconnection layer by twice
Dry etching exposes copper interconnection layer, i.e., dielectric layer of the part above copper interconnection layer is first removed by main etch step,
When will remove dielectric layer and exposure copper interconnection layer completely, by over etching step, remove remaining dielectric layer to be completely exposed
The copper interconnection layer, due to be with the addition of in over etching step relative to main etch step in more excessive oxygen, and oxygen
Gas can suppress fluorocarbon polymer and be reacted with copper, so that avoiding fluorocarbon polymer and the copper of wafer from reacting causes pit
Defect.
Brief description of the drawings
Fig. 1-3 completes a kind of processing operation signal after dry etch step and cleaning step for wafer in the prior art
Figure；
The electron microscope schematic diagram of wafer after processing operations of the Fig. 4-5 to complete Fig. 1-3 in the prior art；
Fig. 6 be a preferred embodiment of the present invention in, one of principle schematic；
Fig. 7 be a preferred embodiment of the present invention in, the two of principle schematic；
Fig. 8 be a preferred embodiment of the present invention in, the flow chart of dry etching method；
Fig. 9-12 be a preferred embodiment of the present invention in, the process schematic of dry etching method.
Embodiment
It should be noted that in the case where not conflicting, following technical proposals can be mutually combined between technical characteristic.
The embodiment to the present invention is further described below in conjunction with the accompanying drawings：
As illustrated in figs. 8-12, a kind of dry etching method, including：
One dry-process etching cavity is provided；
Semiconductor substrate 3 is provided, the semiconductor base 3 includes device layer, copper interconnection layer 2, is situated between successively from the bottom to top
The mask layer 5 of electric layer 4 and patterning；
The dry etching method also includes：
The step of main etching, dry etching is carried out with the mask layer 5 of the patterning, to remove the part dielectric layer 4；
The step of over etching, continue with the mask layer 5 of the patterning, coordinate fluorocarbon polymer 1 and excessive oxygen to enter
Row dry etching, with the exposure copper interconnection layer 2；
Remove the mask layer 5.
In the present embodiment, replaced with original by disposable dry etching exposure copper interconnection layer 2 by doing twice
Method etching exposure copper interconnection layer 2, i.e., first remove dielectric layer 4 of the part positioned at the top of copper interconnection layer 2 by main etch step,
When will remove dielectric layer 4 and exposure copper interconnection layer 2 completely, by over etching step, remaining dielectric layer 4 is removed with completely sudden and violent
Reveal the copper interconnection layer 2, due to be with the addition of in over etching step relative to main etch step in more excessive oxygen, root
According to understanding as shown in fig. 6-7, work as CF*Content be more than O*Content, the polymerization of carbon fluorine can be deposited after dry etching on copper interconnection layer 2
Thing 1, while a part of CF*Volatilization；Work as CF*Content be less than O*Content, carbon will not be deposited on copper interconnection layer 2 after dry etching
C atoms in fluoropolymer 1, fluorocarbon polymer 1 can be combined to form with O atom to volatilize after CO conjugates, and oxygen can suppress carbon
Fluoropolymer 1 is reacted with copper, so that avoiding fluorocarbon polymer 1 and the copper of wafer from reacting causes pit defect.
In preferred embodiments of the present invention, before the main etch step is carried out, the dry etching method also includes：
The step of pre-cleaning, the oxygen of predetermined is passed through into the dry-process etching cavity to remove and is attached to described half
Fluorocarbon polymer 1 on the mask layer 5 of conductor substrate 3.
In the present embodiment, pre-cleaning step is added before main etch step, the carbon fluorine being attached on mask layer 5 is removed and gathers
Compound 1, it is to avoid the fluorocarbon polymer 1 being attached on mask layer 5 and the copper interconnection layer 2 subsequently exposed react and cause pit
Defect.
In preferred embodiments of the present invention, when carrying out above-mentioned pre-cleaning step, the pressure in above-mentioned reaction chamber is
300mt。
In preferred embodiments of the present invention, when carrying out above-mentioned over etching step, the pressure in above-mentioned reaction chamber is 60mt.
In preferred embodiments of the present invention, when carrying out above-mentioned pre-cleaning step, above-mentioned O2Flow be 1500sccm.
In preferred embodiments of the present invention, carry out above-mentioned main etching when, above-mentioned first etching gas include CF4, CHF3 with
And N2；
Above-mentioned CF4 flow is 150sccm, and above-mentioned CHF3 flow is 50sccm, and above-mentioned N2 flow is 170sccm.
In preferred embodiments of the present invention, when carrying out above-mentioned over etching, above-mentioned second etching gas include CF4, Ar, O2With
And N2；
Above-mentioned CF4 flow is 80sccm, and above-mentioned Ar flow is 500sccm, above-mentioned O2Flow be 20sccm, it is above-mentioned
N2 flow is 170sccm.
In the application, pre-cleaning step (Trim), main cleanup step (ME) are carried out, cleanup step (OE) is crossed and removes and cover
Reaction condition during film layer 5 (PRS1 and PRS2) step is such as
Shown in following table：
By explanation and accompanying drawing, the exemplary embodiments of the specific structure of embodiment are given, based on essence of the invention
God, can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, read after described above, various changes and modifications undoubtedly will be evident.
Therefore, appended claims should regard whole variations and modifications of the true intention and scope that cover the present invention as.In power
Any and all scope and content of equal value, are all considered as still belonging to the intent and scope of the invention in the range of sharp claim.
Claims (8)
1. a kind of dry etching method, including：
One dry-process etching cavity is provided；
Semiconductor substrate is provided, semiconductor base includes device layer, copper interconnection layer, dielectric layer and pattern successively from the bottom to top
The mask layer of change；
Characterized in that, dry etching method also includes：
The step of main etching, dry etching is carried out with the mask layer of patterning, to remove part of dielectric layer；
The step of over etching, continue the mask layer to pattern, coordinate fluorocarbon polymer and excessive oxygen to carry out dry etching,
To expose copper interconnection layer；
Remove mask layer.
2. dry etching method according to claim 1, it is characterised in that before main etch step is carried out, dry etching side
Method also includes：
The step of pre-cleaning, the oxygen of predetermined is passed through into dry-process etching cavity and is attached to covering for semiconductor base to remove
Fluorocarbon polymer in film layer.
3. dry etching method according to claim 2, it is characterised in that when carrying out the pre-cleaning, the reaction chamber
Indoor pressure is 300mt.
4. dry etching method according to claim 1, it is characterised in that when carrying out the main etching, the reaction chamber
Indoor pressure is 60mt.
5. dry etching method according to claim 1, it is characterised in that when carrying out the over etching, the reaction chamber
Indoor pressure is 60mt.
6. dry etching method according to claim 2, it is characterised in that when carrying out the pre-cleaning, the oxygen
Flow is 1500sccm.
7. dry etching method according to claim 1, it is characterised in that carry out the main quarter using the first etching gas
Erosion, first etching gas include carbon tetrafluoride, fluoroform and nitrogen；
The flow of the carbon tetrafluoride is 150sccm, and the flow of the fluoroform is 50sccm, and the flow of the nitrogen is
170sccm。
8. dry etching method according to claim 1, it is characterised in that carry out described cross using the second etching gas and carve
Erosion, second etching gas include carbon tetrafluoride, argon, oxygen and nitrogen；
The flow of the carbon tetrafluoride is 80sccm, and the flow of the argon is 500sccm, and the flow of the oxygen is 20sccm,
The flow of the nitrogen is 170sccm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710358532.6A CN107123596A (en) | 2017-05-19 | 2017-05-19 | A kind of dry etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710358532.6A CN107123596A (en) | 2017-05-19 | 2017-05-19 | A kind of dry etching method |
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| CN107123596A true CN107123596A (en) | 2017-09-01 |
Family
ID=59727490
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5110712A (en) * | 1987-06-12 | 1992-05-05 | Hewlett-Packard Company | Incorporation of dielectric layers in a semiconductor |
| JPH06267907A (en) * | 1993-03-10 | 1994-09-22 | Sony Corp | Dry etching |
| CN101459125A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Connection pore forming method |
| CN101728317A (en) * | 2008-10-21 | 2010-06-09 | 中芯国际集成电路制造(北京)有限公司 | Forming methods of conducting structure and pad |
| CN101740374A (en) * | 2008-11-11 | 2010-06-16 | 上海华虹Nec电子有限公司 | Method for etching more than 10mu m of dielectric layer |
| CN103730409A (en) * | 2012-10-16 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method, cleaning method and cleaning system of semiconductor device |
-
2017
- 2017-05-19 CN CN201710358532.6A patent/CN107123596A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5110712A (en) * | 1987-06-12 | 1992-05-05 | Hewlett-Packard Company | Incorporation of dielectric layers in a semiconductor |
| JPH06267907A (en) * | 1993-03-10 | 1994-09-22 | Sony Corp | Dry etching |
| CN101459125A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Connection pore forming method |
| CN101728317A (en) * | 2008-10-21 | 2010-06-09 | 中芯国际集成电路制造(北京)有限公司 | Forming methods of conducting structure and pad |
| CN101740374A (en) * | 2008-11-11 | 2010-06-16 | 上海华虹Nec电子有限公司 | Method for etching more than 10mu m of dielectric layer |
| CN103730409A (en) * | 2012-10-16 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method, cleaning method and cleaning system of semiconductor device |
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