KR100284142B1 - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR100284142B1 KR100284142B1 KR1019940014820A KR19940014820A KR100284142B1 KR 100284142 B1 KR100284142 B1 KR 100284142B1 KR 1019940014820 A KR1019940014820 A KR 1019940014820A KR 19940014820 A KR19940014820 A KR 19940014820A KR 100284142 B1 KR100284142 B1 KR 100284142B1
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Abstract
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 안정된 형상(profile)을 갖는 금속배선을 형성하기 위하여, 패턴화된 감광막을 이용한 금속층 식각시 주식각공정(main etch step)에서 Cl2와 BCl3개스 비율을 1:1로 하고, 과도식각공정(over etch step)에서 RF 레벨을 주식각공정보다 200~300W 상향조정하여, 금속배선에서 발생되는 브릿지(bridge)현상 및 넥킹(necking)을 방지하므로써 안정된 형상을 갖는 금속배선을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device. In order to form metal wirings having a stable profile, Cl 2 and BCl in a main etch step in etching a metal layer using a patterned photosensitive film are provided. The ratio of 3 gas is 1: 1, and the RF level is raised 200 ~ 300W from the stock etching process in the over etch step to prevent bridge phenomenon and necking occurring in the metal wiring. Therefore, the present invention relates to a method of forming a metal wiring having a stable shape.
Description
제1(a)도 내지 제1(d)도는 종래 반도체 소자의 금속배선 형성방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (d) are cross-sectional views of a device for explaining a metal wiring forming method of a conventional semiconductor device.
제2(a)도 내지 제2(d)도는 본 발명에 의한 반도체 소자의 금속배선 형성방법을 설명하기 위한 소자의 단면도.2 (a) to 2 (d) are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2, 12 : 금속층1 substrate 2, 12 metal layer
2A, 12A : 금속배선 3, 13 : 감광막2A, 12A: metal wiring 3, 13: photosensitive film
B : 브릿지(Bridge) N : 넥킹(necking)B: Bridge N: Necking
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 특히 안정된 형상(profile)을 갖는 금속배선을 형성하기 위하여, 패턴화된 감광막을 이용한 금속층 식각시 주식각공정(main etch step)에서 Cl2와 BCl3개스 비율을 1:1로 하고, 과도식각공정(over etch step)에서 RF 레벨을 주식각공정보다 200~300W 상향조정하여, 금속배선에서 발생되는 브릿지(bridge)현상 및 넥킹(necking)을 방지하므로써 안정된 형상을 갖는 금속배선을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device. In particular, in order to form metal wirings having a stable profile, Cl 2 and Cl 2 in a main etch step during metal layer etching using a patterned photosensitive film are formed. The ratio of BCl 3 gas is 1: 1 and the RF level is raised 200 ~ 300W from the stock etch process in the over etch step to reduce the bridge phenomenon and necking generated in the metal wiring. It relates to a method for forming a metal wiring having a stable shape by preventing.
반도체 제조공정중 금속배선을 형성할 때 금속층 식각공정을 실시하게 되는데, 금속층은 금속의 반사성(reflectance)때문에 생기는 포토 노치(photo notch)와 과도식각(over etch)때문에 발생하는 식각 노치(일명 탑 넥킹)현상이 있다. 포토 노치는 금속층상에 난반사막(ARC film)을 추가 삽입하므로써 해결할 수 있으나, 식각 노치는 금속층과 감광막간의 식각 선택비가 낮기 때문에 해결하기 어려운 문제가 있다.During the semiconductor manufacturing process, metal layer etching process is performed when metal wiring is formed. The metal layer is etch notch (aka top necking) caused by photo notch and over etch caused by metal reflectivity. There is a phenomenon. The photo notch can be solved by additionally inserting an ARC film on the metal layer, but the etching notch has a problem that is difficult to solve because the etching selectivity between the metal layer and the photoresist layer is low.
제1(a)도 내지 제1(d)도는 종래 반도체 소자의 금속배선 형성방법을 설명하기 위한 소자의 단면도로서, 제1(a)도는 소정의 반도체 소자 제조공정을 거친 후 최상부에 절연층이 형성된 기판(1)상에 금속층(2)을 형성하고, 상기 금속층(2) 상부에 감광막(3)을 도포한 후 금속배선 마스크를 사용하여 상기 감광막(3)을 패턴화한 상태를 도시한 것이다.1 (a) to 1 (d) are cross-sectional views of a device for explaining a metal wiring formation method of a conventional semiconductor device. FIG. 1 (a) is a top view of an insulating layer after a predetermined semiconductor device manufacturing process. The metal layer 2 is formed on the formed substrate 1, the photoresist film 3 is applied on the metal layer 2, and the photoresist film 3 is patterned using a metal wiring mask. .
제1(b)도는 Cl2와 BCl3개스를 1:2 비율로 하여 주식각공정을 실시하는 상태를 도시한 것으로, 이때 패턴화된 감광막(3)과 하부의 금속층(2)간에 식각 선택비가 낮아 패턴화된 감광막(3)의 손실이 많다.FIG. 1 (b) shows a state in which the stock angle process is performed by using a ratio of Cl 2 and BCl 3 in a 1: 2 ratio, wherein an etching selectivity between the patterned photosensitive film 3 and the lower metal layer 2 is increased. The loss of the patterned photosensitive film 3 is low.
제1(c)도는 과도식각공정을 실시한 상태를 도시한 것으로, 이때 과도식각공정전부터 남아있는 감광막(3)이 적기때문에 충분한 과도식각공정을 실시하지 못할 경우 이웃하는 금속배선간에 브릿지(B)가 발생하게 되고, 이러한 브릿지(B)현상을 제거시키기 위해 과도식각공정을 충분히 실시할 경우 금속배선에 티닝(Thinning)현상 및 넥킹(N)이 발생됨을 보여준다.FIG. 1 (c) shows a state in which the transient etching process is performed. In this case, since there is less photoresist film 3 remaining before the transient etching process, the bridge (B) is formed between neighboring metal wirings if sufficient transient etching process is not performed. When the excessive etching process is sufficiently performed to remove the bridge (B) phenomenon, it shows that the tinning phenomenon and necking (N) are generated in the metal wiring.
제1(d)도는 상기 감광막(3)을 제거하여 금속배선(2A)을 형성한 상태를 도시한 것으로, 금속배선(2A)간의 브릿지(B)현상 및 금속배선(2A)의 넥킹(N)으로 인하여 소자의 수율 및 품질을 저하시킨다.FIG. 1 (d) shows a state in which the photosensitive film 3 is removed to form the metal wiring 2A. The bridge B phenomenon between the metal wiring 2A and the necking N of the metal wiring 2A are shown. This lowers the yield and quality of the device.
따라서, 본 발명은 금속배선간의 브릿지 현상 및 금속배선의 넥킹발생을 방지하면서 안정된 형상을 갖는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming metal wiring of a semiconductor device having a stable shape while preventing the phenomenon of bridge between metal wiring and necking of the metal wiring.
이러한 목적을 달성하기 위한 본 발명의 금속배선 형성방법은 소정의 기판(11)상에 금속층(12)을 형성하고, 그 상부에 패턴화된 감광막(13)을 형성하는 단계와, 상기 단계로부터 Cl2와 BCl3개스를 1:1 비율로하여 상기 패턴화된 감광막(13)을 식각 마스크로 한 주식각 공정을 실시하는 단계와, 상기 단계로부터 RF 레벨을 상향조정하여 과도식각공정을 실시하는 단계와, 상기 단계로부터 패턴화된 감광막(13)을 제거하여 안정된 형상을 갖는 금속배선(12A)을 형성하는 단계로 이루어지는 것을 특징으로 한다.The metallization method of the present invention for achieving the above object is to form a metal layer 12 on a predetermined substrate 11, to form a patterned photosensitive film 13 thereon, Cl from the above step Performing a stock angle process using the patterned photoresist film 13 as an etch mask using 2 and BCl 3 gas in a 1: 1 ratio, and performing an overetch process by adjusting an RF level upward from the step. And removing the patterned photosensitive film 13 from the above step to form a metal wiring 12A having a stable shape.
제2(a)도 내지 제2(d)도는 본 발명에 의한 반도체 소자의 금속배선 형성방법을 설명하기 위한 소자의 단면도로서, 제2(a)도는 소정의 반도체 소자 제조공정을 거친 후 최상부에 절연층이 형성된 기판(11)상에 금속층(12)을 형성하고, 상기 금속층(12)상부에 감광막(13)을 도포한 후 금속배선 마스크를 사용하여 상기 감광막(13)을 패턴화한 상태를 도시한 것이다.2 (a) to 2 (d) are cross-sectional views of a device for explaining a method of forming metal wirings of a semiconductor device according to the present invention. FIG. The metal layer 12 is formed on the substrate 11 on which the insulating layer is formed, the photoresist film 13 is applied on the metal layer 12, and then the photoresist film 13 is patterned using a metal wiring mask. It is shown.
제2(b)도는 Cl2와 BCl3개스를 1:1 비율로하여 주식각공정을 실시하는 상태를 도시한 것으로, 상기 Cl2:BCl3= 1:1의 비율로 함에 의해 감광막(13)과 금속층(12)간의 식각 선택비가 높아져 감광막(13)의 손실이 적다. 즉, 제1(b)도와 비교해 볼때 제1(b)도의 감광막(3)보다 제2(b)도의 감광막(13)이 훨씬 적게 손실된다.FIG. 2 (b) shows a state in which the stock angle process is performed using Cl 2 and BCl 3 gas in a 1: 1 ratio, and the photosensitive film 13 is formed by setting Cl 2 : BCl 3 = 1: 1. And the etching selectivity between the metal layer 12 and the loss of the photosensitive film 13 is small. That is, the photosensitive film 13 of FIG. 2 (b) is lost much less than the photosensitive film 3 of FIG. 1 (b) as compared with FIG.
제2(c)도는 RF 레벨을 주식각공정보다 200~300W 상향한 상태로 과도식각공정을 실시한 상태를 도시한 것으로, 이때 과도식각공정전부터 남아있는 감광막(13)이 많기 때문에 충분히 과도식각공정을 실시하더라도 제1(c)도와 같은 브릿지(B)현상 및 넥킹(N)이 발생되지 않고, 더우기 RF 레벨을 상향조정시킴에 의해 측면 식각보다 수직 식각이 증가되어 식각된 형상이 수직으로 된다.FIG. 2 (c) shows a state in which the transient etching process is performed with the RF level 200-300W higher than the stock etching process. At this time, since the photoresist film 13 is left before the transient etching process, the transient etching process is sufficiently performed Even if it is implemented, the bridge (B) phenomenon and the necking (N) as shown in the first (c) does not occur, and by adjusting the RF level upward, the vertical etching is increased rather than the side etching, the etched shape becomes vertical.
제2(d)도는 상기 감광막(13)을 제거하여 안정된 형상을 갖는 금속배선(12A)을 형성한 상태를 도시한 것이다.FIG. 2 (d) shows a state in which the photosensitive film 13 is removed to form a metal wiring 12A having a stable shape.
상술한 바와같이 본 발명은 감광막과 금속층간의 식각선택비가 높아 충분한 과도식각공정을 실시할 수 있어 브릿지 현상 및 넥킹 발생을 방지하고, 과도식각공정시 RF 레벨을 높여주므로써 식각형상이 수직되게 하므로써 소자의 수율 및 품질을 향상시킬 수 있다.As described above, according to the present invention, the etching selectivity between the photoresist film and the metal layer is high, so that the sufficient etching process can be performed, thereby preventing bridge phenomenon and necking, and increasing the RF level during the etching process. The yield and quality of the device can be improved.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019940014820A KR100284142B1 (en) | 1994-06-27 | 1994-06-27 | Metal wiring formation method of semiconductor device |
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| KR1019940014820A KR100284142B1 (en) | 1994-06-27 | 1994-06-27 | Metal wiring formation method of semiconductor device |
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| KR960002575A KR960002575A (en) | 1996-01-26 |
| KR100284142B1 true KR100284142B1 (en) | 2001-04-02 |
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| KR100450567B1 (en) * | 2001-12-26 | 2004-09-30 | 동부전자 주식회사 | Method for manufacturing line |
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| KR100450567B1 (en) * | 2001-12-26 | 2004-09-30 | 동부전자 주식회사 | Method for manufacturing line |
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