KR960002575A - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

Info

Publication number
KR960002575A
KR960002575A KR1019940014820A KR19940014820A KR960002575A KR 960002575 A KR960002575 A KR 960002575A KR 1019940014820 A KR1019940014820 A KR 1019940014820A KR 19940014820 A KR19940014820 A KR 19940014820A KR 960002575 A KR960002575 A KR 960002575A
Authority
KR
South Korea
Prior art keywords
metal wiring
semiconductor device
forming
photosensitive film
formation method
Prior art date
Application number
KR1019940014820A
Other languages
Korean (ko)
Other versions
KR100284142B1 (en
Inventor
김인철
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940014820A priority Critical patent/KR100284142B1/en
Publication of KR960002575A publication Critical patent/KR960002575A/en
Application granted granted Critical
Publication of KR100284142B1 publication Critical patent/KR100284142B1/en

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 안정된 형상(profile)을 갖는 금속배선을 형성하기 위하여, 패턴화된 감광막을 이용한 금속층 식각시 주식각공정(main etch step)에서 Cℓ2와 BCℓ3개스 비율을 1:1로 하고, 과도식각공정(over etch step)에서 RF 레벨을 주식각공정보다 200~300W 상향 조정하여, 금속배선에서 발생되는 브릿지(bridge)현상 및 넥킹(necking)을 방지하므로써 안정된 형상을 갖는 금속배선을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device. In order to form metal wirings having a stable profile, Cl 2 and BCl in a main etch step in etching a metal layer using a patterned photosensitive film The ratio of 3 gas is 1: 1, and the RF level is increased 200 ~ 300W from the stock etching process in the over etch step to prevent bridge phenomenon and necking occurring in the metal wiring. Therefore, the present invention relates to a method of forming a metal wiring having a stable shape.

Description

반도체소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2D도는 본 발명에 의한 반도체 소자의 금속배선 형성방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.

Claims (2)

반도체 소자의 금속배선 형성방법에 있어서, 소정의 기판(11)상에 금속층(12)을 형성하고, 그 상부에 패턴화된 감광막(13)을 형성하는 단계와, 상기 단계로부터 Cℓ2와 BCℓ3개스를 1:1 비율로하여 상기 패턴화된 감광막(13)을 식각 마스크로 한 주식각공정을 실시하는 단계와, 상기 단계로부터 RF 레벨을 상향조정하여 과도식각공정을 실시하는 단계와, 상기 단계로부터 패턴화된 감광막(13)을 제거하여 안정된 형상을 갖는 금속배선(12A)을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.In the metal wiring formation method of a semiconductor device, forming a metal layer 12 on a predetermined substrate 11, and forming a patterned photosensitive film 13 thereon, and C1 2 and BC1 3 from the above step Performing a stock etching process using the patterned photosensitive film 13 as an etching mask at a gas ratio of 1: 1, and performing an overetching process by adjusting an RF level upward from the step; Forming a metal wiring (12A) having a stable shape by removing the patterned photosensitive film (13) from the metal wiring. 제1항에 있어서, 상기 과도식각공정시 RF 레벨은 주식각공정보다 200~300W 높여 실시하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the RF level is 200-300 W higher than the stock etching process during the transient etching process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940014820A 1994-06-27 1994-06-27 Metal wiring formation method of semiconductor device KR100284142B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940014820A KR100284142B1 (en) 1994-06-27 1994-06-27 Metal wiring formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940014820A KR100284142B1 (en) 1994-06-27 1994-06-27 Metal wiring formation method of semiconductor device

Publications (2)

Publication Number Publication Date
KR960002575A true KR960002575A (en) 1996-01-26
KR100284142B1 KR100284142B1 (en) 2001-04-02

Family

ID=66686448

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940014820A KR100284142B1 (en) 1994-06-27 1994-06-27 Metal wiring formation method of semiconductor device

Country Status (1)

Country Link
KR (1) KR100284142B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101011531B1 (en) * 2008-11-24 2011-01-27 이수정 A structural to sepatating the storeroom of a refrigerator

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100450567B1 (en) * 2001-12-26 2004-09-30 동부전자 주식회사 Method for manufacturing line

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101011531B1 (en) * 2008-11-24 2011-01-27 이수정 A structural to sepatating the storeroom of a refrigerator

Also Published As

Publication number Publication date
KR100284142B1 (en) 2001-04-02

Similar Documents

Publication Publication Date Title
KR960002575A (en) Metal wiring formation method of semiconductor device
KR960035802A (en) Fine pattern formation method and metal wiring formation method using the same
KR960019522A (en) Plug Formation Method for Semiconductor Devices
KR100309133B1 (en) Method for manufacturing metal interconnection of semiconductor device
KR980005480A (en) Metal wiring formation method of semiconductor device
KR970052570A (en) Planarization method of semiconductor device
KR970052761A (en) Pattern formation method of semiconductor device
KR960019488A (en) Wiring pattern formation method of semiconductor device
KR960005792A (en) Micro contact formation method
KR960011550A (en) Double etching cross section formation method
KR970018198A (en) Planarization method of semiconductor device
KR20010063661A (en) Method of forming a damascene pattern in a semiconductor device
KR20030096669A (en) method for manufacturing gate in semiconductor memory device
KR950014975A (en) Method for manufacturing metal wiring of semiconductor device
KR970052239A (en) Via contact formation method of semiconductor device
KR970052342A (en) Metal pattern formation method of semiconductor device
KR970052372A (en) Metal wiring formation method of semiconductor device
KR970023816A (en) Multi layer etching method
KR980005466A (en) Metal wiring formation method of semiconductor device
KR970023828A (en) Planarization Method of Semiconductor Device Using Photoresist Etch Back
KR970018180A (en) Semiconductor device manufacturing method
KR960002569A (en) How to Form Metal Wiring Alignment Keys
KR970023808A (en) How to stabilize photoresist etch back step
KR960043120A (en) Via hole formation method of semiconductor device
KR960002665A (en) Method for manufacturing a conductive layer of a semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee