KR970052239A - Via contact formation method of semiconductor device - Google Patents
Via contact formation method of semiconductor device Download PDFInfo
- Publication number
- KR970052239A KR970052239A KR1019950050473A KR19950050473A KR970052239A KR 970052239 A KR970052239 A KR 970052239A KR 1019950050473 A KR1019950050473 A KR 1019950050473A KR 19950050473 A KR19950050473 A KR 19950050473A KR 970052239 A KR970052239 A KR 970052239A
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- KR
- South Korea
- Prior art keywords
- etching
- forming
- photoresist pattern
- mask
- reflection film
- Prior art date
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 비이콘택 형성방법에 관한 것으로, 아루미늄으로 형성된 제1금속배선 상부에 티타늄 질화막으로 형성된 반사방지막을 형성하고 그 상부에 평탄화층을 형성한 다음, 콘택마스크를 이용해 형성된 감광막패턴을 마스크로하여 상기 감광막패턴 사부에 언더컷을 형성하고 상기 평탄화층을 건식식각하되, 불소계 가스를 이용한 과도식각을 수반하여 소정두께의 반사방지막을 식각한 다음, 상기 감광막패턴을 마스크로하여 염소계 가스를 이용한 건식방법으로 상기 남아있는 반사방지막 그리고 상기 반사방지막과 제1금속배선의 반응으로 형성된 중간절연막을 식각함으로써 비아콘택홀을 형성하고 후속공정에 제2금속배선을 형성하여 안정된 비아콘택을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a non-contact of a semiconductor device, comprising forming an anti-reflection film formed of a titanium nitride film on an upper portion of a first metal wire formed of aluminum, and forming a planarization layer thereon, and then using a contact mask. Using a mask as an undercut to form an undercut on the photoresist pattern sand and dry etching the planarization layer, followed by etching the anti-reflection film of a predetermined thickness with the transient etching using a fluorine-based gas, and then using the photoresist pattern as a mask In the dry method, a via contact hole is formed by etching the remaining anti-reflection film and the intermediate insulating film formed by the reaction between the anti-reflection film and the first metal wiring, and a second metal wiring is formed in a subsequent process to form a stable via contact. Improve the characteristics and reliability of the device It is a technology for enabling high integration party.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1A도 내지 제1C도는 본 발명의 실시예에 따른 반도체소자의 비아콘택 형성공정을 도시한 단면도.1A to 1C are cross-sectional views illustrating a via contact forming process of a semiconductor device in accordance with an embodiment of the present invention.
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950050473A KR970052239A (en) | 1995-12-15 | 1995-12-15 | Via contact formation method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950050473A KR970052239A (en) | 1995-12-15 | 1995-12-15 | Via contact formation method of semiconductor device |
Publications (1)
Publication Number | Publication Date |
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KR970052239A true KR970052239A (en) | 1997-07-29 |
Family
ID=66595034
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950050473A KR970052239A (en) | 1995-12-15 | 1995-12-15 | Via contact formation method of semiconductor device |
Country Status (1)
Country | Link |
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KR (1) | KR970052239A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100596900B1 (en) * | 1999-06-10 | 2006-07-04 | 주식회사 하이닉스반도체 | Method for forming via contact of semiconductor device |
-
1995
- 1995-12-15 KR KR1019950050473A patent/KR970052239A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100596900B1 (en) * | 1999-06-10 | 2006-07-04 | 주식회사 하이닉스반도체 | Method for forming via contact of semiconductor device |
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