KR980005529A - METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR - Google Patents
METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR Download PDFInfo
- Publication number
- KR980005529A KR980005529A KR1019960024292A KR19960024292A KR980005529A KR 980005529 A KR980005529 A KR 980005529A KR 1019960024292 A KR1019960024292 A KR 1019960024292A KR 19960024292 A KR19960024292 A KR 19960024292A KR 980005529 A KR980005529 A KR 980005529A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- film
- etching
- metal wiring
- oxide film
- Prior art date
Links
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 평탄화층이 형성된 반도체기판 상부에 장벽금속층을 형성하고, 상기 장벽금속층 상부에 금속배선 물질인 텅스텐막을 소정두께 형성한 다음, 상기 텅스텐막 상부에 반사 방지막인 산화막을 소정두께 형성하고, 상기 산화막 상부에 감광막패턴을 형성한 다음, 상기 감광막패턴을 마스크로하여 상기 산화막과 텅스텐막을 한번에 식각하고, 상기 감광막패턴과 산화막을 마스크로 하여 상기 장벽금속층을 식각함으로써 식각잔유물의 유발을 방지하고 후속공정으로 금속배선의 손상을 방지하는 안정한 금속배선을 형성함으로써 반도체소자의 수율을 향상시키며, 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, which comprises forming a barrier metal layer on a semiconductor substrate on which a planarization layer is formed, forming a tungsten film as a metal wiring material on the barrier metal layer to a predetermined thickness, Forming an oxide film as an antireflection film to a predetermined thickness, forming a photoresist pattern on the oxide film, etching the oxide film and the tungsten film using the photoresist pattern as a mask, etching the barrier metal layer using the photoresist pattern and the oxide film as masks, It is possible to improve the yield of semiconductor devices, improve the characteristics and reliability of semiconductor devices, and achieve high integration of semiconductor devices by forming stable metal wiring that prevents etching residue by etching and prevents damage to metal wiring by subsequent processes. Technology.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제1a도 내지 제1c도는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.FIGS. 1A through 1C are cross-sectional views illustrating a method of forming a metal wiring of a semiconductor device according to an embodiment of the present invention; FIGS.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960024292A KR980005529A (en) | 1996-06-27 | 1996-06-27 | METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960024292A KR980005529A (en) | 1996-06-27 | 1996-06-27 | METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR |
Publications (1)
Publication Number | Publication Date |
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KR980005529A true KR980005529A (en) | 1998-03-30 |
Family
ID=66240287
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960024292A KR980005529A (en) | 1996-06-27 | 1996-06-27 | METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR |
Country Status (1)
Country | Link |
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KR (1) | KR980005529A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100380277B1 (en) * | 2000-08-22 | 2003-04-16 | 주식회사 하이닉스반도체 | Method of defining micropatterns |
-
1996
- 1996-06-27 KR KR1019960024292A patent/KR980005529A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100380277B1 (en) * | 2000-08-22 | 2003-04-16 | 주식회사 하이닉스반도체 | Method of defining micropatterns |
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