KR980005529A - METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR - Google Patents

METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR Download PDF

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Publication number
KR980005529A
KR980005529A KR1019960024292A KR19960024292A KR980005529A KR 980005529 A KR980005529 A KR 980005529A KR 1019960024292 A KR1019960024292 A KR 1019960024292A KR 19960024292 A KR19960024292 A KR 19960024292A KR 980005529 A KR980005529 A KR 980005529A
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KR
South Korea
Prior art keywords
forming
film
etching
metal wiring
oxide film
Prior art date
Application number
KR1019960024292A
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Korean (ko)
Inventor
이승욱
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960024292A priority Critical patent/KR980005529A/en
Publication of KR980005529A publication Critical patent/KR980005529A/en

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  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 평탄화층이 형성된 반도체기판 상부에 장벽금속층을 형성하고, 상기 장벽금속층 상부에 금속배선 물질인 텅스텐막을 소정두께 형성한 다음, 상기 텅스텐막 상부에 반사 방지막인 산화막을 소정두께 형성하고, 상기 산화막 상부에 감광막패턴을 형성한 다음, 상기 감광막패턴을 마스크로하여 상기 산화막과 텅스텐막을 한번에 식각하고, 상기 감광막패턴과 산화막을 마스크로 하여 상기 장벽금속층을 식각함으로써 식각잔유물의 유발을 방지하고 후속공정으로 금속배선의 손상을 방지하는 안정한 금속배선을 형성함으로써 반도체소자의 수율을 향상시키며, 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, which comprises forming a barrier metal layer on a semiconductor substrate on which a planarization layer is formed, forming a tungsten film as a metal wiring material on the barrier metal layer to a predetermined thickness, Forming an oxide film as an antireflection film to a predetermined thickness, forming a photoresist pattern on the oxide film, etching the oxide film and the tungsten film using the photoresist pattern as a mask, etching the barrier metal layer using the photoresist pattern and the oxide film as masks, It is possible to improve the yield of semiconductor devices, improve the characteristics and reliability of semiconductor devices, and achieve high integration of semiconductor devices by forming stable metal wiring that prevents etching residue by etching and prevents damage to metal wiring by subsequent processes. Technology.

Description

반도체 소자의 금속 배선 형성방법METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1a도 내지 제1c도는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.FIGS. 1A through 1C are cross-sectional views illustrating a method of forming a metal wiring of a semiconductor device according to an embodiment of the present invention; FIGS.

Claims (6)

평탄화층이 형성된 반도체기판 상부에 장벽금속층을 형성하는 공정과, 상기 장벽금속층 상부에 금속배선 물질인 텅스텐막을 소정두께 형성하는 공정과, 상기 텅스텐막 상부에 반사방지막인 산화막을 소정두께 형성하는 공정과, 상기 산화막 상부에 감광막패턴을 형성하는 과정과 상기 감광막패턴을 마스크로하여 상기 산화막과 텅스텐막을 한번에 식각하는 공정과, 상기 감광막패턴과 산화막을 마스크로 하여 상기 장벽금속층을 식각하는 공정을 포함하는 반도체소자의 금속배선 형성방법.A step of forming a predetermined thickness of a tungsten film as a metal wiring material on the barrier metal layer, a step of forming a predetermined thickness of an oxide film as an antireflection film on the tungsten film, A step of forming a photoresist pattern on the oxide film, a step of etching the oxide film and the tungsten film all at once using the photoresist pattern as a mask, and a step of etching the barrier metal layer using the photoresist pattern and the oxide film as masks. A method for forming a metal wiring of a device. 제1항에 있어서, 상기 장벽금속층은 티타늄막/티타늄질화막이 각각 100~1000Å 정도의 적층되 구조로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method according to claim 1, wherein the barrier metal layer is formed by stacking a titanium film / a titanium nitride film to a thickness of about 100 to 1000 angstroms. 제1항에 있어서, 상기 텅스텐막은 1000~5000Å 정도의 두께로 형성하는 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the tungsten film is formed to a thickness of about 1000 to 5000 ANGSTROM. 제1항에 있어서,상기 산화막은 300 ~2000Å 정도의 두께로 증착하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the oxide layer is deposited to a thickness of about 300 to 2000 ANGSTROM. 제1항에 있어서, 상기 산화막 텅스텐막 식각공정은 불소계 가스를 이용하여 실시하는 것을 특징으로하는 반도체소자의 금속배선 형성방법.The method according to claim 1, wherein the etching of the tungsten oxide film is performed using a fluorine-based gas. 제1항에 있어서, 상기 장벽금속층 식각공정은 불소계 가스를 이용하여 실시하는 것을 특징으로하는 반도체소자의 금속배선 형성방법.The method according to claim 1, wherein the step of etching the barrier metal layer is performed using a fluorine-based gas. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960024292A 1996-06-27 1996-06-27 METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR KR980005529A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960024292A KR980005529A (en) 1996-06-27 1996-06-27 METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960024292A KR980005529A (en) 1996-06-27 1996-06-27 METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR

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KR980005529A true KR980005529A (en) 1998-03-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100380277B1 (en) * 2000-08-22 2003-04-16 주식회사 하이닉스반도체 Method of defining micropatterns

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100380277B1 (en) * 2000-08-22 2003-04-16 주식회사 하이닉스반도체 Method of defining micropatterns

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