KR100290910B1 - Method for fabricating metal line of semiconductor device - Google Patents
Method for fabricating metal line of semiconductor device Download PDFInfo
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- KR100290910B1 KR100290910B1 KR1019990011025A KR19990011025A KR100290910B1 KR 100290910 B1 KR100290910 B1 KR 100290910B1 KR 1019990011025 A KR1019990011025 A KR 1019990011025A KR 19990011025 A KR19990011025 A KR 19990011025A KR 100290910 B1 KR100290910 B1 KR 100290910B1
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 29
- 239000002184 metal Substances 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 27
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 26
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 3
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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Abstract
배선형성을 위한 감광막 노광시에 반응잔유물이 발생하는 것을 방지하여서 신뢰성있는 배선을 형성할 수 있는 반도체소자의 배선 형성방법을 제공하는 데 그 목적이 있는 것으로써, 이와 같은 목적을 달성하기 위한 반도체소자의 배선 형성방법은 반도체기판상에 베리어금속층과 주배선층과 반사방지막을 차례로 증착하는 공정, 상기 반사방지막상에 감광막 또는 노광원과의 반응을 억제할 수 있는 물질층을 증착하는 공정, 상기 물질층상에 감광막을 도포한 후 노광 및 패터닝하는 공정, 상기 패터닝된 감광막을 마스크로 상기 물질층 및 상기 반사방지막, 주배선층, 베리어금속층을 차례로 식각하는 공정을 포함함을 특징으로 한다.The object of the present invention is to provide a method for forming a wiring of a semiconductor device capable of forming a reliable wiring by preventing a reaction residue from being generated during exposure of a photosensitive film for forming a wiring. The wire forming method of the method comprises depositing a barrier metal layer, a main wiring layer, and an antireflection film on a semiconductor substrate, and depositing a material layer capable of suppressing a reaction with a photosensitive film or an exposure source on the antireflection film. Exposing and patterning the photoresist film, and then etching the material layer, the anti-reflection film, the main wiring layer, and the barrier metal layer using the patterned photoresist as a mask.
Description
본 발명은 반도체소자의 배선형성방법에 대한 것으로, 특히 적층형 메탈배선을 노광 및 식각으로 형성할 때 식각잔유물이 발생하지 않도록하기에 적당한 반도체소자의 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a wiring of a semiconductor device, and more particularly, to a method of forming a wiring of a semiconductor device suitable for preventing etching residues from occurring when a stacked metal wiring is formed by exposure and etching.
첨부 도면을 참조하여 종래 반도체소자의 배선 형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method of forming a wiring of a conventional semiconductor device will be described below.
도 1a 내지 도 1c는 종래 적층형 메탈배선의 형성방법을 나타낸 공정단면도이고, 도 3은 적층된 메탈의 구성에 따른 이물발생 테스트결과를 나타낸 데이블이다.1A to 1C are cross-sectional views illustrating a method of forming a conventional stacked metal wiring, and FIG. 3 is a table showing a test result of foreign matters according to the structure of the stacked metal.
종래 반도체소자의 배선 형성방법은 도 1a에 도시한 바와 같이 반도체기판(1)의 소정부분에 콘택홀을 형성하고 콘택홀내에 텅스텐플러그(2)를 형성한다. 그리고 텅스텐플러그(2)를 포함한 반도체기판(1)상에 Ti/TiN으로 구성된 베리어메탈층(3)과 알루미늄배선층(4)과 Ti/TiN으로 구성된 반사방지막(5)을 차례로 증착한다.In the conventional method for forming a wiring of a semiconductor device, as shown in FIG. 1A, a contact hole is formed in a predetermined portion of the semiconductor substrate 1, and a tungsten plug 2 is formed in the contact hole. Then, a barrier metal layer 3 composed of Ti / TiN, an aluminum wiring layer 4, and an antireflection film 5 composed of Ti / TiN are sequentially deposited on the semiconductor substrate 1 including the tungsten plug 2.
이후에 도 1b에 도시한 바와 같이 반사방지막(5)상에 감광막(6)을 도포한 후에 딥 유브이(Deep UV:DUV)나 이빔(E-BEAM)의 노광원을 이용해서 감광막(6)을 노광한 후 텅스텐플러그(2)의 상측에만 남도록 감광막(6)을 패터닝한다.Subsequently, as shown in FIG. 1B, the photoresist film 6 is coated on the antireflection film 5, and then the photoresist film 6 is formed using an exposure source of Deep UV (DUV) or E-BEAM. After exposure, the photosensitive film 6 is patterned so that only the upper side of the tungsten plug 2 remains.
이때 반사방지막(5)의 TiN을 구성하는 TiSi와 감광막(6)이 반응하여서 반응 잔여물(Residue)이 발생하고 또한 E-BEAM에 의해 반사방지막(5)이 변성되어서 감광막(6)의 일측에 감광막(6)이 남는 감광막 풋팅(Footing)과 같은 이물질(7)이 발생된다.At this time, TiSi constituting TiN of the anti-reflection film 5 reacts with the photosensitive film 6 to generate a reaction residue, and the anti-reflection film 5 is denatured by E-BEAM to the side of the photosensitive film 6. The foreign matter 7 such as the photosensitive film footing in which the photosensitive film 6 remains is generated.
다음에 도 1c에 도시한 바와 같이 상기 패터닝된 감광막(6)을 마스크로 반사방지막(5)과 알루미늄배선층(4)과 베리어메탈층(3)을 차례로 식각한다. 이때 노광시 발생된 이물질(7)에 의해서 식각잔여물(8)이 발생된다.Next, as shown in FIG. 1C, the anti-reflection film 5, the aluminum wiring layer 4, and the barrier metal layer 3 are sequentially etched using the patterned photosensitive film 6 as a mask. At this time, the etching residue 8 is generated by the foreign matter 7 generated during exposure.
그리고 도 3에 도시한 바와 같이 Ti/TiN(베리어메탈층), Al(알루미늄 배선층), Arc Ti/TiN(반사방지막)으로 구성된 배선을 형성할 때는 DUV나 E-BEAM으로 노광할 때 모두 스팟(Spot)이물과 풋팅(Footing)이물이 발생됨을 알 수 있다.As shown in FIG. 3, when forming a wiring composed of Ti / TiN (barrier metal layer), Al (aluminum wiring layer), and Arc Ti / TiN (antireflection film), all spots are exposed when exposed with DUV or E-BEAM. Spot) and footing (Footing) foreign matter can be seen that occurs.
상기와 같은 종래 반도체소자의 배선 형성방법은 다음과 같은 문제가 있다.The wiring formation method of the conventional semiconductor device as described above has the following problems.
E-BEAM을 사용하여 감광막을 노광할 때 반사방지막을 구성하는 TiN의 구성요소중 TiSi와 TiO에 의해서 반응잔유물이 발생하고, 또한 E-BEAM에 의해 TiN이 변성되어 반사방지막상에 스팟(Spot)성 이물과 감광막하부 일측에 풋팅(Footing) 현상이 발생하므로, 차후에 배선의 저항이 증가되고 또한 배선의 씨디(Critical Demension:CD)가 커지는 문제가 있다.When exposing the photoresist using E-BEAM, reaction residues are generated by TiSi and TiO among TiN constituents of the antireflection film, and TiN is denatured by E-BEAM to spot on the antireflection film. Since footing occurs on one side of the foreign material and the lower part of the photoresist, there is a problem that the resistance of the wiring is increased later and the CD (Critical Demension) of the wiring is increased.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 배선형성을 위한 감광막 노광시에 반응잔유물이 발생하는 것을 방지하여서 신뢰성있는 배선을 형성할 수 있는 반도체소자의 배선 형성방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in particular, to provide a method for forming a wiring of a semiconductor device capable of forming reliable wiring by preventing a reaction residue from occurring during exposure of a photosensitive film for forming wiring. The purpose is.
도 1a 내지 도 1c는 종래 적층형 메탈배선의 형성방법을 나타낸 공정단면도1A through 1C are cross-sectional views illustrating a method of forming a conventional stacked metal wiring.
도 2a 내지 도 2c는 본 발명 적층형 메탈배선의 형성방법을 나타낸 공정단면도2a to 2c is a cross-sectional view showing a method of forming a laminated metal wiring of the present invention
도 3은 적층된 메탈의 구성에 따른 이물발생 테스트결과를 나타낸 데이블3 is a table showing a foreign material generation test results according to the configuration of the laminated metal
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 텅스텐플러그21 semiconductor substrate 22 tungsten plug
23 : 베리어메탈층 24 : 제 1 알루미늄배선층23: barrier metal layer 24: the first aluminum wiring layer
25 : 반사방지막 26 : 제 2 알루미늄배선층25 antireflection film 26 second aluminum wiring layer
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 배선 형성방법은 반도체기판상에 베리어금속층과 주배선층과 반사방지막을 차례로 증착하는 공정, 상기 반사방지막상에 감광막 또는 노광원과의 반응을 억제할 수 있는 물질층을 증착하는 공정, 상기 물질층상에 감광막을 도포한 후 노광 및 패터닝하는 공정, 상기 패터닝된 감광막을 마스크로 상기 물질층 및 상기 반사방지막, 주배선층, 베리어금속층을 차례로 식각하는 공정을 포함함을 특징으로 한다.The wiring forming method of the semiconductor device of the present invention for achieving the above object is a step of depositing a barrier metal layer, a main wiring layer and an anti-reflection film on a semiconductor substrate in order, to suppress the reaction with a photosensitive film or an exposure source on the anti-reflection film A process of depositing a layer of a material, a process of exposing and patterning a photoresist film on the material layer, and then etching the material layer, the anti-reflection film, the main wiring layer, and the barrier metal layer using the patterned photoresist as a mask. It is characterized by including.
첨부 도면을 참조하여 본 발명 반도체소자의 배선 형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a wiring forming method of the semiconductor device of the present invention will be described.
도 2a 내지 도 2c는 본 발명 적층형 메탈배선의 형성방법을 나타낸 공정단면도이고, 도 3은 적층된 메탈의 구성에 따른 이물발생 테스트결과를 나타낸 데이블이다.2A to 2C are cross-sectional views illustrating a method of forming a stacked metal wire according to the present invention, and FIG. 3 is a table showing a foreign material generation test result according to the structure of the stacked metal.
본 발명은 Ti/TiN으로 형성된 반사방지막이 감광막을 노광시킬 때 반응하거나, 또는 Ti/TiN으로 형성된 반사방지막이 E-빔(beam)에 의해서 스팟(spot)성 반응이물이 형성되거나 감광막의 하부 일측면에 감광막이 잔유하는 풋팅(Footing)을 방지하기 위해서 반사방지막상에 얇은 두께의 알루미늄층이나 산화막을 형성한 후에 배선을 형성하는 것에 대한 것으로써, 그 형성방법은 다음과 같다.The present invention reacts when the anti-reflection film formed of Ti / TiN exposes the photosensitive film, or the anti-reflection film formed of Ti / TiN reacts with a spot reaction substance formed by an E-beam or lower part of the photosensitive film. In order to prevent the footing of the photoresist film remaining on one side, the wiring is formed after forming a thin aluminum layer or an oxide film on the anti-reflection film.
본 발명 반도체소자의 배선 형성방법은 도 2a에 도시한 바와 같이 반도체기판(21)의 소정부분에 콘택홀을 형성하고 콘택홀내에 텅스텐플러그(22)를 형성한다. 그리고 텅스텐플러그(22)를 포함한 반도체기판(21)상에 Ti/TiN으로 구성된 베리어메탈층(23)과 제 1 알루미늄배선층(24)과 Ti/TiN으로 구성된 반사방지막(25)을 차례로 증착한 후에 반사방지막(25)상에 얇은 두께의 제 2 알루미늄배선층(26)을 형성한다. 여기서 제 2 알루미늄배선층(26)은 차후에 도포된 감광막을 노광시킬 때 노광원과 반응하는 것을 방지하기 위한 것으로써, 제 2 알루미늄배선층(26) 대신에 산화막을 증착할 수도 있다. 이때 상기 제 2 알루미늄배선층(26)은 50∼1000Å 범위의 두께를 갖도록 증착하고, 산화막을 증착할 경우에는 100∼2000Å 범위의 두께를 갖도록 증착한다.In the method for forming a wiring of the semiconductor device of the present invention, as shown in FIG. 2A, a contact hole is formed in a predetermined portion of the semiconductor substrate 21, and a tungsten plug 22 is formed in the contact hole. After depositing the barrier metal layer 23 made of Ti / TiN, the first aluminum wiring layer 24, and the antireflection film 25 made of Ti / TiN on the semiconductor substrate 21 including the tungsten plug 22 in this order. The second aluminum wiring layer 26 having a thin thickness is formed on the antireflection film 25. In this case, the second aluminum wiring layer 26 is for preventing the reaction with an exposure source when exposing the subsequently applied photosensitive film, and an oxide film may be deposited instead of the second aluminum wiring layer 26. At this time, the second aluminum wiring layer 26 is deposited to have a thickness in the range of 50 to 1000 kPa, and when the oxide film is deposited, it is deposited to have a thickness in the range of 100 to 2000 kPa.
다음에 도 2b에 도시한 바와 같이 상기 제 2 알루미늄배선층(26)상에 감광막(27)을 도포한 후에 딥 유브이(Deep UV:DUV)나 이빔(E-BEAM)의 노광원을 이용해서 감광막(27)을 노광한 후 텅스텐플러그(22)의 상측에만 남도록 감광막(27)을 패터닝한다.Next, as shown in FIG. 2B, the photoresist layer 27 is coated on the second aluminum wiring layer 26, and then the photoresist layer (eg, a deep UV (DUV) or an E-BEAM exposure source is used). After exposing 27, the photosensitive film 27 is patterned so that only the upper side of the tungsten plug 22 remains.
그리고 도 2c에 도시한 바와 같이 상기 패터닝된 감광막(27)을 마스크로 제 2 알루미늄배선층(26)과 반사방지막(25)과 제 1 알루미늄배선층(24)과 베리어메탈층(23)을 차례로 식각한다.As shown in FIG. 2C, the second aluminum wiring layer 26, the antireflection film 25, the first aluminum wiring layer 24, and the barrier metal layer 23 are sequentially etched using the patterned photosensitive film 27 as a mask. .
상기에서 제 2 알루미늄배선층(26)대신에 산화막을 사용하였을 때에는 산화막 식각용 하드 마스크(Hard mask)를 이용해서 산화막을 식각하고, 이후에 반사방지막(25)과 제 1 알루미늄배선층(24)과 베리어메탈층(23)을 차례로 식각한다. 이때는 감광막(27)의 두께를 낮게 하여도 되기 때문에 감광막의 노광 마진을 극대화시킬 수 있다.When the oxide film is used instead of the second aluminum wiring layer 26, the oxide film is etched using an oxide film hard mask, and then the antireflection film 25, the first aluminum wiring layer 24, and the barrier are used. The metal layer 23 is sequentially etched. At this time, since the thickness of the photosensitive film 27 may be made low, the exposure margin of the photosensitive film can be maximized.
상기에서 제 2 알루미늄배선층(26)을 식각할 때의 식각가스로는 Cl2, BCl3, N2을 사용하고, 산화막을 식각할 경우의 식각가스로는 CxFy계열과 아르곤, 산소(O2), 질소(N2)를 사용한다.When etching the second aluminum wiring layer 26, Cl 2 , BCl 3 , N 2 is used as an etching gas, and when etching the oxide film, CxFy series, argon, oxygen (O 2 ), and nitrogen are used as etching gases. (N 2 ) is used.
다음에 상기에서 반사방지막(25)과 제 2 알루미늄배선층(26) 또는 반사방지막(25)과 산화막을 형성하지 않고, 베리어메탈층(23)과 제 1 알루미늄배선층(24)상에 직접 감광막을 도포한 후에 DUV나 E-BEAM을 이용하여 감광막을 노광한 후에 패터닝하여서 배선을 식각할 수도 있다.Next, the photoresist film is applied directly onto the barrier metal layer 23 and the first aluminum wiring layer 24 without forming the antireflection film 25 and the second aluminum wiring layer 26 or the antireflection film 25 and the oxide film. After that, the photosensitive film may be exposed using DUV or E-BEAM and then patterned to etch the wiring.
도 3에 도시한 바와 같이 Ti/TiN(베리어메탈층), Al(제 1 알루미늄배선층), Arc Ti/TiN(확산방지막), Al(제 2 알루미늄배선층) 및 Ti/TiN(베리어메탈층), Al, Arc Ti/TiN(확산방지막), Ox HM(Hard Mask)(산화막)으로 구성된 적층형 메탈배선은 Al(제 2 알루미늄배선층)이나 Ox HM(Hard Mask)(산화막)을 더 증착하므로 인해서 DUV나 E-BEAM에 의한 노광공정시에 스팟(Spot)이물이나 풋팅(Footing)이물이 발생되지 않는 것을 알 수 있다.As shown in Fig. 3, Ti / TiN (barrier metal layer), Al (first aluminum wiring layer), Arc Ti / TiN (diffusion prevention film), Al (second aluminum wiring layer) and Ti / TiN (barrier metal layer), Laminated metal wiring consisting of Al, Arc Ti / TiN (diffusion barrier), and Ox HM (Hard Mask) (oxide film) is further deposited by DUV or DUV due to further deposition of Al (second aluminum wiring layer) or Ox HM (Hard Mask) (oxide film). It can be seen that no spot foreign matter or footing foreign matter occurs during the exposure process by E-BEAM.
또한 베리어메탈층(23)과 제 1 알루미늄배선층(24)상에 직접 감광막을 도포한 후에 DUV나 E-BEAM을 이용하여 감광막을 노광한 후에 패터닝하여서 배선을 식각할 경우에도 DUV에서 풋팅이물이 발생하는 것을 제외하고는 E-BEAM에서는 스팟이물과 풋팅이물이 발생하지 않음을 알 수 있다. 이때는 E-BEAM을 노광원으로 사용한다.In addition, in the case of etching the wiring by applying a photoresist film directly on the barrier metal layer 23 and the first aluminum interconnection layer 24 and then exposing the photoresist film using DUV or E-BEAM, the foreign body in the DUV is exposed. Except for the occurrence of E-BEAM, spot foreign matter and putting foreign matter do not occur. In this case, E-BEAM is used as the exposure source.
상기와 같은 본 발명 반도체소자의 배선 형성방법은 다음과 같은 효과가 있다.The wiring forming method of the semiconductor device of the present invention as described above has the following effects.
첫째, Ti/TiN으로 구성된 확산방지막상에 제 2 알루미늄배선층이나 산화막을 더 증착한 후에 감광막을 노광하여 패터닝하므로 감광막이 TiN과 반응하여 식각잔유물이 발생하는 것을 방지할 수 있고, 이에 따라서 차후에 적층형의 배선을 형성한 후에도 잔유물이 발생되지 않으므로 배선의 저항 및 배선의 신뢰성이 향상된다.First, since the second photoresist layer or oxide film is further deposited on the diffusion barrier layer made of Ti / TiN, the photoresist layer is exposed and patterned, thereby preventing the photoresist from reacting with TiN and generating etch residues. Since no residue is generated even after the wiring is formed, the resistance of the wiring and the reliability of the wiring are improved.
둘째, 미세배선 형성시에 이물의 발생이 없으므로, 이물에 의한 배선의 씨디(Critical Demension:CD)가 증가되는 것을 막을 수 있다.Second, since there is no foreign matter during the formation of the micro wiring, it is possible to prevent the increase in the CD (Critical Demension) of the wiring by the foreign matter.
셋째, 별도의 공정 추가 없이 기존의 적층형 메탈배선층 형성방법을 적용할 수 있으므로 공정이 용이하다.Third, the process is easy because the existing method of forming a layered metal wiring layer can be applied without adding a separate process.
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