KR100464660B1 - Etch byproduct removal method of semiconductor device - Google Patents

Etch byproduct removal method of semiconductor device Download PDF

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KR100464660B1
KR100464660B1 KR1019970055952A KR19970055952A KR100464660B1 KR 100464660 B1 KR100464660 B1 KR 100464660B1 KR 1019970055952 A KR1019970055952 A KR 1019970055952A KR 19970055952 A KR19970055952 A KR 19970055952A KR 100464660 B1 KR100464660 B1 KR 100464660B1
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etching
metal
products
semiconductor device
exposed
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KR19990034357A (en
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이형섭
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

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Abstract

본 발명은 반도체 소자의 식각부산물 제거방법에 관한 것으로, 종래에는 금속공정으로 금속배선을 형성한 후, 발생하는 식각부산물을 제거하는 특별한 방법이 없어 식각부산물의 잔류로 인해 금속배선간에 전기적인 쇼트가 발생하여 반도체 소자의 수율이 감소하는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 고 에너지의 광을 조사하는 사진식각공정을 통해 금속전극사이에 잔존하는 식각부산물을 노출시키는 식각부산물 노출단계와; 상기 노출된 식각부산물을 플라즈마 식각법으로 식각하는 식각부산물 제거단계로 이루어져 금속공정 후에 발생한 식각부산물을 높은 에너지의 광을 사용하는 사진식각공정으로 노출시키고, 플라즈마 식각을 이용하여 모두 제거함으로써, 반도체 소자의 불량을 감소시켜 수율을 증가시키는 효과가 있다.The present invention relates to a method for removing etch by-products of a semiconductor device. In the related art, there is no special method for removing etch by-products formed after forming a metal wiring by a metal process. There was a problem that the yield of the semiconductor device is reduced. In view of the above problems, the present invention includes an etching by-product exposure step of exposing the remaining etching by-products between the metal electrodes through a photolithography process for irradiating high energy light; The etching by-products are removed by etching the exposed etching by-products by plasma etching. The etching by-products generated after the metal process are exposed by a photolithography process using high energy light, and all are removed by plasma etching. There is an effect of increasing the yield by reducing the defect of.

Description

반도체 소자의 식각부산물 제거방법Etch byproduct removal method of semiconductor device

본 발명은 반도체 소자의 식각부산물 제거방법에 관한 것으로, 특히 반도체 소자가 증착된 기판의 상부에 금속을 증착하고, 1차의 사진식각공정을 통해 식각하고 이때 발생하는 식각부산물을 다시 노광에너지를 증가시킨 2차의 사진식각공정을 통해 식각함으로써, 식각부산물을 완전히 제거하여 반도체 소자의 수율을 증가시키는데 적당하도록 한 반도체 소자의 식각부산물 제거방법에 관한 것이다.The present invention relates to a method for removing etch byproducts of a semiconductor device, and in particular, depositing a metal on the substrate on which the semiconductor device is deposited, and etching through a first photolithography process to increase exposure energy of the etch byproducts generated at this time. By etching through the secondary photolithography process, the etching by-products of the semiconductor device to remove the etching by-products to increase the yield of the semiconductor device.

일반적으로, 실리콘 기판 등에 형성한 반도체 소자는 외부와의 전적인 연결을 위하여 그 상부에 금속배선을 형성하게 되며, 그 금속배선은 알루미늄 등의 금속을 증착하고, 그 증착된 금속의 상부에 포토레지스트를 도포하고, 노광하여 금속배선의 패턴을 형성하고, 그 패턴이 형성된 포토레지스트를 식각 마스크로 하는 건식식각으로 금속의 일부를 선택적으로 식각 하여 형성하였다. 이와 같은 과정에서 금속의 식각될 부분이 완전히 식각 되지 않거나, 식각부산물이 남아있게 되면 두 금속배선간에 쇼트가 발생하여 그 배선에 접속된 반도체 소자를 사용할 수 없었으며, 이와 같이 식각부산물을 제거하는 방법이 없어 처음 금속을 식각 하는 공정에서 완전한 식각이 이루어지도록 하였으며, 이와 같은 종래 금속공정을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, a semiconductor device formed on a silicon substrate or the like forms a metal wiring on the upper part for total connection with the outside, and the metal wiring deposits a metal such as aluminum and a photoresist on the deposited metal. After coating and exposing, a pattern of metal wiring was formed, and a part of the metal was selectively etched by dry etching using the photoresist on which the pattern was formed as an etching mask. In this process, if the portion to be etched of the metal is not completely etched or the etch by-products remain, short circuit occurs between the two metal wires, and thus a semiconductor device connected to the wires cannot be used. Since there is no first to complete etching in the process of etching the metal, it will be described in detail with reference to the accompanying drawings, such a conventional metal process as follows.

도1은 종래 금속공정 후 웨이퍼의 평면도이며, 도2는 상기 도1의 단면도로서, 이에 도시한 바와 같이 반도체 소자가 형성된 기판(1)의 상부에 절연층(2)을 증착하고, 그 절연층(2)에 콘택홀을 형성하여 상기 반도체 소자의 특정영역을 노출시키는 단계와; 상기 콘택홀과 절연층(2)의 상부전면에 금속(3), 절연층(4), 금속(5)을 순차적으로 증착하고, 사진식각공정을 통해 상기 금속(5), 절연층(4) 및 금속(3)의 일부를 식각 하여 다층의 금속배선(3),(5)을 형성하는 단계로 구성된다.1 is a plan view of a wafer after a conventional metal process, and FIG. 2 is a cross-sectional view of FIG. 1, in which an insulating layer 2 is deposited on top of a substrate 1 on which a semiconductor element is formed, as shown in FIG. Forming a contact hole in (2) to expose a specific region of the semiconductor device; The metal 3, the insulating layer 4, and the metal 5 are sequentially deposited on the upper surface of the contact hole and the insulating layer 2, and the metal 5 and the insulating layer 4 are formed by a photolithography process. And etching a part of the metal 3 to form multilayer metal wirings 3 and 5.

이때의 사진식각공정은 금속(5)의 상부에 포토레지스트를 도포하고, 그 포토레지스트의 상부에 마스크를 배치한 후, 소정 에너지의 광을 조사하여 포토레지스트에 패턴을 형성한다. 그리고, 그 포토레지스트의 일부를 제거하고, 다시 잔존하는 포토레지스트를 식각 마스크로 사용하는 건식식각으로 노출된 금속(5)을 식각하고, 그 식각공정으로 인해 노출되는 절연층(4)과 금속(3)을 차례로 식각 하게 되며, 이러한 과정에서 식각의 종료점을 정확히 맞추지 못하면, 도1 및 도2에 도시한 바와 같이 금속배선(3)간에 금속 식각부산물(6) 또는 식각 되지 않은 금속이 남게 된 체로 공정을 완료하게 된다.In this photolithography process, a photoresist is applied on the upper portion of the metal 5, a mask is disposed on the photoresist, and light is irradiated with a predetermined energy to form a pattern on the photoresist. Then, a part of the photoresist is removed, and the exposed metal 5 is dried by dry etching using the remaining photoresist as an etching mask, and the insulating layer 4 and the metal ( 3) are sequentially etched, and in this process, if the end point of the etch cannot be accurately matched, as shown in FIGS. 1 and 2, the metal etching by-product (6) or the unetched metal remains between the metal wires (3). The process is complete.

상기한 바와 같이 종래의 금속공정은 1차적인 사진식각공정으로 금속을 식각 하여 금속배선을 형성함으로써, 식각부산물이 발생한 경우에 그 식각부산물을 제거하는 방법이 없어 식각부산물에 의한 금속배선간에 전기적인 접속이 발생하여 반도체 소자의 수율이 감소하는 문제점이 있었다.As described above, in the conventional metal process, a metal wiring is formed by etching a metal by a primary photolithography process, and thus, when an etching by-product occurs, there is no method of removing the etching by-products. There was a problem that the connection occurred and the yield of the semiconductor element was reduced.

이와 같은 문제점을 감안한 본 발명은 금속배선공정 후, 식각부산물을 제거할 수 있는 반도체 소자의 식각부산물 제거방법을 제공함에 그 목적이 있다. In view of the above problems, an object of the present invention is to provide an etching by-product removal method of a semiconductor device capable of removing etching by-products after a metallization process.

상기와 같은 목적은 고 에너지의 광을 조사하는 사진식각공정을 통해 금속전극사이에 잔존하는 식각부산물을 노출시키는 식각부산물 노출단계와; 상기 노출된 식각부산물을 플라즈마 식각법으로 식각 하는 식각부산물 제거단계로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is an etching by-product exposure step of exposing the remaining etching by-products between the metal electrode through a photolithography process of irradiating high energy light; It is achieved by the etching by-products removing step of etching the exposed etching by-products by plasma etching, described in detail with reference to the accompanying drawings, the present invention.

도3a 및 도3b는 본 발명 반도체 소자의 식각부산물 제거방법을 적용한 반도체 소자의 단면도로서, 이에 도시한 바와 같이 종래와 동일한 공정으로, 금속배선(3)간에 식각부산물(6)이 생성된 상태에서 그 금속배선(5)과 식각부산물(6)의 상부 전면에 포토레지스트(P/R)를 도포하고, 강한 에너지의 광을 조사하여 패턴을 형성한 후, 포토레지스트(P/R)의 일부를 제거하여 상기 식각부산물(6)을 노출시키는 단계(도3a)와; 그 다음 노출된 식각부산물(6)을 강한 직류바이어스를 사용하는 플라즈마 식각법으로 제거하는 단계(도3b)로 구성된다.3A and 3B are cross-sectional views of a semiconductor device to which the method for removing etching by-products of the semiconductor device of the present invention is applied. As shown in FIG. 3A and FIG. 3B, the etching by-products 6 are formed between the metal wires 3 in the same process as in the related art. The photoresist (P / R) is applied to the upper surface of the metal wiring 5 and the etching by-product 6, a pattern is formed by irradiating strong energy light, and then a part of the photoresist (P / R) is removed. Removing to expose the etch byproduct (6) (FIG. 3A); Then, the exposed etch by-product 6 is removed by plasma etching using a strong direct current bias (FIG. 3B).

이하, 상기와 같이 구성된 본 발명, 반도체 소자의 식각부산물 제거방법을 좀 더 상세히 설명한다.Hereinafter, the present invention configured as described above, the etching by-products removal method of the semiconductor device in more detail.

먼저, 종래와 동일한 방법으로 반도체 소자가 형성된 기판(1)의 상부에 절연층(2)을 증착하고, 그 절연층(2)에 콘택홀을 형성한 후, 그 콘택홀과 상기 절연층(2)의 상부에 금속(3)을 증착하고, 그 금속(3)의 상부에 절연층(4)과 금속(5)을 순차적으로 증착한 다음, 사진식각공정을 통해 상기 금속(5), 절연층(4), 금속(3)의 일부를 선택적으로 식각 하여 다층의 금속배선을 형성한다. 이때 역시 각 금속배선간에는 식각부산물(6)이 남아있게 된다.First, the insulating layer 2 is deposited on the substrate 1 on which the semiconductor element is formed in the same manner as in the prior art, and a contact hole is formed in the insulating layer 2, and then the contact hole and the insulating layer 2 The metal (3) is deposited on top of the metal layer, the insulating layer (4) and the metal (5) are sequentially deposited on the metal (3), and then the metal (5) and the insulating layer are formed through a photolithography process. (4) A portion of the metal 3 is selectively etched to form multilayer metal wiring. At this time, the etching by-product 6 remains between the metal wires.

그 다음, 도3a에 도시한 바와 같이 상기 금속(5)과 식각부산물(6)의 상부 전면에 포토레지스트(P/R)를 도포하고, 그 포토레지스트(P/R)를 노광한다. 이때, 조사하는 광의 에너지는 상기 금속배선 부분과 식각부산물(6)부분의 단차로 인해 노광해야 할 포토레지스트(P/R)영역이 두꺼워 보통 일반 포토레지스트 노광시 사용하는 에너지인 1930J/m2보다 큰 2500J/m2의 에너지로 노광한 후, 그 노광된 포토레지스트(P/R)를 제거하여 상기 식각부산물(6)을 노출시킨다.Then, as shown in FIG. 3A, photoresist (P / R) is applied to the entire upper surface of the metal 5 and the etching by-product 6, and the photoresist P / R is exposed. At this time, the energy of light to be irradiated is thicker than the photoresist (P / R) area to be exposed due to the step difference between the metal wiring part and the etching by-product (6) part, which is more than 1930J / m 2 which is the energy used for general photoresist exposure. After exposing with a large energy of 2500 J / m 2 , the exposed photoresist P / R is removed to expose the etch byproduct 6.

그 다음, 도3b에 도시한 바와 같이 플라즈마 식각법으로 상기 노출된 식각부산물(6)을 선택적으로 식각 한다. 이때, 플라즈마 식각은 직류바이어스를 최대한 높게 사용하여 식각을 실시한다. 이때의 플라즈마 식각공정에 의해 상기 식각부산물(6)의 하부 절연층(2)의 일부까지 식각이 일어나 식각부산물(6)을 완전히 제거할 수 있으며, 상기 절연층(4)의 상부 측면 일부 또한 식각되나 이는 금속배선의 특성에 영향을 주지 않는다. Next, as shown in FIG. 3B, the exposed etch by-product 6 is selectively etched by plasma etching. At this time, the plasma etching is performed using a DC bias as high as possible. In this case, etching may occur to a part of the lower insulating layer 2 of the etching by-product 6 by the plasma etching process, and the etching by-product 6 may be completely removed, and a part of the upper side of the insulating layer 4 may also be etched. However, this does not affect the characteristics of the metallization.

상기한 바와 같이 본 발명 반도체 소자의 식각부산물 제거방법은 금속공정 후에 발생한 식각부산물을 높은 에너지의 광을 사용하는 사진식각공정으로 노출시키고, 플라즈마 식각을 이용하여 모두 제거함으로써, 반도체 소자의 불량을 감소시켜 수율을 증가시키는 효과가 있다.As described above, the method of removing the etch byproducts of the semiconductor device of the present invention is to expose the etch byproducts generated after the metal process by a photolithography process using high energy light and to remove all of them by using plasma etching, thereby reducing defects of the semiconductor device. It is effective to increase the yield.

도1은 종래 금속배선이 형성된 반도체 소자의 평면도.1 is a plan view of a semiconductor device in which a conventional metal wiring is formed.

도2는 도1의 단면도.2 is a cross-sectional view of FIG.

도3a 및 도3b는 본 발명 반도체 소자의 식각부산물 제거단계를 보인 단면도.3A and 3B are cross-sectional views illustrating an etching byproduct removing step of the semiconductor device of the present invention.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

1:기판 2,4:절연층1: substrate 2, 4: insulation layer

3,5:금속3,5: metal

Claims (2)

고 에너지의 광을 조사하는 사진식각공정을 통해 금속전극사이에 잔존하는 식각부산물을 노출시키는 식각부산물 노출단계와; 상기 노출된 식각부산물을 플라즈마 식각법으로 식각 하는 식각부산물 제거단계로 이루어 진 것을 특징으로 하는 반도체 소자의 식각부산물 제거방법.An etching byproduct exposure step of exposing the remaining etching byproducts between the metal electrodes through a photolithography process of irradiating high energy light; And removing the etching by-products by etching the exposed etching by-products by plasma etching. 제 1항에 있어서, 상기 식각부산물 노출단계의 사진식각공정에서는 광을 2500J/m2의 에너지로 조사하는 것을 특징으로 하는 반도체 소자의 식각부산물 제거방법.The method of claim 1, wherein in the photolithography step of exposing the etching byproduct, light is irradiated with an energy of 2500 J / m 2 .
KR1019970055952A 1997-10-29 1997-10-29 Etch byproduct removal method of semiconductor device KR100464660B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04103123A (en) * 1990-08-23 1992-04-06 Nec Corp Wiring formation
JPH04278535A (en) * 1991-03-07 1992-10-05 Nec Corp Wiring formation method
KR970052634A (en) * 1995-12-14 1997-07-29 문정환 How to remove etch residue
KR970053589A (en) * 1995-12-29 1997-07-31 김주용 A semiconductor device manufacturing method comprising a multilayer metal layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04103123A (en) * 1990-08-23 1992-04-06 Nec Corp Wiring formation
JPH04278535A (en) * 1991-03-07 1992-10-05 Nec Corp Wiring formation method
KR970052634A (en) * 1995-12-14 1997-07-29 문정환 How to remove etch residue
KR970053589A (en) * 1995-12-29 1997-07-31 김주용 A semiconductor device manufacturing method comprising a multilayer metal layer

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