KR100268709B1 - Method for manufacturing metal interconnection of semiconductor device - Google Patents

Method for manufacturing metal interconnection of semiconductor device Download PDF

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KR100268709B1
KR100268709B1 KR1019970082290A KR19970082290A KR100268709B1 KR 100268709 B1 KR100268709 B1 KR 100268709B1 KR 1019970082290 A KR1019970082290 A KR 1019970082290A KR 19970082290 A KR19970082290 A KR 19970082290A KR 100268709 B1 KR100268709 B1 KR 100268709B1
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metal
metal layer
etching
photoresist pattern
film
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KR1019970082290A
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Korean (ko)
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KR19990061985A (en
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신강섭
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

Abstract

PURPOSE: A method for forming a metal interconnect of a semiconductor device is provided to assure the metal interconnect of a stable structure by performing a metal interconnect patterning process using a metal etching pattern. CONSTITUTION: A metal layer(12) comprising an aluminum alloy is deposited on an interlayer insulation film(10) to insulate a semiconductor device and an upper structure thereof. Next, a negative photoresist pattern is formed by performing a photo process to prevent the formation of a metal interconnect layer on the metal layer. An interlayer insulation film is formed on the metal layer including the photoresist pattern. The interlayer insulation film(17) is formed by depositing a TEOS film(16') and a SOG film(18) in sequence. And, the SOG film is planarized by a CMP process and then is hardened at 500 deg.C. Then, the SOG film and the TEOS film are etched by a blanket etching process until the surface of the photoresist pattern is revealed. Thus, a metal mask pattern is formed on a side of the photoresist pattern. Then, an opening aperture(14') opening the surface of the metal layer is formed by removing the photoresist pattern. And, the metal layer is etched using the metal mask pattern. And, a protection film(20) comprising a thin Al2O3 is formed on a side of the metal interconnect by an etching process using Cl2 and BCl3 and O3. And, a metal interconnect(12') is formed which is self-aligned to the metal etch mask by the protection film by etching the metal layer.

Description

반도체 장치의 금속 배선 형성 방법Metal wiring formation method of semiconductor device

본 발명은 반도체 장치의 금속 배선 형성 방법에 관한 것으로서, 특히 식각 선택비를 갖는 절연막으로 이루어진 금속 식각 패턴을 정의한 후에 이 패턴을 이용하여 금속 배선 패터닝 공정을 실시하므로 금속 배선 패터닝 공정의 신뢰성을 높일 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring in a semiconductor device, and in particular, after defining a metal etching pattern made of an insulating film having an etching selectivity, the metal wiring patterning process is performed using the pattern, thereby increasing the reliability of the metal wiring patterning process. It is a skill.

반도체 장치의 금속 패터닝 형성 기술은 통상적으로 다음과 같은 제조 공정을 가진다. 이러한 종래 금속 배선 제조 방법의 예는 국내특허공개 97-18351에 기재되어 있다.The metal patterning formation technique of a semiconductor device typically has the following manufacturing process. An example of such a conventional metal wire manufacturing method is described in Korean Patent Publication No. 97-18351.

도 7a 및 도 7b는 종래 기술에 의한 반도체 장치의 금속 배선 방법을 설명하기 위한 단면도이다.7A and 7B are cross-sectional views for explaining a metal wiring method of a semiconductor device according to the prior art.

도 7a 및 도 7b를 참조하면, 반도체 소자와 상부 구조물을 절연하기 위한 층간 절연막(10) 위에 Al 합금 등의 금속층(12)을 증착한다. 그 다음 금속층(12) 위에 사진 공정을 실시하여 포토레지스트를 1㎛이상의 두께로 도포하고, 스테퍼 또는 스케너를 이용하여 레티클에 빛을 조사하고, 이에 빛을 받는 부분과 받지 않는 부분의 노광 특성 차이를 이용하여 현상액을 뿌려주면 화학적 반응을 통해 양각성(positive) 포토레지스트 패턴(14)을 형성하게 된다.7A and 7B, a metal layer 12, such as an Al alloy, is deposited on the interlayer insulating layer 10 for insulating the semiconductor device and the upper structure. Then, the photoresist is applied to the metal layer 12 to a thickness of 1 μm or more, and the light is irradiated to the reticle using a stepper or a scanner, and the difference in the exposure characteristics between the part receiving and the light is different. When the developer is sprayed using the positive electrode, a positive photoresist pattern 14 is formed through a chemical reaction.

이러한 포토레지스트 패턴(14)에 맞추어 아래 금속층(12)을 패터닝하여 금속 배선을 형성하게 되는데, 이때 주로 패터닝 공정은 플라즈마 건식식각을 이용하게 된다.The metal layer 12 is patterned according to the photoresist pattern 14 to form metal lines. In this case, the patterning process mainly uses plasma dry etching.

그러나, 고직접화 반도체소자의 미세 금속 배선을 패터닝하기 위하여 포토레지스트 높이를 1.0㎛이상으로 두껍게 도포하던지 인라인(In-line) 스테퍼에서 0.4㎛ 정도 이하의 패턴, 및 긴 자외선에서 0.3㎛ 이하의 패턴을 형성하게 될 경우 이후 금속 식각 공정시 포토레지스트의 카본이 잔여되어 금속 배선 측면에 카본 폴리머가 쌓이게 된다. 이로 인해, 아래 도 8a 및 도 8b의 도면 부호 12''와 같이 금속 배선 패턴에 푸팅(footing) 또는 경사가 발생하게 된다.However, in order to pattern the fine metal wiring of the high-facing semiconductor device, the photoresist height is thickly applied to 1.0 mu m or more, or about 0.4 mu m or less in an in-line stepper, and 0.3 mu m or less in long ultraviolet rays. In the case of forming a metal, the carbon of the photoresist remains during the metal etching process, so that the carbon polymer is accumulated on the metal wiring side. As a result, footing or inclination occurs in the metal wiring pattern as shown by reference numerals 12 '' of FIGS. 8A and 8B.

도 8a 및 도 8b는 통상의 금속 배선 방법에 의해 금속배선의 디자인룰이 불량한 상태를 나타낸 도면들로서, 푸팅 또는 경사가 발생된 금속 배선(12'')의 형태를 나타낸 것이다.8A and 8B are diagrams illustrating a state in which a design rule of a metal wiring is poor by a conventional metal wiring method, and shows a form of a metal wiring 12 ″ in which footing or inclination occurs.

그러므로, 종래 기술은 고집적화 반도체소자에서 미세 금속 배선 패터닝시 금속 배선의 측면 디자인 룰이 불량하게 되어 다른 금속선 저항, 과도 에칭의 마진 저하 등 악영향을 끼치게 되므로 현재, 이를 개선하기 위한 새로운 금속 배선의 제조 공정이 요구되고 있는 실정이다.Therefore, the conventional technology is that the side design rules of the metal wiring is poor when patterning the fine metal wiring in the highly integrated semiconductor device, which adversely affects other metal wire resistance, margin of over-etching, etc. This situation is required.

본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 음극성 포토리소그래피 공정으로 식각 선택비를 갖는 절연막으로 이루어진 금속 식각 패턴을 정의한 후에 이 패턴을 이용하여 금속 배선 패터닝 공정을 실시하므로 안정한 형태의 금속 배선 패턴을 확보할 수 있는 반도체 장치의 금속 배선 형성 방법을 제공하는데 있다.An object of the present invention is to define a metal etching pattern consisting of an insulating film having an etch selectivity in the negative photolithography process in order to solve the problems of the prior art as described above and to perform a metal wiring patterning process using this pattern stable form The present invention provides a method for forming a metal wiring of a semiconductor device that can secure a metal wiring pattern.

도 1 내지 도 6은 본 발명에 따른 반도체 장치의 금속 배선 구조를 형성하기 위한 공정 순서도이다.1 to 6 are process flowcharts for forming a metal wiring structure of a semiconductor device according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10 : 실리콘 기판10: silicon substrate

12 : 금속층12: metal layer

12' : 금속 배선12 ': metal wiring

14 : 음각 포토레지스트 패턴14: Engraved Photoresist Pattern

16 : TEOS막16: TEOS film

18 : SOG막18: SOG film

20 : 보호막20: protective film

상기 목적을 달성하기 위하여 본 발명에 따른 반도체 장치의 금속 배선 형성 방법은 반도체 소자와 상부 구조물을 절연하기 위한 층간 절연막 위에 금속층을 증착하는 단계; 상기 금속층위에 금속 배선층이 형성되지 않도록 음각 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 포함한 금속층 위에 식각 선택비가 다른 물질로 이루어진 층간 절연막을 형성하는 단계; 상기 포토레지스트 패턴의 표면이 노출되도록 상기 층간 절연막을 평탄화하는 단계; 상기 포토레지스트 패턴을 제거하는 단계; 잔여된 층간 절연막을 금속 식각용 패턴을 사용하여 금속층을 식각하여 금속 배선을 형성하는 단계; 및 상기 금속 식각용 패턴을 제거하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention comprises the steps of depositing a metal layer on an interlayer insulating film for insulating the semiconductor device and the upper structure; Forming a negative photoresist pattern such that a metal wiring layer is not formed on the metal layer; Forming an interlayer insulating layer formed of a material having a different etching selectivity on the metal layer including the photoresist pattern; Planarizing the interlayer insulating film to expose a surface of the photoresist pattern; Removing the photoresist pattern; Etching the metal layer using the remaining interlayer insulating layer to form a metal wiring; And removing the metal etching pattern.

본 발명의 제조 방법에 있어서, 상기 금속층은 알루미늄으로 형성하며, 상기 층간 절연막은 TEOS와 SOG를 순차적으로 적층하여 형성한다. 여기서 상기 층간 절연막의 식각공정은 TEOS와 SOG의 식각 선택비를 1:1의 조건으로 하는데, 이때 식각 공정은 CF4을60∼70sccm, O2를 20∼30 sccm, 90∼110mTorr의 반응 챔버내 압력, 90∼110Watts의 전력 세기 조건으로 진행한다.In the manufacturing method of the present invention, the metal layer is formed of aluminum, and the interlayer insulating film is formed by sequentially stacking TEOS and SOG. Here, the etching process of the interlayer insulating film has an etching selectivity ratio of TEOS and SOG of 1: 1, in which the etching process is performed in a reaction chamber of 60 to 70 sccm of CF 4 , 20 to 30 sccm of O 2 , and 90 to 110 mTorr. Pressure, power intensity conditions of 90-110 Watts.

또한, 본 발명의 제조 방법에 있어서, 상기 음각 포토레지스트 패턴은 0.5㎛ 이하로 형성한다.In addition, in the manufacturing method of the present invention, the negative photoresist pattern is formed to 0.5㎛ or less.

본 발명의 제조 방법에 있어서, 상기 금속층 식각 공정후 금속 배선 측면에는 식각 방지용막이 형성되어 있다.In the manufacturing method of the present invention, an etching preventing film is formed on the side surface of the metal wiring after the metal layer etching process.

본 발명의 제조 방법에 있어서, 상기 금속층 식각 공정은 Cl2를 60∼70sccm, BCl3를 30∼40sccm, O3를 30∼50sccm, 9∼11mTorr의 반응 챔버내 압력, 40∼60Watts의 고주파 바이어스 전력 세기의 조건으로 진행한다.In the manufacturing method of the present invention, the metal layer etching process is performed in the reaction chamber of Cl 2 60 to 70 sccm, BCl 3 30 to 40 sccm, O 3 30 to 50 sccm, 9 to 11 mTorr, 40 to 60 Watts high frequency bias power Proceed to the terms of strength.

본 발명은 금속층 식각 공정시 O2가스를사용하여 금속 배선에 보호막을 형성하므로써 식각용 마스크로 사용되는 산화막과 포토레지스트와의 선택비를 증가시켜 금속층 위에 형성되는 포토레지스트의 두께를 최소 두께, 즉 0.5㎛ 이하로 형성할 수 있다. 이로 인해 포토레지스트 근접 효과 또한 동시에 감소하기 때문에 조밀한 패턴 영역과 그렇지 않은 부분에서도 메탈라인의 임계 선폭 차이가 없어지게 되어 금속 배선 공정의 신뢰성을 높일 수 있다The present invention increases the selectivity between the oxide film used as an etching mask and the photoresist by forming a protective film on the metal wiring using O 2 gas during the metal layer etching process, thereby reducing the thickness of the photoresist formed on the metal layer to a minimum thickness. It can be formed in 0.5 micrometer or less. As a result, the proximity effect of the photoresist is also reduced, thereby eliminating the difference in the critical line width of the metal line even in the dense pattern area and the non-part area, thereby increasing the reliability of the metal wiring process.

이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 6은 본 발명에 따른 반도체 장치의 금속 배선 구조를 형성하기 위한 공정 순서도이다.1 to 6 are process flowcharts for forming a metal wiring structure of a semiconductor device according to the present invention.

본 발명의 제조 공정은 도 1에 나타난 바와 같이 반도체 소자와 상부 구조물을 절연하기 위한 층간 절연막(10) 위에 Al 합금으로 이루어진 금속층(12)을 증착한다. 그 다음 금속층(12) 위에 금속 배선층이 형성되지 않도록 하기 위한 사진 공정을 실시하여 음각성 포토레지스트 패턴(14)을 형성한다.In the manufacturing process of the present invention, as shown in FIG. 1, a metal layer 12 made of Al alloy is deposited on the interlayer insulating film 10 for insulating the semiconductor device and the upper structure. Next, a photo process for preventing the metal wiring layer from being formed on the metal layer 12 is performed to form the negative photoresist pattern 14.

도 2에 나타난 바와 같이 포토레지스트 패턴(14)을 포함한 금속층(12) 전면에 층간 절연막을 형성한다. 이때, 층간 절연막은 식각 선택비가 다른 물질로서 500∼1000Å 두께의 TEOS막(16)과 그 위에 6000Å두께의 SOG막(18)을 증착한다. 그리고, CMP 공정으로 SOG막(18)의 표면을 평탄화한 후에 500℃에서 경화시킨다.As shown in FIG. 2, an interlayer insulating film is formed on the entire surface of the metal layer 12 including the photoresist pattern 14. At this time, the interlayer insulating film is formed of a TEOS film 16 having a thickness of 500 to 1000 占 and a SOG film 18 having a 6,000 占 thick thereon as a material having a different etching selectivity. Then, the surface of the SOG film 18 is planarized by a CMP process and then cured at 500 占 폚.

그 다음 도 3에 나타나 바와 같이 층간 절연막을 이루는 SOG막(18)과 TEOS막(16)에 전면 식각 공정을 실시하여 포토레지스트 패턴(14)의 표면이 노출될 때까지 SOG막(18)과 TEOS막(16)을 식각한다. 이때, TEOS막(16)과 SOG막(18)은 식각 선택비를 1:1의 조건으로 하며, 더욱 상세하게는 CF4을60∼70sccm, O2를 20∼30 sccm, 90∼110mTorr의 반응 챔버내 압력, 90∼110Watts의 전력 세기로 식각 공정을 진행한다. 이로 인해 포토레지스트 패턴(14) 측면에는 층간 절연막(16',18')으로 이루어진 금속 마스크 패턴(17)이 형성된다.Then, as shown in FIG. 3, the entire surface etching process is performed on the SOG film 18 and the TEOS film 16 forming the interlayer insulating film until the surface of the photoresist pattern 14 is exposed to the SOG film 18 and the TEOS. The film 16 is etched. In this case, the TEOS film 16 and the SOG film 18 have an etching selectivity of 1: 1. More specifically, the reaction of CF 4 with 60 to 70 sccm, O 2 with 20 to 30 sccm and 90 to 110 mTorr is performed. The etching process is carried out at a pressure in the chamber and a power intensity of 90 to 110 Watts. As a result, a metal mask pattern 17 including interlayer insulating layers 16 ′ and 18 ′ is formed on the side surface of the photoresist pattern 14.

이어서 도4에 나타난 바와 같이 포토레지스트 패턴(14)을 제거하여 금속층(12) 표면을 개방하는 개구부(14')를 형성한다. 이 개구부(14')는 금속 배선이 형성될 부분이다.Next, as shown in FIG. 4, the photoresist pattern 14 is removed to form an opening 14 ′ that opens the surface of the metal layer 12. This opening portion 14 'is a portion where a metal wiring is to be formed.

그리고, 도 5에 나타난 바와 같이 층간 절연막(16',18')으로 이루어진 금속 마스크 패턴(17)을 이용하여 하부의 금속층(12)을 선택 식각한다. 이때, 식각 마스크로 산화막을 사용하기 때문에 금속 배선 측면에 보호막으로서 카본 폴리머를 형성할 수 없다. 그러므로, 본 발명은 다음과 같은 식각 공정을 실시하는데, 이 식각 공정은 Cl2를 60∼70sccm, BCl3를 30∼40sccm, O3를 30∼50sccm, 9∼11mTorr의 반응 챔버내 압력, 40∼60Watts의 고주파 바이어스 전력 세기의 조건으로 한다. 이에 따라 식각 공정시 O3가스에 의해 금속 배선(12') 측면에 얇은 Al2O3으로 이루어진 보호막(20)을 형성한다.As shown in FIG. 5, the lower metal layer 12 is selectively etched using the metal mask pattern 17 formed of the interlayer insulating layers 16 ′ and 18 ′. At this time, since an oxide film is used as an etching mask, a carbon polymer cannot be formed as a protective film on the metal wiring side surface. Therefore, the present invention performs the following etching process, which includes 60 to 70 sccm of Cl 2 , 30 to 40 sccm of BCl 3 , 30 to 50 sccm of O 3 , and pressure in the reaction chamber of 9 to 11 mTorr, 40 to A condition of high frequency bias power strength of 60 Watts is used. Accordingly, during the etching process, a protective film 20 made of thin Al 2 O 3 is formed on the side surface of the metal wiring 12 ′ by the O 3 gas.

계속해서 금속층(12) 식각 공정을 실시하여 상기 보호막(20)에 의해 금속 식각 마스크(17)에 셀프얼라인하는 금속 배선(12')을 형성한다. 그리고, 금속 식각 마스크(17)를 제거하면 도 6에 나타난 바와 같이 절연막(10) 위에는 금속 배선(12')만이 남겨진다.Subsequently, the metal layer 12 is etched to form metal lines 12 ′ self-aligning to the metal etch mask 17 by the passivation layer 20. When the metal etching mask 17 is removed, only the metal wiring 12 ′ remains on the insulating film 10 as shown in FIG. 6.

상술한 바와 같이 본 발명에 의하면, 금속 식각용 마스크 패턴을 포토레지스트로 직접 접촉시켜 패터닝하는 종래 기술 대신에 산화막으로 패턴을 형성하여 금속층 식각 공정시 포토레지스트의 카본이 잔여되지 않으므로 금속 배선 측면에 카본 폴리머가 쌓이지 않게 된다. 또한 금속층 식각 공정시 O2가스를사용하여 금속 배선에 보호막을 형성하므로써 식각용 마스크로 사용되는 산화막과 포토레지스트와의 선택비를 증가시켜 금속층 위에 형성되는 포토레지스트의 두께를 최소 두께, 즉 0.5㎛ 이하로 형성할 수 있다. 이로 인해 포토레지스트 근접 효과 또한 동시에 감소하기 때문에 조밀한 패턴 영역과 그렇지 않은 부분에서도 메탈라인의 임계 선폭 차이가 없어지게 되어 금속 배선 공정의 신뢰성을 높일 수 있다. 특히 금속 배선 공정이 많이 요구되는 비메모리 반도체 장치의 경우 사진 공정에서 I-Line 장비로 값비싼 자외선 장비를 대신할 수 있기 때문에 금속 식각시 과도 식각 또는 브릿지로 인한 수율 감소를 방지할 수 있는 효과가 있다.As described above, according to the present invention, instead of the conventional technique of directly contacting and patterning a metal etching mask pattern with a photoresist, a pattern is formed of an oxide film so that carbon of the photoresist does not remain during the metal layer etching process. The polymer will not accumulate. In addition, by forming a protective film on the metal wiring by using O 2 gas during the metal layer etching process, the selectivity between the oxide film and the photoresist used as an etching mask is increased to minimize the thickness of the photoresist formed on the metal layer, that is, 0.5 μm. It can form below. As a result, the proximity effect of the photoresist is also reduced, thereby eliminating the difference in the critical line width of the metal line even in the dense pattern area and the non-part area, thereby increasing the reliability of the metal wiring process. In particular, non-memory semiconductor devices, which require a lot of metal wiring processes, can replace expensive ultraviolet equipment with I-Line equipment in the photolithography process, which can prevent a decrease in yield due to excessive etching or bridge during metal etching. have.

Claims (8)

반도체 소자와 상부 구조물을 절연하기 위한 층간 절연막 위에 금속층을 증착하는 단계; 상기 금속층위에 금속 배선층이 형성되지 않도록 음각 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 포함한 금속층 위에 식각 선택비가 다른 다층의 물질로 이루어진 층간 절연막을 형성하는 단계; 상기 포토레지스트 패턴의 표면이 노출되도록 상기 층간 절연막을 평탄화하는 단계; 상기 포토레지스트 패턴을 제거하는 단계; 잔여된 층간 절연막을 식각 마스크 패턴으로 사용하여 금속층을 식각하는 단계; 및 상기 식각 마스크 패턴을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.Depositing a metal layer on the interlayer insulating film for insulating the semiconductor device and the upper structure; Forming a negative photoresist pattern such that a metal wiring layer is not formed on the metal layer; Forming an interlayer insulating layer made of a multilayer material having different etching selectivity on the metal layer including the photoresist pattern; Planarizing the interlayer insulating film to expose a surface of the photoresist pattern; Removing the photoresist pattern; Etching the metal layer using the remaining interlayer insulating film as an etching mask pattern; And removing the etch mask pattern. 제1항에 있어서, 상기 금속층은 알루미늄으로 형성하는 특징으로 하는 반도체 장치의 금속 배선 형성 방법.The method of claim 1, wherein the metal layer is formed of aluminum. 제1항에 있어서, 상기 층간 절연막은 TEOS와 SOG를 순차적으로 적층하여 형성하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.The method of claim 1, wherein the interlayer insulating film is formed by sequentially stacking TEOS and SOG. 제1항 내지 제3항에 있어서, 상기 층간 절연막의 식각공정은 TEOS와 SOG의 식각 선택비를 1:1의 조건으로 하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.The method of claim 1, wherein the etching of the interlayer insulating film is performed by using an etching selectivity ratio of TEOS and SOG at a ratio of 1: 1. 제4항에 있어서, 상기 층간 절연막 식각 공정은 CF4을 60~70sccm, O2를 20~30 sccm, 90~110mTorr의 반응 챔버내 압력, 90~110Watts의 전력 세기 조건으로 진행하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.The method of claim 4, wherein the interlayer insulating film etching process is performed at 60 to 70 sccm of CF 4 , 20 to 30 sccm of O 2 , a pressure in a reaction chamber of 90 to 110 mTorr, and a power intensity of 90 to 110 Watts. Metal wiring formation method of a semiconductor device. 제1항에 있어서, 상기 음각 포토레지스트 패턴은 0.5㎛ 이하로 형성하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.The method of claim 1, wherein the negative photoresist pattern is formed to be 0.5 μm or less. 제1항에 있어서, 상기 금속층 식각 공정시 금속 배선 측면에는 식각 방지용막이 형성되어 있는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.The method of claim 1, wherein an etching preventing film is formed on a side surface of the metal wiring during the metal layer etching process. 제1항에 있어서, 상기 금속층 식각 공정은 Cl2를 60~70sccm, BCl3를 30~40sccm, O3를 30~50sccm, 9~11mTorr의 반응 챔버내 압력, 40~60Watts의 고주파 바이어스 전력 세기의 조건으로 진행하는 것을 특징으로 하는 반도체 장치의 금속 배선 형성 방법.According to claim 1, wherein the metal layer etching process is Cl 2 60 ~ 70sccm, BCl 3 30 ~ 40sccm, O 3 30 ~ 50sccm, pressure in the reaction chamber of 9 ~ 11mTorr, high frequency bias power strength of 40 ~ 60Watts It progresses on condition, The metal wiring formation method of the semiconductor device characterized by the above-mentioned.
KR1019970082290A 1997-12-31 1997-12-31 Method for manufacturing metal interconnection of semiconductor device KR100268709B1 (en)

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