KR100442782B1 - a method for manufacturing of semiconductor device - Google Patents

Abstract

The present invention discloses a capacitor manufacturing method of a semiconductor device capable of maximizing the electrode surface area to implement a large capacity capacitor. The disclosed method includes forming an interlayer insulating film having a contact hole on a semiconductor substrate; Forming a first conductive layer on the interlayer insulating film to fill the contact hole; Alternately stacking a first insulating film and a second conductive layer on the first conductive layer a plurality of times; First patterning the stacked first insulating layer and the second conductive layer; Forming a third conductive layer in the form of a sidewall spacer on both sidewalls of the first patterned laminated film; Second patterning the stacked first insulating layer and the second conductive layer such that an opening for exposing the first conductive layer is formed while the first patterned laminated film is bisected; Removing the first insulating film; Depositing a second insulating film on the third conductive layer, the second conductive layer and the first conductive layer, and then etching the entire surface of the second insulating film to expose the third conductive layer and the first conductive layer; Depositing a fourth conductive layer on the second insulating layer to be disposed outside the third conductive layer while being disposed between the second conductive layers via the second insulating layer; Forming a storage electrode including first to fourth conductive layers by etching the fourth conductive layer on the entire surface and simultaneously etching a portion of the first conductive layer; Removing the second insulating film; And sequentially forming a dielectric film and a plate electrode on the storage electrode.

Description

A method for manufacturing a semiconductor device of a semiconductor device

The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device capable of forming a large capacity capacitor by maximizing an effective area per unit cell.

In general, as the integration of semiconductor memory devices has progressed, large-capacity capacitors have been required. Therefore, from various angles, such as increasing the effective area of capacitors, thinning the dielectric film thickness of capacitors, or developing dielectric films with high dielectric constants. Many studies have been conducted.

Efforts to increase the effective area of capacitors have led to the proposal of three-dimensional capacitors, which include a fin structure, a cylindrical structure, and a trench structure.

Hereinafter, a method of manufacturing a capacitor of a conventional semiconductor device will be described with reference to the accompanying drawings.

1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a conventional semiconductor device.

As shown in FIG. 1A, a first interlayer insulating film 12 is formed on the semiconductor substrate 11, a first interlayer insulating film 12 is formed on the semiconductor substrate 11, and the first interlayer insulating film 12 is formed. ) Is selectively etched to form a plurality of contact holes 13.

As shown in FIG. 1B, the first polysilicon layer 14 and the first insulating layer 15 are sequentially formed on the first interlayer insulating layer 12 including the contact hole 13, and then a photolithography process is used. Thus, the first polysilicon layer 14 and the first insulating layer 15 are selectively patterned.

As shown in FIG. 1C, a second polysilicon layer is deposited on the first insulating layer 15 including the first interlayer insulating layer 12, and the first polysilicon layer 14 and A second polysilicon layer sidewall 16 is formed on the side of the first insulating layer 15.

The first insulating layer 15 is removed to form a capacitor storage electrode 17 having a cylinder shape.

As shown in FIG. 1D, a dielectric material is deposited on the storage electrode 17 to form a dielectric film 18, a third polysilicon layer is deposited on the dielectric film 18, and then patterned to form a capacitor. The plate electrode 18 is formed to complete the stacked capacitor.

However, as the integration of semiconductor memory devices has progressed, a large capacity capacitor has been required. Accordingly, the effective area of the capacitor has to be increased.

That is, according to the conventional method of manufacturing a capacitor of a semiconductor device, it is increasingly difficult to secure the capacity of a capacitor per unit cell.

Disclosure of Invention The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a capacitor of a semiconductor device capable of increasing capacitance by increasing an effective surface area per unit cell.

1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a conventional semiconductor device.

2A through 2C are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 101 interlayer insulating film

102: first polysilicon layer 103: first insulating film

104: second polysilicon layer 105: second insulating film

106: third polysilicon layer 107: third insulating film

108: fourth polysilicon layer 109: fourth insulating film

110: fifth polysilicon layer spacer 111: fifth insulating film

112: sixth polysilicon layer 113: storage electrode

A capacitor manufacturing method of a semiconductor device of the present invention for achieving the above object comprises the steps of forming an interlayer insulating film having a contact hole on the semiconductor substrate; Forming a first conductive layer on the interlayer insulating film to fill the contact hole; Alternately stacking a first insulating film and a second conductive layer on the first conductive layer a plurality of times; First patterning the stacked first insulating layer and the second conductive layer; Forming a third conductive layer in the form of a sidewall spacer on both sidewalls of the first patterned laminated film; Second patterning the stacked first insulating layer and the second conductive layer such that an opening for exposing the first conductive layer is formed while the first patterned laminated film is bisected; Removing the first insulating film; Depositing a second insulating film on the third conductive layer, the second conductive layer and the first conductive layer, and then etching the entire surface of the second insulating film to expose the third conductive layer and the first conductive layer; Depositing a fourth conductive layer on the second insulating layer to be disposed outside the third conductive layer while being disposed between the second conductive layers via the second insulating layer; Forming a storage electrode including first to fourth conductive layers by etching the fourth conductive layer on the entire surface and simultaneously etching a portion of the first conductive layer; Removing the second insulating film; And sequentially forming a dielectric film and a plate electrode on the storage electrode.

In this case, the removing of the first insulating layer is preferably performed by a wet etching process.

Hereinafter, a method of manufacturing a capacitor of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2C are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, after forming an interlayer insulating film 101 on a semiconductor substrate 100 having a predetermined lower structure, the interlayer insulating film 101 is selectively etched to form a predetermined portion of the substrate, for example, junction regions. A plurality of contact holes each exposed are formed.

Then, after depositing the first polysilicon layer 102 on the interlayer insulating film 101 to fill the contact holes, the insulating film and the polysilicon layer on the first polysilicon layer 102 alternately a plurality of times. Laminated. For example, on the first polysilicon layer 102, a first insulating film 103, a second polysilicon layer 104, a second insulating film 105, a third polysilicon layer 106, The third insulating film 107, the fourth polysilicon layer 108, and the fourth insulating film 109 are sequentially formed.

Next, the fourth insulating film 109, the fourth polysilicon layer 108, the third insulating film 107, the third polysilicon layer 106, the second insulating film 105, the second polysilicon layer 104, and the like. The first insulating film 103 is patterned.

Next, after depositing a fifth polysilicon layer on the patterned layered film and the first polysilicon layer 102, the first layer is formed by etching the entire surface to form sidewall spacers on both sidewalls of the patterned layered layer. Fifth polysilicon layer spacers that connect the sides of the second, third, and fourth polysilicon layers 104, 106, 108, including the third and fourth insulating films 103, 105, 107, and 109. Forms 110.

Referring to FIG. 2B, the fourth insulating layer 109 and the fourth polysilicon layer may be formed using a photolithography process so that an opening for exposing the first polysilicon layer 102 may be formed while the first patterned laminate is divided. 108, the third insulating film 107, the third polysilicon layer 106, the second insulating film 105, the second polysilicon layer 104, and the first insulating film 103 are second patterned. Thereafter, the first, second, third, and fourth insulating layers 103, 105, 107, and 109 are removed by a wet etching process.

Next, the second, third, and fourth polysilicon layers 104 connected to the first polysilicon layer 102, the fifth polysilicon layer spacer 110, and the fifth polysilicon layer spacer 110 ( After the fifth insulating film 111 is formed on the surfaces of 106 and 108, the entire surface is etched.

Then, after depositing the sixth polysilicon layer 112 on the fifth insulating film 111, the entire surface is etched, and subsequently, a part of the interlayer insulating film 101 is removed to form a separation between the cells. . Here, the sixth polysilicon layer 112 is formed between the first polysilicon layer 102 and the second polysilicon layer 104, the second polysilicon layer 104 and the first interlayer via the fifth insulating layer 111. It is formed between the three polysilicon layers 106, between the third polysilicon layer 106 and the fourth polysilicon layer 108, and on the outside of the fifth polysilicon layer spacer 110, respectively.

Referring to FIG. 2C, a wet etching process may be performed on the substrate result to completely remove the fifth insulating layer, and thereby, the first, second, third, fourth, and sixth polysilicon layers 102 and 104. The storage electrode 113 is formed of (106) 108 (112) and the fifth polysilicon layer spacer (110).

Subsequently, although not shown, a dielectric film is formed on the storage electrode 113 and a plate electrode made of a seventh polysilicon layer is formed on the dielectric film to complete the capacitor of the present invention.

As described above, according to the method of the present invention, the effective surface area of the storage electrode can be maximized, so that a large capacity capacitor required by a highly integrated semiconductor device can be realized. It can be changed.

Claims (4)

Forming an interlayer insulating film having a contact hole on the semiconductor substrate; Forming a first conductive layer on the interlayer insulating film to fill the contact hole; Alternately stacking a first insulating film and a second conductive layer on the first conductive layer a plurality of times; First patterning the stacked first insulating layer and the second conductive layer; Forming a third conductive layer in the form of a sidewall spacer on both sidewalls of the first patterned laminated film; Second patterning the stacked first insulating layer and the second conductive layer such that an opening for exposing the first conductive layer is formed while the first patterned laminated film is bisected; Removing the first insulating film; Depositing a second insulating film on the third conductive layer, the second conductive layer and the first conductive layer, and then etching the entire surface of the second insulating film to expose the third conductive layer and the first conductive layer; Depositing a fourth conductive layer on the second insulating layer to be disposed outside the third conductive layer while being disposed between the second conductive layers via the second insulating layer; Forming a storage electrode including first to fourth conductive layers by etching the fourth conductive layer on the entire surface and simultaneously etching a portion of the first conductive layer; Removing the second insulating film; And And sequentially forming a dielectric film and a plate electrode on the storage electrode. The method of claim 1, wherein the removing of the first insulating layer is performed by a wet etching process. delete delete