KR100391068B1 - 반도체 집적회로 - Google Patents

반도체 집적회로 Download PDF

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Publication number
KR100391068B1
KR100391068B1 KR10-2000-0072239A KR20000072239A KR100391068B1 KR 100391068 B1 KR100391068 B1 KR 100391068B1 KR 20000072239 A KR20000072239 A KR 20000072239A KR 100391068 B1 KR100391068 B1 KR 100391068B1
Authority
KR
South Korea
Prior art keywords
output
semiconductor integrated
signal
integrated circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2000-0072239A
Other languages
English (en)
Korean (ko)
Other versions
KR20010096513A (ko
Inventor
타니무라마사아키
Original Assignee
미쓰비시덴키 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 미쓰비시덴키 가부시키가이샤 filed Critical 미쓰비시덴키 가부시키가이샤
Publication of KR20010096513A publication Critical patent/KR20010096513A/ko
Application granted granted Critical
Publication of KR100391068B1 publication Critical patent/KR100391068B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
KR10-2000-0072239A 2000-04-11 2000-12-01 반도체 집적회로 Expired - Fee Related KR100391068B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000109917A JP2001297600A (ja) 2000-04-11 2000-04-11 半導体集積回路およびそのテスト方法
JP2000-109917 2000-04-11

Publications (2)

Publication Number Publication Date
KR20010096513A KR20010096513A (ko) 2001-11-07
KR100391068B1 true KR100391068B1 (ko) 2003-07-12

Family

ID=18622525

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2000-0072239A Expired - Fee Related KR100391068B1 (ko) 2000-04-11 2000-12-01 반도체 집적회로

Country Status (4)

Country Link
US (1) US6479363B1 (enExample)
JP (1) JP2001297600A (enExample)
KR (1) KR100391068B1 (enExample)
DE (1) DE10062081A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3874653B2 (ja) * 2001-11-29 2007-01-31 富士通株式会社 圧縮テスト機能を有するメモリ回路
KR100564033B1 (ko) * 2003-12-05 2006-03-23 삼성전자주식회사 단일 버퍼 선택 입력 단자를 가지는 반도체 메모리 및반도체 메모리 테스트 방법
KR100583152B1 (ko) * 2004-02-19 2006-05-23 주식회사 하이닉스반도체 데이터 억세스타임 측정모드를 갖는 반도체 메모리 소자
DE102004024668A1 (de) * 2004-05-18 2005-12-15 Infineon Technologies Ag Verfahren zum Testen von elektronischen Schaltungseinheiten und Testvorrichtung
JP4540433B2 (ja) * 2004-09-06 2010-09-08 ルネサスエレクトロニクス株式会社 入出力縮退回路
KR20080033671A (ko) * 2006-10-13 2008-04-17 삼성전자주식회사 테스트 사이클을 감소시키는 반도체 메모리 장치 및 테스트방법
JP2009070456A (ja) * 2007-09-12 2009-04-02 Renesas Technology Corp 半導体記憶装置
US7631233B2 (en) 2007-10-07 2009-12-08 United Memories, Inc. Data inversion register technique for integrated circuit memory testing
JP5612249B2 (ja) * 2008-01-31 2014-10-22 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5301155A (en) * 1990-03-20 1994-04-05 Mitsubishi Denki Kabushiki Kaisha Multiblock semiconduction storage device including simultaneous operation of a plurality of block defect determination circuits
JP3409527B2 (ja) 1995-08-17 2003-05-26 富士通株式会社 半導体記憶装置
JP2833563B2 (ja) 1996-01-23 1998-12-09 日本電気株式会社 半導体記憶装置
US6046943A (en) * 1998-03-10 2000-04-04 Texas Instuments Incorporated Synchronous semiconductor device output circuit with reduced data switching

Also Published As

Publication number Publication date
DE10062081A1 (de) 2001-10-18
JP2001297600A (ja) 2001-10-26
KR20010096513A (ko) 2001-11-07
US6479363B1 (en) 2002-11-12

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