KR100389549B1 - 템포럴 및 넌템포럴 명령어에 대한 공유 캐시 구조 - Google Patents

템포럴 및 넌템포럴 명령어에 대한 공유 캐시 구조 Download PDF

Info

Publication number
KR100389549B1
KR100389549B1 KR10-2000-7010799A KR20007010799A KR100389549B1 KR 100389549 B1 KR100389549 B1 KR 100389549B1 KR 20007010799 A KR20007010799 A KR 20007010799A KR 100389549 B1 KR100389549 B1 KR 100389549B1
Authority
KR
South Korea
Prior art keywords
data
cache
temporal
bit
cache memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2000-7010799A
Other languages
English (en)
Korean (ko)
Other versions
KR20010042262A (ko
Inventor
팔랑카살바도르
쿠레이니란잔엘.
나랑앙가드
펜트코브스키블라드미르
사이스티브
Original Assignee
인텔 코오퍼레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인텔 코오퍼레이션 filed Critical 인텔 코오퍼레이션
Publication of KR20010042262A publication Critical patent/KR20010042262A/ko
Application granted granted Critical
Publication of KR100389549B1 publication Critical patent/KR100389549B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR10-2000-7010799A 1998-03-31 1999-03-24 템포럴 및 넌템포럴 명령어에 대한 공유 캐시 구조 Expired - Fee Related KR100389549B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/053,386 1998-03-31
US09/053,386 US6202129B1 (en) 1998-03-31 1998-03-31 Shared cache structure for temporal and non-temporal information using indicative bits
US9/053,386 1998-03-31

Publications (2)

Publication Number Publication Date
KR20010042262A KR20010042262A (ko) 2001-05-25
KR100389549B1 true KR100389549B1 (ko) 2003-06-27

Family

ID=21983863

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2000-7010799A Expired - Fee Related KR100389549B1 (ko) 1998-03-31 1999-03-24 템포럴 및 넌템포럴 명령어에 대한 공유 캐시 구조

Country Status (10)

Country Link
US (2) US6202129B1 (enExample)
EP (1) EP1066566B1 (enExample)
JP (1) JP4486750B2 (enExample)
KR (1) KR100389549B1 (enExample)
CN (1) CN1230750C (enExample)
AU (1) AU3364599A (enExample)
BR (1) BR9909295A (enExample)
RU (1) RU2212704C2 (enExample)
TW (1) TW573252B (enExample)
WO (1) WO1999050752A1 (enExample)

Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5978379A (en) 1997-01-23 1999-11-02 Gadzoox Networks, Inc. Fiber channel learning bridge, learning half bridge, and protocol
US6202129B1 (en) * 1998-03-31 2001-03-13 Intel Corporation Shared cache structure for temporal and non-temporal information using indicative bits
US6216215B1 (en) 1998-04-02 2001-04-10 Intel Corporation Method and apparatus for senior loads
US6542966B1 (en) * 1998-07-16 2003-04-01 Intel Corporation Method and apparatus for managing temporal and non-temporal data in a single cache structure
US7430171B2 (en) 1998-11-19 2008-09-30 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
US6560677B1 (en) * 1999-05-04 2003-05-06 International Business Machines Corporation Methods, cache memories, systems and computer program products for storing transient, normal, and locked entries in an associative cache memory
US6728835B1 (en) * 2000-08-30 2004-04-27 Unisys Corporation Leaky cache mechanism
US6681295B1 (en) * 2000-08-31 2004-01-20 Hewlett-Packard Development Company, L.P. Fast lane prefetching
US6668307B1 (en) * 2000-09-29 2003-12-23 Sun Microsystems, Inc. System and method for a software controlled cache
US6578111B1 (en) * 2000-09-29 2003-06-10 Sun Microsystems, Inc. Cache memory system and method for managing streaming-data
WO2002027498A2 (en) * 2000-09-29 2002-04-04 Sun Microsystems, Inc. System and method for identifying and managing streaming-data
US6598124B1 (en) * 2000-09-29 2003-07-22 Sun Microsystems, Inc. System and method for identifying streaming-data
US6766413B2 (en) * 2001-03-01 2004-07-20 Stratus Technologies Bermuda Ltd. Systems and methods for caching with file-level granularity
US6574708B2 (en) * 2001-05-18 2003-06-03 Broadcom Corporation Source controlled cache allocation
US6766389B2 (en) 2001-05-18 2004-07-20 Broadcom Corporation System on a chip for networking
US7287649B2 (en) * 2001-05-18 2007-10-30 Broadcom Corporation System on a chip for packet processing
US7239636B2 (en) 2001-07-23 2007-07-03 Broadcom Corporation Multiple virtual channels for use in network devices
US6823426B2 (en) * 2001-12-20 2004-11-23 Intel Corporation System and method of data replacement in cache ways
US7328328B2 (en) * 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
US7295555B2 (en) 2002-03-08 2007-11-13 Broadcom Corporation System and method for identifying upper layer protocol message boundaries
US7114043B2 (en) * 2002-05-15 2006-09-26 Broadcom Corporation Ambiguous virtual channels
US7269709B2 (en) * 2002-05-15 2007-09-11 Broadcom Corporation Memory controller configurable to allow bandwidth/latency tradeoff
US7266587B2 (en) * 2002-05-15 2007-09-04 Broadcom Corporation System having interfaces, switch, and memory bridge for CC-NUMA operation
US7035979B2 (en) * 2002-05-22 2006-04-25 International Business Machines Corporation Method and apparatus for optimizing cache hit ratio in non L1 caches
US7073030B2 (en) 2002-05-22 2006-07-04 International Business Machines Corporation Method and apparatus providing non level one information caching using prefetch to increase a hit ratio
US6904501B1 (en) * 2002-06-17 2005-06-07 Silicon Graphics, Inc. Cache memory for identifying locked and least recently used storage locations
US7934021B2 (en) 2002-08-29 2011-04-26 Broadcom Corporation System and method for network interfacing
US7346701B2 (en) 2002-08-30 2008-03-18 Broadcom Corporation System and method for TCP offload
US8180928B2 (en) 2002-08-30 2012-05-15 Broadcom Corporation Method and system for supporting read operations with CRC for iSCSI and iSCSI chimney
WO2004021626A2 (en) 2002-08-30 2004-03-11 Broadcom Corporation System and method for handling out-of-order frames
US7313623B2 (en) 2002-08-30 2007-12-25 Broadcom Corporation System and method for TCP/IP offload independent of bandwidth delay product
US7512498B2 (en) * 2002-12-31 2009-03-31 Intel Corporation Streaming processing of biological sequence matching
WO2005050455A1 (ja) * 2003-11-18 2005-06-02 Matsushita Electric Industrial Co., Ltd. キャッシュメモリ及びその制御方法
US7321954B2 (en) * 2004-08-11 2008-01-22 International Business Machines Corporation Method for software controllable dynamically lockable cache line replacement system
US20060101208A1 (en) * 2004-11-09 2006-05-11 Intel Corporation Method and apparatus for handling non-temporal memory accesses in a cache
US7356650B1 (en) * 2005-06-17 2008-04-08 Unisys Corporation Cache apparatus and method for accesses lacking locality
US7437510B2 (en) * 2005-09-30 2008-10-14 Intel Corporation Instruction-assisted cache management for efficient use of cache and memory
US7624257B2 (en) * 2005-11-30 2009-11-24 International Business Machines Corporation Digital data processing apparatus having hardware multithreading support including a register set reserved for special class threads
US20070150658A1 (en) * 2005-12-28 2007-06-28 Jaideep Moses Pinning locks in shared cache
US8527713B2 (en) * 2006-01-31 2013-09-03 Qualcomm Incorporated Cache locking without interference from normal allocations
GB0603552D0 (en) 2006-02-22 2006-04-05 Advanced Risc Mach Ltd Cache management within a data processing apparatus
WO2007097028A1 (ja) * 2006-02-27 2007-08-30 Fujitsu Limited Ｌｒｕ制御装置、ｌｒｕ制御方法およびｌｒｕ制御プログラム
US20080147989A1 (en) * 2006-12-14 2008-06-19 Arm Limited Lockdown control of a multi-way set associative cache memory
US7949834B2 (en) * 2007-01-24 2011-05-24 Qualcomm Incorporated Method and apparatus for setting cache policies in a processor
CN101595462B (zh) 2007-01-31 2012-04-25 高通股份有限公司 用以减少多级高速缓冲存储器层级中的掷出的设备和方法
US7793049B2 (en) * 2007-10-30 2010-09-07 International Business Machines Corporation Mechanism for data cache replacement based on region policies
US8108614B2 (en) * 2007-12-31 2012-01-31 Eric Sprangle Mechanism for effectively caching streaming and non-streaming data patterns
BRPI0822963B1 (pt) * 2008-07-23 2019-10-01 Micro Motion, Inc. Método para executar uma rotina de processamento utilizando uma memória externa e uma memória interna, e, sistema de processamento
US8364898B2 (en) * 2009-01-23 2013-01-29 International Business Machines Corporation Optimizing a cache back invalidation policy
US8312219B2 (en) * 2009-03-02 2012-11-13 International Business Machines Corporation Hybrid caching techniques and garbage collection using hybrid caching techniques
US9063825B1 (en) 2009-09-21 2015-06-23 Tilera Corporation Memory controller load balancing with configurable striping domains
US8560777B2 (en) * 2009-12-16 2013-10-15 Telefonaktiebolaget L M Ericsson (Publ) Method, server, computer program and computer program product for caching
US9323527B2 (en) * 2010-10-15 2016-04-26 International Business Machines Corporation Performance of emerging applications in a virtualized environment using transient instruction streams
EP2761480A4 (en) 2011-09-30 2015-06-24 Intel Corp APPARATUS AND METHOD FOR IMPLEMENTING MULTINIVE MEMORY HIERARCHY ON COMMON MEMORY CHANNELS
CN107391397B (zh) 2011-09-30 2021-07-27 英特尔公司 支持近存储器和远存储器访问的存储器通道
EP2761466B1 (en) 2011-09-30 2020-08-05 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy
EP2761464B1 (en) 2011-09-30 2018-10-24 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
US9122286B2 (en) * 2011-12-01 2015-09-01 Panasonic Intellectual Property Management Co., Ltd. Integrated circuit apparatus, three-dimensional integrated circuit, three-dimensional processor device, and process scheduler, with configuration taking account of heat
US9519549B2 (en) * 2012-01-11 2016-12-13 International Business Machines Corporation Data storage backup with lessened cache pollution
US8856455B2 (en) 2012-03-28 2014-10-07 International Business Machines Corporation Data cache block deallocate requests
US8874852B2 (en) 2012-03-28 2014-10-28 International Business Machines Corporation Data cache block deallocate requests in a multi-level cache hierarchy
CN103577480B (zh) * 2012-08-07 2017-05-31 中国银联股份有限公司 一种参数划分系统及其方法、一种业务处理系统及其方法
US9558121B2 (en) * 2012-12-28 2017-01-31 Intel Corporation Two-level cache locking mechanism
US9256539B2 (en) 2013-03-07 2016-02-09 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Sharing cache in a computing system
US9311239B2 (en) 2013-03-14 2016-04-12 Intel Corporation Power efficient level one data cache access with pre-validated tags
US20150095586A1 (en) * 2013-09-30 2015-04-02 Advanced Micro Devices , Inc. Storing non-temporal cache data
US11580125B2 (en) * 2015-05-08 2023-02-14 Adp, Inc. Information system with temporal data
US10379827B2 (en) 2016-12-29 2019-08-13 Intel Corporation Automatic identification and generation of non-temporal store and load operations in a dynamic optimization environment
US11681627B1 (en) * 2021-10-18 2023-06-20 Meta Platforms Technologies, Llc Distributed temporal cache for Systems on a Chip
US12072803B1 (en) * 2022-06-30 2024-08-27 Advanced Micro Devices, Inc. Systems and methods for tracking data cache miss requests with data cache tags

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471605A (en) * 1992-08-27 1995-11-28 Intel Corporation Apparatus for updating a multi-way set associative cache memory status array
US5493667A (en) * 1993-02-09 1996-02-20 Intel Corporation Apparatus and method for an instruction cache locking scheme

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US549366A (en) * 1895-11-05 Plow-protector
JPS5119453A (en) * 1974-08-08 1976-02-16 Fujitsu Ltd Patsufua memoriseigyohoshiki
JPS5534336A (en) * 1978-08-31 1980-03-10 Fujitsu Ltd Buffer memory control method
JPS58159285A (ja) * 1982-03-17 1983-09-21 Nec Corp バツフアメモリ制御方式
SU1304030A1 (ru) * 1985-06-19 1987-04-15 Войсковая Часть 25840 Устройство дл управлени доступом к пам ти от двух ЦВМ
JPH01133162A (ja) * 1987-11-18 1989-05-25 Fujitsu Ltd キャッシュメモリ制御方式
US4905141A (en) 1988-10-25 1990-02-27 International Business Machines Corporation Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification
JPH0358151A (ja) * 1989-07-26 1991-03-13 Nec Corp キャッシュメモリ装置
JPH0358252A (ja) * 1989-07-27 1991-03-13 Nec Corp キャッシュメモリ制御装置
JPH041838A (ja) * 1990-04-18 1992-01-07 Nec Corp キャッシュメモリ制御回路
JPH04215151A (ja) * 1990-12-13 1992-08-05 Nec Commun Syst Ltd キャッシュ制御方式
DE69224084T2 (de) * 1991-01-15 1998-07-23 Koninkl Philips Electronics Nv Rechneranordnung mit Mehrfachpufferdatencachespeicher und Verfahren dafür
GB2255211B (en) * 1991-04-25 1995-05-17 Intel Corp LRU pointer updating in a controller for two-way set associative cache
GB2256512B (en) * 1991-06-04 1995-03-15 Intel Corp Second level cache controller unit and system
JPH05165726A (ja) * 1991-12-12 1993-07-02 Nec Corp データ処理装置
JPH05233454A (ja) * 1992-02-24 1993-09-10 Hitachi Ltd キャッシュメモリ装置
US5353425A (en) * 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
US5434992A (en) 1992-09-04 1995-07-18 International Business Machines Corporation Method and means for dynamically partitioning cache into a global and data type subcache hierarchy from a real time reference trace
JPH06348595A (ja) * 1993-06-07 1994-12-22 Hitachi Ltd キャッシュ装置
JPH07281957A (ja) * 1994-04-15 1995-10-27 Hitachi Ltd キャッシュ記憶装置およびアクセス命令生成方法
US5826052A (en) 1994-04-29 1998-10-20 Advanced Micro Devices, Inc. Method and apparatus for concurrent access to multiple physical caches
JPH07334428A (ja) * 1994-06-14 1995-12-22 Toshiba Corp キャッシュメモリ
US5584014A (en) * 1994-12-20 1996-12-10 Sun Microsystems, Inc. Apparatus and method to preserve data in a set associative memory device
US5701426A (en) * 1995-03-31 1997-12-23 Bull Information Systems Inc. Data processing system and method using cache miss address prediction and forced LRU status in a cache memory to improve cache hit ratio
US5845317A (en) * 1995-11-17 1998-12-01 Micron Technology, Inc. Multi-way cache expansion circuit architecture
GB2311880A (en) * 1996-04-03 1997-10-08 Advanced Risc Mach Ltd Partitioned cache memory
US5829025A (en) * 1996-12-17 1998-10-27 Intel Corporation Computer system and method of allocating cache memories in a multilevel cache hierarchy utilizing a locality hint within an instruction
JPH10207767A (ja) * 1997-01-16 1998-08-07 Toshiba Corp ロック機能付キャッシュメモリ及びこのキャッシュメモリを備えたマイクロプロセッサ
US6434671B2 (en) * 1997-09-30 2002-08-13 Intel Corporation Software-controlled cache memory compartmentalization
US6223258B1 (en) * 1998-03-31 2001-04-24 Intel Corporation Method and apparatus for implementing non-temporal loads
US6105111A (en) * 1998-03-31 2000-08-15 Intel Corporation Method and apparatus for providing a cache management technique
US6205520B1 (en) * 1998-03-31 2001-03-20 Intel Corporation Method and apparatus for implementing non-temporal stores
US6202129B1 (en) * 1998-03-31 2001-03-13 Intel Corporation Shared cache structure for temporal and non-temporal information using indicative bits

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471605A (en) * 1992-08-27 1995-11-28 Intel Corporation Apparatus for updating a multi-way set associative cache memory status array
US5493667A (en) * 1993-02-09 1996-02-20 Intel Corporation Apparatus and method for an instruction cache locking scheme

Also Published As

Publication number Publication date
WO1999050752A1 (en) 1999-10-07
AU3364599A (en) 1999-10-18
WO1999050752A9 (en) 2000-05-25
EP1066566A4 (en) 2002-10-23
US6584547B2 (en) 2003-06-24
EP1066566A1 (en) 2001-01-10
US20020007441A1 (en) 2002-01-17
RU2212704C2 (ru) 2003-09-20
CN1230750C (zh) 2005-12-07
TW573252B (en) 2004-01-21
EP1066566B1 (en) 2006-11-02
JP4486750B2 (ja) 2010-06-23
BR9909295A (pt) 2000-12-05
KR20010042262A (ko) 2001-05-25
US6202129B1 (en) 2001-03-13
CN1295687A (zh) 2001-05-16
JP2002510085A (ja) 2002-04-02

Similar Documents

Publication Publication Date Title
KR100389549B1 (ko) 템포럴 및 넌템포럴 명령어에 대한 공유 캐시 구조
US6105111A (en) Method and apparatus for providing a cache management technique
US6219760B1 (en) Cache including a prefetch way for storing cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line
US6912623B2 (en) Method and apparatus for multithreaded cache with simplified implementation of cache replacement policy
US6990557B2 (en) Method and apparatus for multithreaded cache with cache eviction based on thread identifier
US7783837B2 (en) System and storage medium for memory management
US6292871B1 (en) Loading accessed data from a prefetch buffer to a least recently used position in a cache
US20100217937A1 (en) Data processing apparatus and method
US20070239938A1 (en) Area effective cache with pseudo associative memory
JPH0364893B2 (enExample)
EP1012723A1 (en) Cache hierarchy management with locality hints for different cache levels
US20060069843A1 (en) Apparatus and method for filtering unused sub-blocks in cache memories
KR100320974B1 (ko) 수직 캐시 계층구조에서 의사 정밀 아이-캐시의 포함 방법
CN1093961C (zh) 增强存储器性能的方法及数据处理系统
US7293141B1 (en) Cache word of interest latency organization
US11397680B2 (en) Apparatus and method for controlling eviction from a storage structure
US8176254B2 (en) Specifying an access hint for prefetching limited use data in a cache hierarchy
US20120102271A1 (en) Cache memory system and cache memory control method

Legal Events

Date Code Title Description
A201 Request for examination
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

FPAY Annual fee payment

Payment date: 20120601

Year of fee payment: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20130618

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20130618

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000